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Top Stories — June 18, 2015
Samsung to put 10nm chips into mass production by end of 2016
Samsung Semiconductor on Thursday announced that it will have 10-nanometer FinFET chips in volume production by the end of next year.
Power shift reflects the need for a new way of thinking
Handheld and smart devices are driving a methodology shift in power analysis. Mentor Graphics has recognized the need to calculate power values earlier in the design cycle, and has introduced the Veloce Power Application software to its portfolio to help SoC designers shave time off development and testing.
Intel CEO looks to 3D tech at display conference
Intel CEO Brian Krzanich touted the capabilities of his company's RealSense technology in a keynote address at the Society for Information Display conference in San Jose, California.
Custom Layout Designers Need New Tools for New and Expanding Markets
Now more than ever, time to market could mean the difference between so-so results and profitability. With that came the need to reduce design and verification timelines while still ensuring high-quality products.
It's blue skies for Jabil and its customers
While making printed circuit boards is still a big business for the St. Petersburg, Fla.-based Jabil, which boasts 90 plants in 24 countries around the world, the Blue Sky Center emphasizes that Jabil has progressed from being a board manufacturer to a full-service supply chain management firm.
Tackling Parameter Extraction for 16nm and Below
There are four reasons why parasitic parameter extraction is getting a lot harder for 16nm and below technology nodes: 1) 3D device geometries, such as the finFET, which result in more complex electrical fields around the device 2) multi-patterning, which causes increased variability; 3) a demand for 10X tighter levels of accuracy, and 4) increased levels of secrecy from foundries and designers.
New Applied PVD system targets TiN hardmasks for 10nm, 7nm chips
Applied Materials introduced the Applied Endura Cirrus HTX PVD, a physical vapor deposition system for creating titanium nitride hardmask films that could be used in fabricating 10-nanometer and 7nm chips.
Veloce Redefines Power Analysis Flow
Mentor Graphics Corp. released the Veloce® Power Application software that enables accurate, timely and efficient power analysis at the system, RTL and gate level for complex SoC designs.
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News & Features
Solid State Technology's Latest Issue
The June issue of SST features articles on Reduced defectivity and cost-of-ownership copper CMP cleans; A novel characterization technique for 3D structures; The impact of consumer demand for cutting-edge display technology on the gases market; The cost-down route to foldable display manufacture; How to drive profitability through better forecasting; and how emerging IoT impacts the semiconductor sector.
"Easy does it" — Fabs trim spending plans
Semiconductor capital expenditures (without fabless and backend) are expected to slow in rate, but continue to grow by 5.8 percent in 2015 (over US$66 billion) and 2.5 percent in 2016 (over $68 billion), according to the May update of the SEMI World Fab Forecast report. A significant part of this capex is fab equipment spending.
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Pete's Posts Blog
IoT, Healthcare and 5G to Drive RF and Microwave
Industry trends to the Internet of Things, advanced healthcare and 5G are good news for everyone involved in ...
IC Design
Custom Layout Designers Need New Tools for New and Expanding Markets
For a long time, digital was the darling of the semiconductor industry.
Applied Innovation
50 Years of Moore's Law
For 50 years, Moore's Law has served as a guide for technologists everywhere in the world, setting the ...
Materials Matters
On-Site Hydrogen Solutions: Smart, Reliable, and Flexible
Semiconductor manufacturers are seeking on-site hydrogen solutions as a result of increasing volumes of hydrogen usage and the ...
Ed's Threads
ALD of Crystalline High-K SHTO on Ge
Alternative channel materials (ACM) such as germanium (Ge) will need to be integrated into future CMOS ICs, and ...
Insights From Leading Edge
IFTLE 242 Advanced Packaging at the ConFab
At the recent ConFab meeting in Las Vegas, aside from all the talk about consolidation (see IFTLE 241), ...
Viewpoints: SEMI
SEMI Recognizes Leaders, Pushes Issues at Washington Forum
As Congress continued a busy spring session, SEMI hosted its annual Washington Forum event on April 28 & ...
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Our Sponsors
Solid State Watch: May 1-8, 2015
First quarter semiconductor sales up 6% compared to last year; New study suggests that rapid innovation in semiconductors provides hope for better economic times ahead; Microchip and GlobalFoundries announce new 55nm embedded NVM; ASE and TDK announce plans for joint venture agreement
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White Papers
RF-SOI Wafers for Wireless Applications
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
DFM: What is it and what will it do?
Everybody's talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
Via Doubling to Improve Yield
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
The Impact Of 14-nm Photomask Uncertainties on Computational Lithography Solutions
Certain measurement methodologies can be inaccurate even if they're precise, and there are known errors associated with certain system parameters.
A Study Of Model-Based Etch Bias Retarget For OPC
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
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