Experts at the table: Continued strong growth for semiconductor intellectual property (IP) through 2017 has been forecast by Semico Research. Semiconductor Manufacturing & Design invited Steve Roddy, Product Line Group Director, IP Group at Cadence, Bob Smith, Senior Vice President of Marketing and Business Development at Uniquify and Grant Pierce, CEO at Sonics to discuss how the IP landscape is changing and provide some perspectives, as the industry moves to new device architectures.
Top Stories Archive
The transition to 3D NAND is inevitable, but there is still plenty to be squeezed from 2D NAND technology. An Applied Materials-sponsored panel at IEDM discussed where the industry is today and where it’s headed.
Foundries, both pure-play and independent device manufacturers (IDM), rigorously compete for market share. One factor that helps them get and keep business is turnaround time (TAT). As technology nodes advance, achieving targeted production runtimes in the post-tapeout flow gets ever more challenging.
Should foundries establish and share best practices to manage sub-nanometer effects to improve yield and also manufacturability?
Devices used in safety critical applications such as automobiles need be known to work and have the ability to be regularly verified. Therefore, a very high-quality test is important as well as method to perform a built-in self-test.
Zvi Or-Bach, President and CEO of MonolithIC 3D, blogs that this is the “one learning” we can take away from IEDM 2013.
We report here empirical results demonstrating the electrical benefits of SOI-based FinFETs. There are benefits inherent in the elimination of dopant as the means to establish the effective device dimensions. However, significant compromise is unavoidable when using doping as a means of isolation, as in bulk-based FinFETs.
The electronics industry trend towards smaller and thinner form factors has ushered an era of significant changes in packaging materials. As these trends continue, innovative material solutions will be needed to address demanding requirements related to product integration, mobility, and reliability.
The process flows applied today for real product manufacturing are quite different from the process flows initially proposed for a universal 3D IC.
GLOBALFOUNDRIES, Open-Silicon and Amkor Technology have jointly exhibited a functional system-on-chip (SoC) solution on a 2.5D silicon interposer featuring two 28nm logic chips, with embedded ARM processors.
The HMC provides a breakthrough solution that delivers unmatched performance with the utmost reliability.
We have an interesting dynamic in the world of semiconductor training that has been in play since the financial crisis in 2008-2009.
It’s apparent that the world’s appetite for electronics has never been greater. That has increasingly taken the form of mobile electronics, including smartphones, tablets and tablets and the new “phablets.”
At Semicon West last week (and at The ConFab a few weeks ago) some key trends were clearly evident in the semiconductor industry.
You are currently browsing the archives for the Technology Features category.
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
How to tame data file sizes, address fractured data files creation and streamline data review techniques.