At IEDM 2014 last month in San Francisco, Applied Materials sponsored an evening panel discussion on the theme of “How do we continue past 7nm?”
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Before there were electrical engineers and standard definitions for the ampere, ohm and volt, entrepreneurs and scientists in the United Kingdom and the United States worked on the issue of improving communications between the Old World and the New World.
Multi-patterning lithography is a fact of life for many chipmakers. Experts in the fields of electronic design automation and lithography address the issues associated with the technology. Providing responses are David Abercrombie, Design for Manufacturing Program Manager, Mentor Graphics; Gary Zhang, Vice President Marketing, ASML Brion; and Dr. Donis Flagello of Nikon Research Corporation of America.
In another example of the old one-liner that “all that is old is new again,” the old technique of solid-source doping is being used by Intel for a critical process step in so-called “14nm node” finFET manufacturing.
At the 60th annual International Electron Devices Meeting this week in San Francisco, there was much buzz about the 14-nanometer FinFET papers being presented by IBM and Intel. Those papers were the subject of a press release two months in advance.
The presentations at this week’s 3D Architectures in Semiconductor Integration and Packaging conference could be summed up in a famous Facebook status.
Enabling NMOS using Ge channels for CMOS finFETs.
A new hardmask material, called Saphira, and accompanying processes was introduced Applied Materials. The material, which is transparent and offers high selectivity and good mechanical strength, could reduce manufacturing costs by 35% per module.
Intel’s “14nm-node” process uses air-gaps in dielectrics; direction disclosed four years ago.
Communications and energy-harvesting capabilities can be integrated into ubiquitous always-on smart nodes.
Determining an optimum sampling strategy comes down to weighing the cost of process control against the benefit of capturing the defect or other excursion in a timely manner.
A leading semiconductor foundry and an EDA vendor with design-for-yield (DFY) solutions have enjoyed a long-term partnership. Recently, they worked together to leverage DFY technologies for process technology development and design flow enhancement.
Recovering and reusing materials is becoming an increasingly essential consideration in order to ensure consistent quality, a stable supply of materials, and lower costs. On- and off-site options are reviewed for helium, argon, sulfuric acid and Xenon.
Flexible displays is a technological field that has been in R&D and pre-commercial development for several years, but what needs to happen to make volume production a reality, in areas including substrates, materials and production processes? Semiconductor Manufacturing & Design discussed the issues with Mac McDaniel, Director and Chief Marketing Officer, Display Business Group, Applied Materials, Michael Ciesinski, MD of the Flextech Alliance, and Keri Goodwin, Principal Scientist from the Centre for Process Innovation (CPI), in the UK.
Devices used in safety critical applications such as automobiles need be known to work and have the ability to be regularly verified. Therefore, a very high-quality test is important as well as method to perform a built-in self-test.
Zvi Or-Bach, President and CEO of MonolithIC 3D, blogs that this is the “one learning” we can take away from IEDM 2013.
We report here empirical results demonstrating the electrical benefits of SOI-based FinFETs. There are benefits inherent in the elimination of dopant as the means to establish the effective device dimensions. However, significant compromise is unavoidable when using doping as a means of isolation, as in bulk-based FinFETs.
The electronics industry trend towards smaller and thinner form factors has ushered an era of significant changes in packaging materials. As these trends continue, innovative material solutions will be needed to address demanding requirements related to product integration, mobility, and reliability.
The process flows applied today for real product manufacturing are quite different from the process flows initially proposed for a universal 3D IC.
GLOBALFOUNDRIES, Open-Silicon and Amkor Technology have jointly exhibited a functional system-on-chip (SoC) solution on a 2.5D silicon interposer featuring two 28nm logic chips, with embedded ARM processors.
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The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
How to tame data file sizes, address fractured data files creation and streamline data review techniques.