During system-level verification, it is imperative to verify that the software power control applications properly initialize power states and power domains.
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Circuit performance and silicon area improvements seen in new die stacks.
Handheld and smart devices are driving a methodology shift in power analysis. Mentor Graphics has recognized the need to calculate power values earlier in the design cycle, and has introduced the Veloce Power Application software to its portfolio to help SoC designers shave time off development and testing.
Mentor Graphics Corp. released the Veloce® Power Application software that enables accurate, timely and efficient power analysis at the system, RTL and gate level for complex SoC designs.
There are four reasons why parasitic parameter extraction is getting a lot harder for 16nm and below technology nodes: 1) 3D device geometries, such as the finFET, which result in more complex electrical fields around the device 2) multi-patterning, which causes increased variability; 3) a demand for 10X tighter levels of accuracy, and 4) increased levels of secrecy from foundries and designers.
At Display Week 2015, bigger is better. Smaller is better. And flexible may be best of all, for the era of wearable electronics.
Intel CEO Brian Krzanich touted the capabilities of his company’s RealSense technology in a keynote address at the Society for Information Display conference in San Jose, California.
Samsung Semiconductor on Thursday announced that it will have 10-nanometer FinFET chips in volume production by the end of next year.
Applied Materials introduced the Applied Endura Cirrus HTX PVD, a physical vapor deposition system for creating titanium nitride hardmask films that could be used in fabricating 10-nanometer and 7nm chips.
While making printed circuit boards is still a big business for the St. Petersburg, Fla.-based Jabil, which boasts 90 plants in 24 countries around the world, the Blue Sky Center emphasizes that Jabil has progressed from being a board manufacturer to a full-service supply chain management firm.
Determining an optimum sampling strategy comes down to weighing the cost of process control against the benefit of capturing the defect or other excursion in a timely manner.
A leading semiconductor foundry and an EDA vendor with design-for-yield (DFY) solutions have enjoyed a long-term partnership. Recently, they worked together to leverage DFY technologies for process technology development and design flow enhancement.
Recovering and reusing materials is becoming an increasingly essential consideration in order to ensure consistent quality, a stable supply of materials, and lower costs. On- and off-site options are reviewed for helium, argon, sulfuric acid and Xenon.
Flexible displays is a technological field that has been in R&D and pre-commercial development for several years, but what needs to happen to make volume production a reality, in areas including substrates, materials and production processes? Semiconductor Manufacturing & Design discussed the issues with Mac McDaniel, Director and Chief Marketing Officer, Display Business Group, Applied Materials, Michael Ciesinski, MD of the Flextech Alliance, and Keri Goodwin, Principal Scientist from the Centre for Process Innovation (CPI), in the UK.
Devices used in safety critical applications such as automobiles need be known to work and have the ability to be regularly verified. Therefore, a very high-quality test is important as well as method to perform a built-in self-test.
Zvi Or-Bach, President and CEO of MonolithIC 3D, blogs that this is the “one learning” we can take away from IEDM 2013.
We report here empirical results demonstrating the electrical benefits of SOI-based FinFETs. There are benefits inherent in the elimination of dopant as the means to establish the effective device dimensions. However, significant compromise is unavoidable when using doping as a means of isolation, as in bulk-based FinFETs.
The electronics industry trend towards smaller and thinner form factors has ushered an era of significant changes in packaging materials. As these trends continue, innovative material solutions will be needed to address demanding requirements related to product integration, mobility, and reliability.
The process flows applied today for real product manufacturing are quite different from the process flows initially proposed for a universal 3D IC.
GLOBALFOUNDRIES, Open-Silicon and Amkor Technology have jointly exhibited a functional system-on-chip (SoC) solution on a 2.5D silicon interposer featuring two 28nm logic chips, with embedded ARM processors.
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The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
How to tame data file sizes, address fractured data files creation and streamline data review techniques.