Cadence Design Systems is introducing the Modus Test Solution, a product that it touts as capable of reducing IC testing time and test costs, while improving profit margins for chips.
Top Stories Archive
Qualcomm reported net income of $1.5 billion for the fiscal first quarter ended December 27, down 24 percent from $2.0 billion a year ago. Revenue fell 19 percent to $5.8 billion, from $7.1 billion in the first quarter of fiscal 2015.
Knowm Inc., a start-up pioneering next-generation advanced computing architectures and technology, recently announced the availability of two new variations of memristors targeting different neuromorphic applications.
China has been successfully investing in technology to reach global competitiveness for many decades. Integrated circuit (IC) manufacturing technology is highly strategic for countries, enabling both economically-valuable commercial fabs as well as military power.
Intel reported net income of $11.4 billion on revenue of $55.4 billion for the year ended December 26, compared with net of $11.7 billion on revenue of $55.9 billion in 2014.
Lei Zhang, et al. from Pennsylvania State University—with collaborators from Rutgers University and University of Toledo—have found two new families of transparent conductive oxides (TCO) based on “correlated” electrons in ternary oxides of vanadium.
Low-cost IoT designs, which interface the edge of the real world to the Internet, mesh together several design domains. Individually, these design domains are challenging for today’s engineers. Bringing them all together to create an IoT product can place extreme pressure on design teams.
On the second day of the 12th annual 3D ASIP conference, the heavy hitters came out to talk. Attendees heard presentations from executives of Amkor Technology, the Defense Advanced Research Projects Agency (DARPA), Northrop Grumman, Taiwan Semiconductor Manufacturing, Teledyne Scientific & Imaging, and Xilinx, among other companies.
In a deal with significant implications for high-tech chemicals and materials, The Dow Chemical Company and E. I. du Pont de Nemours and Company (DuPont) have agreed to merge, forming the second largest chemical company in the world, behind BASF SE.
“It’s not about the sensors,” Nandini (Nan) Nayak, managing director of design strategy at Fjord, said Thursday morning (December 3) in a keynote address at the Designers of Things conference in San Jose, Calif.
Determining an optimum sampling strategy comes down to weighing the cost of process control against the benefit of capturing the defect or other excursion in a timely manner.
A leading semiconductor foundry and an EDA vendor with design-for-yield (DFY) solutions have enjoyed a long-term partnership. Recently, they worked together to leverage DFY technologies for process technology development and design flow enhancement.
Recovering and reusing materials is becoming an increasingly essential consideration in order to ensure consistent quality, a stable supply of materials, and lower costs. On- and off-site options are reviewed for helium, argon, sulfuric acid and Xenon.
Flexible displays is a technological field that has been in R&D and pre-commercial development for several years, but what needs to happen to make volume production a reality, in areas including substrates, materials and production processes? Semiconductor Manufacturing & Design discussed the issues with Mac McDaniel, Director and Chief Marketing Officer, Display Business Group, Applied Materials, Michael Ciesinski, MD of the Flextech Alliance, and Keri Goodwin, Principal Scientist from the Centre for Process Innovation (CPI), in the UK.
Devices used in safety critical applications such as automobiles need be known to work and have the ability to be regularly verified. Therefore, a very high-quality test is important as well as method to perform a built-in self-test.
Zvi Or-Bach, President and CEO of MonolithIC 3D, blogs that this is the “one learning” we can take away from IEDM 2013.
We report here empirical results demonstrating the electrical benefits of SOI-based FinFETs. There are benefits inherent in the elimination of dopant as the means to establish the effective device dimensions. However, significant compromise is unavoidable when using doping as a means of isolation, as in bulk-based FinFETs.
The electronics industry trend towards smaller and thinner form factors has ushered an era of significant changes in packaging materials. As these trends continue, innovative material solutions will be needed to address demanding requirements related to product integration, mobility, and reliability.
The process flows applied today for real product manufacturing are quite different from the process flows initially proposed for a universal 3D IC.
GLOBALFOUNDRIES, Open-Silicon and Amkor Technology have jointly exhibited a functional system-on-chip (SoC) solution on a 2.5D silicon interposer featuring two 28nm logic chips, with embedded ARM processors.
You are currently browsing the archives for the Technology Features category.
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
How to tame data file sizes, address fractured data files creation and streamline data review techniques.