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High-NA EUV Lithography Investment

ASML funds Zeiss for anamorphic >0.5 NA.

Process Control Deals with Big Data, Busy Engineers

“Engineers are busy, and so you only tell them something they need to know.” Intel’s Steve Chadwick

2D Materials May Be Brittle

Molybdenum-diselenide brittle, borophene not

Air-Gaps for FinFETs Shown at IEDM

Researchers from IBM and Globalfoundries will report on the first use of “air-gaps” as part of the dielectric insulation around active gates of “10nm-node” finFETs at the upcoming International Electron Devices Meeting (IEDM) of the IEEE.

Multibeam Patents Direct Deposition & Direct Etch

E-beams directed by design to form and repair device structures.

Has SOI’s Turn Come Around Again?

Analysts see another chance for Silicon-on-Insulator technology, as proponents claim technical and cost advantages for fully-depleted SOI.

D2S Releases 4th-Gen IC Computational Design Platform

14 installations of GPU-accelerated platforms aid mask-makers worldwide

Elusive Analog Fault Simulation Finally Grasped

The test time per logic gate in ICs has greatly decreased in the last 20 years, thanks to scan-based design-for-test (DFT), automatic test pattern generation (ATPG) tools, and scan compression.

Linde Launches Asian R&D Center in Taiwan

Strategic investment serves IC, FPD, LED, and PV fabs

What is Your China Strategy?

Equipment vendors have a lot on their plates now, with memory customers pushing 3D NAND, foundries advancing to the 7 nm node, and 200mm fabs clamoring to come up with hard-to-find tools.