Mentor Graphics and Samsung announce a yield-improvement approach that’s based on mined test data.
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Using feedback mechanisms among a variety of EDA tool flows would allow designers to optimize incremental tapeouts to the benefit of the entire design-manufacturing ecosystem.
Semiconductor technologists face a crossroads at the 14nm node, when partially depleted, planar transistors are unlikely to deliver improvements in performance and power. Technologists at the recent International Electron Devices Meeting (IEDM) in San Francisco debated the relative merits of FinFETs (tall) versus extremely thin silicon on insulator, or ETSOI (thin).
To make matters worse, the market research company predicts positive growth will not return until 2014.
Qualcomm CDMA Technologies said it will not use a high-k/metal gate (HKMG) process for most of the chips it makes at the 28nm node, sticking with a poly/SiON gate stack. The company described the rationale behind the strategy – which because of Qualcomm’s size will have a major impact on the foundry business — at the 2010 International Electron Devices Meeting (IEDM) held in San Francisco.
The technology competition to supply the source of EUV radiation for the next-generation lithography tools has long been divided between the laser-produced plasma (LPP) approach, favored by Cymer Inc. (San Diego) and Gigaphoton Inc. (Oyama, Japan), and the discharge-produced plasma (DPP) method supported by Xtreme Technologies GmbH (Aachen, Germany).