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Design Archive

Elusive Analog Fault Simulation Finally Grasped

The test time per logic gate in ICs has greatly decreased in the last 20 years, thanks to scan-based design-for-test (DFT), automatic test pattern generation (ATPG) tools, and scan compression.

3D-NAND Deposition and Etch Integration

Lam talks about process control and default roadmaps.

Fab Facilities Data and Defectivity

In-the-know attendees at SEMICON West at a Thursday morning working breakfast heard from executives representing the world’s leading memory fabs discuss manufacturing challenges at the 4th annual Entegris Yield Forum.

CMOS-Photonics Technology Challenges

imec and Mentor detail painstaking progress.

79 GHz CMOS RADAR Chips for Cars from Imec and Infineon

Compact, low power, low cost solution to advance vehicle safety and automation.

Leti’s CoolCube 3D Transistor Stacking Improves with Qualcomm Help

Collaborating to build out design to fabrication ecosystem.

Molecular Modeling of Materials Defects for Yield Recovery

New materials are being integrated into High Volume Manufacturing (HVM) of semiconductor ICs, while old materials are being extended with more stringent specifications.

EUV Resists and Stochastic Processes

Random variability requires statistical control approaches.

Many Mixes to Match Litho Apps

“Mix and Match” has long been a mantra for lithographers in the deep-sub-wavelength era of IC device manufacturing.

Design-for-Testability (DFT) Verified with Hardware Emulation

Several years ago, while at Automatic Test Equipment (ATE) leader Teradyne, I witnessed frequent debates on a fundamental dilemma: On the production/testing floor, is it better to pass a failing device or reject a good device?