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White Papers Archive

Mask Data Preparation Flow For Advanced Technology Nodes

How to tame data file sizes, address fractured data files creation and streamline data review techniques.

Computational Lithography

Enabling 12 technology nodes in 12 years.

Next-Generation Signoff Analysis

Best practices for tackling electrical, physical and manufacturing challenges.

Optimizing Test To Enable Diagnosis-Driven Yield Analysis

Decreasing time to yield requires planning for what patterns to generate, what data to archive and hot to optimize your test program.

Calibre RealTime: Placing Signoff Verification into the Custom Designer’s Hands

A look at how to reduce custom/AMS design cycle time while improving design quality with on-demand, in-design signoff-quality verification.

A Call To Action: How 20nm Will Change IC Design

Double patterning marks a turning point in terms of lithography, variability and complexity.

Double Patterning From Design Enablement To Verification

A look at the challenges and various solutions using LELE at 20nm, including place and route effects, OPC and mask misalignment and image rounding.

Reducing IC Cycle Time With Calibre

Getting more functionality on the same die area using more and increasingly complex verification rules is getting more difficult. Here are some solutions.

EUV OPC For 56nm Metal Pitch

At 15nm and beyond, printing of pitches of 64nm and below will be required, and for EUV to replace ArF multi-exposure approaches patterns will have to be printed in a single-exposure process.

Innovative Wafers For Energy-Efficient CMOS Technology

How and why substrates will facilitate the introduction of planar and non-planar designs beginning at 28nm.