By David Abercrombie
In our double patterning (DP) conversations so far, we’ve discussed what it means to decompose a single layer into two masks, and identified typical configurations of polygons that can cause DP violations. We specifically discussed the most common odd cycle violations, and how to fix them by increasing the spaces between polygons. The reality, though, is that no matter how much you know about DP, trying to correct DP errors can be frustrating and finicky. There are times when your layout can benefit from a more surgical approach.
Believe it or not, that’s a viable approach…if the “hospital” you use gives you operating privileges. The correction technique is called “cutting and stitching,” although you will often just hear it referred to as stitching (guess some engineers are just squeamish). Let’s take a look at how it works. Figure 1 shows a couple of classic layout configurations that cannot be decomposed properly into two masks.
The top row shows a single polygon that has minimum spacing conflicts with itself. In other words, the highlighted minimum spaces are not allowed between polygon edges unless the edges belong to polygons on different masks. Because all the polygon edges involved in the minimum spaces belong to the same polygon, they have to be on the same mask. The only correct solution is to increase these spaces, which requires more design area. The bottom row shows an odd-cycle error. These three polygons cannot be alternated between two masks, because you can’t divide three by two without a remainder.
However, by slicing a polygon into two or more pieces (okay, it’s called a “cut”), both of these error conditions have a DP solution, as shown in Figure 2. Now, one piece of the original polygon can be defined by one mask and the other by the second mask. In the top row, the polygon edges forming the minimum spaces now belong to different masks, making them legal. In the bottom row, the bottom polygon of the three is “cut” into two pieces, creating a legal, even cycle. The benefit is that the errors are corrected without increasing the design size. In fact, the basic design is not changed at all.
If this sounds like magic, you aren’t too far off. We have seen cases in which 90% to 95% of a design’s DP errors can be fixed using cuts, while leaving the design essentially unchanged from a circuit layout and area perspective.
Of course, nothing comes for free, so it’s time for the fine print on the medicine bottle. As we discussed previously, because the DP process uses two separate lithographic printing steps to define the one design layer, there can be misalignment between the two lithography contours, in addition to the lithography rounding effects inherent to all designs. Figure 3 shows how this potential misalignment can negatively impact the use of cuts to fix DP violations.
As you can see, the two pieces that originally touched at the cut location may not make a robust connection after each piece is rounded during imaging, then misaligned relative to each other. This would, of course, cause an open circuit in your design, which is unacceptable. So how do we “heal” a cut? To overcome this issue, we extend the two pieces of the original polygon to overlap at the cut location. This overlapped area is called a “stitch,” and as you can see in Figure 4, it provides margin against the lithography rounding and misalignment concerns.
Figure 5 shows a more realistic layout that has several DP odd-cycle and anchor-path violations (marked by red and yellow error rings) that would normally require spacing adjustments to fix. Using stitches, you can see that most of the errors are corrected.
You may be asking at this point why the remaining error could not also be fixed using a stitch. Well, that’s the second caveat in the fine print. You can’t just put a stitch anywhere. Like anything else in a layout, there are many design rules associated with forming stitches. Stitching adds a whole new level of design complexity to the rules that guarantee robust electrical functionality in manufacturing, and it can be difficult for a designer to determine how to create a “legal” stitch that meets all of these extended rules. Precisely because of this added complexity, not all foundries offer the option for using stitches.
One design-side solution for this complexity, like many challenges in IC design, is to push the complexity into the EDA tool. That’s exactly what we’ve done at Mentor with the Calibre Multi-Patterning tool. We built automated functionality that can generate stitch candidates that comply with all the design rules, and that can be evaluated with our decomposition and checking tool to identify and solve DP errors.
In my next blog, we’ll examine the types of rules associated with generating stitches, and how EDA automation enables support for the ever-changing set of rules and makes utilization of stitching possible in 20nm design. I promise there will be no blood…
—David Abercrombie is the Advanced Physical Verification Methodology Program Manager at Mentor Graphics.