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Chipworks Zooms In on Tri-gate

Wednesday, April 25th, 2012

By David Lammers

Ever since Intel uncloaked its tri-gate transistor a year ago, technology watchers have had to make do with the few images Intel released at that time.

Now, the long-awaited Chipworks images are on-line, following the company’s initial teardown report (Intel’s 22nm tri-gate transistors exposed) posted Monday (April 23). One initial surprise was the shape of the Intel fin, rounded on top and tapered or sloped on the sides.

Dick James

Chipworks senior technology analyst (and chief  blogger) Dick James said the 22nm teardown process got started when he saw a review of an Intel 22nm server chip on the Anandtech site, which included a helpful link to a site in Hong Kong which had the server processors for sale, even though the server MPUs are not officially on sale until June.

Chipworks (Ottawa) ordered half a dozen of the Intel Xeon E3-1230V2 Server CPUs, at $300 per processor, and they arrived on April 1. Though Chipworks has been burned before with counterfeit die inside packages with new markings, the 22nm chips from Tao Bao in Hong Kong turned out to be genuine, and Chipworks went back and bought more.

Fortunately, Chipworks had upgraded its transmission electron microscope (TEM) in January, replacing an out-of-date model with an FEI Osiris TEM, a much more automated system. The new TEM  pumps down to a vacuum state more quickly, and alignment checking also is automated.

The Osiris TEM can do 400,000-times magnification. However, the microscope requires a sample thickness of about 80nm, which means that the images of the Intel transistors show more than is sometimes optimum: with a fin shown next to a gate, for example. “While the fin may be only 5-15nm wide, the sample has to be 80nm thick to get it in to the TEM. That increases the difficult of imaging. You are always seeing a gate and the fin, for example,” James said.

Looking at finFETs takes some getting used to, compared with planar transistors. “You definitely have got to be able to think in 3D. With a regular transistor I can explain how it works with one cross section. With finFETs, I need one image to show the shape of the fin, and another to show the shape of the gate, in right angles to each other. It is a bit more complicated from that point of view,” said James, who has worked for 17 years at Chipworks after earlier employment at semiconductor fabs in his native England.

Another complication is that the one-to-one ratio between structures and transistors doesn’t apply. One transistor can have multiple fins — six or more — while one fin can have multiple transistors.

Since each fin is a defined height and width, designers use quantized fins to create a wider PMOS, for example. “It is a whole different ballgame. These are quantized transistors, so the designers have to think in multiples of a single unit,” James said.

Designers must learn to use quantized gates with finFETs. The SRAM shown here has s a 6-transistor SRAM cell; the transistors marked T2 and T5 use two fins, while the others have one fin. T2 and T5 have gates twice as wide as T1, T3, T4, and T6. (Source: Chipworks)

The Virtues of a Tapered Fin

The Chipworks images show an Intel transistor with a rounded top and tapered, sloping sides. James said that was an interesting and surprising early observation, because many of the photos of finFETs shown in recent years at IEDM and other conferences — by Sematech, Imec, TSMC, and others — all have shown a vertical fin. Intel’s own schematic diagrams show an idealized structure with straight sides.

A lattice image of the NMOS fin structure shows a rounded fin with tapered sides. (Source: Chipworks)

James speculated that Intel’s tapered fin is easier to manufacture, and the rounded top evens out the electric field at the top of the fin. “Any pointed surface has a higher electric field than a flat surface, so the rounded structure may even out the electric field between the fin and the gate. Our speculation about why it is rounded relates to the fact that if the transistor had square corners on the fin, it would crank up the electric field and make the device less reliable.”

Also, etching straight walls is difficult, making it likely that the etching steps are probably easier with a tapered fin. James said flash memories also often have rounded corners in order to avoid damaging the gate dielectric on the memory cell.

The gate oxide and metal gate are much the same as Intel’s earlier planar transistor, and the PMOS stressing mechanisms also are similar. Intel appears to have changed the metal fill at the center of the gate, using tungsten instead of aluminum and titanium aluminum. James said they feel fairly confident of that conclusion because the “very dark” area appears to be the same color as the W contacts.

On the other hand, Chipworks at this point has “no idea what the stress mechanisms for NMOS are.” Intel is no longer using the nitride stressors it employed at the 90nm and 65nm nodes, because there is not enough room around the gate. At 45nm, Intel used a mixture of metals on the gate to put tensile stress on the channel. “That may be possible (with tri-gate), but it doesn’t show. If there is stress in the NMOS, it is different from the 32nm approach,” he said.

TEM image shows the transition between PMOS and NMOS gates. The mottled TiN layer is in the PMOS, but not the NMOS. Some epitaxial SiGe can be seen on the source/drain of the PMOS fin. (Source: Chipworks)

I asked James if Intel’s technologists cooperate with Chipworks as it struggles to figure out what the images show. He said he posts the blogs first, and hopes for some reaction steering him in the right direction later, if the initial conclusions are faulty.

“Sometimes one or another person from Intel will get back to me, and say, ‘I can’t tell you where you were wrong, but this is not quite right. And they are fairly cordial when I meet them at IEDM. When I am chatting with them, they might say ‘You are pretty well right 90 percent of the time,’ which I take as a compliment since we are groping in the dark on something like this.”

The IEDM Logic Debate

Monday, December 12th, 2011

By David Lammers

The just-concluded 2011 IEDM in Washington, D.C. had three tracks, to my mind, and trying to make sense of it all is a long process. The first theme was the continuing debate over just how manufacturable (or not?) finFETs will be over the next two or three years, and how fully-depleted SOI and the SuVolta Deeply Depleted Channel approaches will compete with bulk finFETs.

The second track was on memory technology: the competition between a never-say-die phase-change (PC-RAM), a resurgent spin-torque-transfer MRAM, IBM’s fascinating Racetrack memory technology as a replacement for HDDs, and the Resistive RAMs (RRAMs).

The third track was on further-out technologies, including graphene, tunnel FETs (probably on III-V materials) and nanowires (seen as an extension of thin-channel finFETs). And IEDM has “Other” category papers on flexible circuits and displays, biomedical devices, and the like.

This year’s IEDM came seven months after Intel Corp. unveiled its 22nm tri-gate technology, which might lead one to expect a more detailed IEDM presentation on tri-gate. This is a “Tick” year for Intel, meaning the emphasis is on bringing in a new process rather than a new microarchitecture: the “Tock” in Tick-Tock. But the 22nm “Ivy Bridge” processors are five or six months late, which means the reverse engineering specialists such as Chipworks (Ottowa, Canada) haven’t had a chance to get their hands on an Ivy Bridge chip. Until Dick James & Co. (Dick’s IEDM slides, presented an ASM International lunch, are available here) start in with their microphotography and analysis, Intel doesn’t have much motivation to detail its tri-gate structures and materials.

That didn’t stop everyone else from talking about finFETs. Scott Thompson, who ran the 90nm program at Intel before departing for the University of Florida in 2002, is now the CTO at SuVolta Inc. Thompson said Intel’s tri-gate-based Ivy Bridge processors are likely to draw about 77W at the same 3-3.5Ghz clock frequency as the 32nm Sandy Bridge products, which draw 95W.

Thompson said that works out to a 19 percent improvement in power consumption, and he argues that Intel could have saved about that much power with a planar 22nm transistor.

“That level of power reduction is about what you would see if you move a planar transistor from one node to the next.  The power reduction comes from a few factors, but the scaling of the transistor width (W) accounts for about 15-20% power reduction. So in 22nm it does not appear tri-gate helped that much,” he said.

To get any new technology out the door – including strain and high-k/ metal gate — many tradeoffs are made in the first-generation implementations. Intel, for example, was forced to implant dopants in the fins to adjust threshold voltages in the 22nm tri-gate transistors, Thompson said, adding that going forward Intel will figure out other ways to support multiple Vts without degrading the channel mobility in the fins.

“The key for Intel is to first debug the manufacturing issues with tri-gate and set themselves up well for the next node (14nm), when they will take full advantage of tri-gate. For Intel’s CPU market the physics suggest the gains should be meaningful,” he said.

Mark Bohr, Intel’s director of process architecture, gave a keynote speech to open IEDM. Bohr said the tri-gate transistors provide a 37% gate delay improvement at 0.7V or a 50% active power reduction at constant performance when compared to Intel’s 32 nm logic technology “on a comprehensive set of benchmark circuits.”

If tri-gate delivers a much better sub-threshold swing, and slices 0.2V from the Vdd, that will be quickly proven when the 22nm MPUs emerge in personal computers next year. It will have been late, but worth the wait.

Attributes and challenges, with "no perfect options" facing designers, STMicro said. (Source: IEDM 2011 presentation)

What about fully depleted SOI (FD-SOI)? STMicroelectronics was the first company to describe its plans to use a FD-SOI process for its 28nm CMOS platform. What grabbed my attention is that STMicro’s program manager Franck Arnaud also said STMicro would use TSVs to support broadband links to a DDR DRAM, and have embedded DRAM on the logic die at some point during the 28nm generation. “The eDRAM was presented as a bulk option,” Arnaud said in a follow-up e-mail. The TSVs support a wide IO approach, with 1,024 TSVs in parallel.

“We plan to get our first SoC based on FD-SOI out in the second quarter of 2012. Integration with TSVs is targeted for later on,” he said.

The STMicro 28nm FD-SOI technology has a back biasing capability, which means that a control gate under the 25nm buried oxide layer can be used at the device level to either raise or lower the threshold voltage by 100mV, delivering extra performance or power savings, as needed. There is no body factor to take into account, said Michel Haond, director of FD-SOI process integration at STMicro, during the Q&A session after the presentation.

Besides Soitec and its two SOI 300mm wafer factories (Bernin, France, and Singapore), STMicro will draw upon MEMC (St. Louis), and Japan’s Shin Etsu Handotai (SEH) for competitively priced wafer supplies, Arnaud and Haond said. “The process flow with FD-SOI is simpler, with fewer implant steps than bulk. That compensates for the SOI wafer cost totally,” Arnaud said.

There are a couple of things to watch out for in 2012 regarding SOI. One is IBM’s direction, as they could support a bulk or SOI finFET, and/or FD-SOI planar architecture, or all three, at the 14nm node. A planar FD-SOI supports multiple Vts for SoC applications and delivers a competitive effective drive current (Ieff) for high-performance circuits, according to IBM research manager Bruce Doris.

IBM has used an embedded DRAM technology extensively for its Power series of server MPUs, based on an SOI technology, which is denser than SRAM while delivering 2ns-class access times. I asked a couple of IBM technologists at IEDM if — with much of IBM’s design and IP resources tuned to SOI — the SOI eDRAM would keep IBM on either a planar or vertical SOI platform. They said the SOI eDRAM was “one consideration we are taking into account.”

GlobalFoundries is another company expected to make a 14nm announcement soon. At the Global Technology Conference in Santa Clara in the late summer, CTO Greg Bartlett said GlobalFoundries would use some form of fully depleted technology at the 14nm node, but he didn’t say if that would be a planar or a vertical transistor. At IEDM, Ali Keshavarzi of the GlobalFoundries R&D group gave a presentation describing the attributes of a fully depleted finFET transistor.

GlobalFoundries R&D Group listed 10 Key Performance Indicators as it considers its 14nm options. (Source: 2011 IEDM)

Keshavarzi emphasized the tradeoffs between power vs. performance at a given cost, or PPC, an acronym that could become part of the mainstream lexicon.

And what about SuVolta, which partnered with Fujitsu to show stable SRAM operation in the 0.5V regime? Several technologists said the SuVolta approach appears to be based on a steep retrograde well process, which Thompson did not deny, noting that there is more to the SuVolta recipe than its implant scheme. One source said companies with patent portfolios on retrograde wells may be cautious before signing up with SuVolta. The SuVolta approach, he argued, “may appeal to second tier fabless companies” which seek to avoid a lot of EDA/IP porting costs. Thompson appeared confident that SuVolta would gain traction, fitting in for semiconductor companies that don’t want to take the leap to finFETs, with their myriad manufacturing complexities.

Thoughout the IEDM, starting with a Sunday short course presentation by Intel’s Ian Young, the challenge of reducing external resistance (Rext) was emphasized, with contact resistance as one of the most-challenging hurdles going forward.

Greg Yeric, an ARM technologist, gave an invited paper on a designer’s perspective of scaling issues. FinFETs have narrow width effects, he noted, saying “W matters. In critical paths, which often are folded, we are now seeing contacts with twice the resistance (of thick Ws). Parasitic capacitance as a function of W is becoming a serious issue,” Yeric said.