GlobalFoundries R&D with Samsung leads to 28nm fabs in the U.S., Korea, and Germany, and first tape-outs using leading EDA flows. Still with IBM, but also doing things with IMEC, Intermolecular, and PDF Solutions.

EUV source sub-systems continue to develop. Gigaphoton reports 92% Sn debris mitigation, and Cymer and Xtreme provided product updates at SEMICON West 2011. The IC industry, once again, is engineering the impossible.

Both TSMC and GlobalFoundries say they could have chosen finFETs for 22/20nm, but chose to stay planar to allow more design flexibility for diverse IC customers; foundries might use finFETs at 16/14nm.

Intel’s 22nm finFET process plans can be gleaned from past IEDM presentations, and Applied Materials’ buying Varian’s implant business is partly to get plasma-doping implant IP needed for finFET processing.

Intel’s 22nm node tri-gate finFET architecture for digital transistors provides fully-depleted function without SOI wafer cost, though with more costs for design and 3% more cost in manufacturing.

E-beam Direct Write (EbDW) lithography for silicon ICs may sneak into the industry behind mask writing technologies developed by ASELTA, D2S, Mentor Graphics, MAPPER, and Multibeam, probably to cut grids formed using 193i litho.

SPIE Advanced Lithography 2011 will show updates to EUV now planned for <16nm nodes, double-patterning extensions, and next-generation litho (NGL).

Common Platform of IBM, Samsung, GlobalFoundries switches from HKMG CMOS IC transistors gate-first @ 3Xnm to gate-last @ 2Xnm node, while Intel and TSMC remain gate-last.