Part of the  

Solid State Technology

  Network

About  |  Contact

IFTLE 244 3D Stacked CMOS Image Sensors; IEEE 3DIC Conf

By Dr. Phil Garrou, Contributing Editor

At the recent 2015 Int Image Sensor Workshop, Ray Fontaine of Chipworks presented a review of “The State-of-the-art of Mainstream CMOS Image Sensors” Chipwork’s estimate, from other market research firms, is that the CIS market in 2014 was ~ $9B. Of this total it is estimated that Sony, Samsung and Omnivision hold > 66% market share driven by mobile phone and tablet camera chips.

Their look at the patent literature shows the field continues to grow with 2500 patents filed in 2014, the majority of them being processing patents.

cmos image sensor patents

Stacked Chip CIS

3D stacked CIS became a reality in 2012 when Sony announced the worlds first stacked chip CIS in consumer cameras. In 2013 they introduced the 8 MP ISX014 in a tablet computer [ref]

[P. Jagodzinski, “Sony ISX014 ¼ inch 8 MP 1.12um pixel size Examor RS stacked back illuminated CIS imager process review” Chipworks March 2013 ]

The first gen chips employed via last TSV to connect pads on the Sony 90nm CIS die to the pads on the Sony 65nm ISP. The die stack was partitioned such that most of the functionality of a conventional system-on-chip (SoC) CIS was implemented on the ISP die; the CIS die retained the active pixel array, final stage of the row drivers, and comparator portion of the column-parallel ADCs. The CIS (left) and ISP die (right) are shown below.

Click to view full size. Click to view full size.

Sony’s 13 MP IMX214 second generation stacked CIS chips were fabricated using its 90/65 nm (CIS/ISP) technology generation. The key work on the second generation stacked process was to use the CIS silicon only as the active pixel array substrate and move the column readout chain and peripheral transistors to the underlying ISP die.

In 2014, Sony announced they were using TSMC as a foundry for the 40nm ISP wafers on the Apple iPhone 6/6 Plus iSight cameras. These chips incorporate Sony 90 nm CIS wafers and TSMC 40 nm ISP wafers.

In 2015, Samsung and OmniVision have both been sampling small-pixel, stacked chip CIS.

Given the continued, aggressive stacked CIS development underway from independent device manufacturers (IDM) and foundries it’s predictable that stacked chip adoption will occur very rapidly over the next few years.

IEEE 3DIC Conference Sendi Japan Aug 31st

Click to view full size. Click to view full size.

The IEEE International 3D System Integration Conference (3DIC) will be held in Sendai, Japan August 31-Sepember 2, 2015. After the first conference in San Francisco in 2009, the 2nd IEEE 3DIC Conference was held in Munich in 2010, and then Osaka in 2012. The forth conference was back in San Francisco in 2013 and the fifth conference in Cork, Ireland in 2014.

IEEE 3DIC 2015 will cover all 3D integration topics, including 3D process technology, materials, equipment, circuits technology, design methodology and applications. The conference invites authors and attendees to submit and interact with 3D researchers from all around the world. Papers are solicited in subject topics, including, but not limited to:

  • 3D IC Process Technology
  • 3D IC Circuits Technology
  • 3D Applications
  • 3D Design Methodology

For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…

Leave a Reply