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IFTLE 164 Semicon Taiwan part 2; GlobalFoundries Manocha Interview

By Garrou

Over the past few years, SEMICON Taiwan has been a conference where significant new advances in packaging technology, especially 3D-IC, have been revealed. There were no such revelations this year.

The Advanced Packaging Technology Symposium was chaired by Mike Liang, resident of Amkor Taiwan.  The 3D-IC Technology Forum and the embedded Technology Forum were chaired by Chair  Ho-Ming Tong, General Manager & Chief R&D Officer for  ASE.

FC and WLP Continue to Expand

At the Advanced packaging symposium, Vardaman of TechSearch reported that FC and WLP growth , driven by mobile products, will increase from 15% of the pie in 2012 to 21% of the pie by 2017.

TS 1

Moving to copper pillar because bump pitch is limited to ~ 130um. Cu pillar bump pitch can go to < 100um. Most are looking at NCP/NCF underfill solutions.

Corning Updates Capabilities for Glass Interposers

At the 3DIC technology symposium Shorey of Corning updated their progress in the area of glass interposers. Working on 100 to 300mm wafers and 500mm panels (100 – 700um thick) some typical results are shown below.

corning 1

Looks like current minimums at 20um TSV on 50um pitch with wafer thicknesses of 100um. Max via densities greater than 250 TSV/mm. Warpage looks better on glass than on silicon.

Click to view full screen. Click to view full screen.

Unimicrons look at Panel Level Technology

At the Embedded Technology Forum Hu of Unimicron looked at panel level embedded technology. They offer the following comparison of WLP technology on silicon to “panel level packaging”

UM 1

(Note: IFTLE does not agree with the density capability assumptions in either category)

Two processes are evolving for embedded passive panel level processing as shown in the slide below.

UM 2

Key Process Items include (a)  Component placement accuracy; (b) Interface Adhesion with Dielectric Layer and (c) Warpage Control.

On interesting concept is the embedding of the SI interposed into the substrate as shown below. Reportedly less testing steps would be required and certainly thin wafer handling would be reduced.

 

Click to view full screen. Click to view full screen.

GF’s CEO Agit Manocha on stacked die, 450mm and consolidation

Ed Spurling of Semi Manuf. & Design posted a interesting interview with GlobalFoundries CEO Agit Manocha. Manocha indicates that GF will be moving from 20 to 14nm in mid 2014 with a finfet product.

He reports that GF is working with multiple assembly houses and memory supplier partners to develop 2.5/3D technology which will be available for 28, 22 and 14nm.

He does not see 450mm being mainstream till 2020.

80% of the worlds IC production is now in moderate to high risk zones for natural disasters. GF has their production ( New York, Germany and Singapore) in the 20% low risk zone.

Moving to the 20 NAND 14 noted Manocha supports those who say there will be very few players left. He indicates TSMC, GF, Samsung and Intel. That’s it…four !

More coverage of SEMICON Taiwan is coming in the next few weeks.

For all the latest on 3D-IC and advanced packaging, stay linked to IFTLE.

2 Responses to “IFTLE 164 Semicon Taiwan part 2; GlobalFoundries Manocha Interview”

  1. Blog Review October 14 2013 | Solid State Technology Says:

    [...] Phil Garrou reports on developments in 3D integration from Semicon Taiwan. He notes that at the Embedded Technology Forum, Hu of Unimicron looked at panel level embedded technology. [...]

  2. Blog Review October 14 2013 | Semiconductor Manufacturing & Design Community Says:

    [...] Phil Garrou reports on developments in 3D integration from Semicon Taiwan. He notes that at the Embedded Technology Forum, Hu of Unimicron looked at panel level embedded technology. [...]

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