Graphene meets heat waves; UT Dallas technology could make night vision, thermal imaging affordable; Breakthrough in OLED technology
Industry Research Archive
A new spin on spintronics; Novel solid-state nanomaterial platform enables terahertz photonics; Novel crumpling method takes flat graphene from 2-D to 3-D
Fabrication of patterns with linewidths down to 1.5nm; New method allows for greater variation in band gap tunability; New pathway to valleytronics
Solving an organic semiconductor mystery; Rice-sized laser, powered one electron at a time, bodes well for quantum computing; Carbon nanotube finding could lead to flexible electronics with longer battery life
Stacking 2-dimensional materials may lower cost of semiconductor devices; Scientists measure speedy electrons in silicon; Holst Centre and imec develop thin-film hybrid oxide-organic microprocessor
Soitec announces new world record for solar cell efficiency at 46%; High photosensitivity 2-D-few-layered molybdenum diselenide phototransistors; Finding the Achilles’ heel of GaN-based LEDs in harsh radiation environments
New process isolates promising material; Revolutionary solar-friendly form of silicon shines; New way to move atomically thin semiconductors for use in flexible devices
Revving up fluorescence for super fast LEDs; Smallest world record has ‘endless possibilities’ for bio-nanotechnology; Printing in the hobby room: Paper-thin and touch-sensitive displays on various materials
GLOBALFOUNDRIES and SRC announce new scholarship for undergraduate engineering students; Layered graphene sandwich for next generation electronics; Doped graphene nanoribbons with potential
A new, tunable device for spintronics; Copper shines as flexible conductor; Competition for graphene
You are currently browsing the archives for the Industry Research category.
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
How to tame data file sizes, address fractured data files creation and streamline data review techniques.