Revving up fluorescence for super fast LEDs; Smallest world record has ‘endless possibilities’ for bio-nanotechnology; Printing in the hobby room: Paper-thin and touch-sensitive displays on various materials
Industry Research Archive
GLOBALFOUNDRIES and SRC announce new scholarship for undergraduate engineering students; Layered graphene sandwich for next generation electronics; Doped graphene nanoribbons with potential
A new, tunable device for spintronics; Copper shines as flexible conductor; Competition for graphene
Scientists craft a semiconductor only three atoms thick; A breakthrough in imaging gold nanoparticles to atomic resolution by electron microscopy
New test reveals purity of graphene; Promising ferroelectric materials suffer from unexpected electric polarizations; MIPT and RAS scientists made an important step towards creating medical nanorobots
SRC, UC Davis explore new materials and device structures to develop next-generation “Race Track Memory” technologies; Notre Dame paper offers insights into a new class of semiconducting materials; Pairing old technologies with new for next-generation electronic devices
Taking great ideas from the lab to the fab; National Science Foundation tests out the assembly line of the future; New material allows for ultra-thin solar cells
A nanosensor to identify vapors based on a Graphene/Silicon heterojunction Schottky diode; A cool approach to flexible electronics; Graphene grain boundaries reviewed
imec joins Graphene Flagship; Collecting light with artificial “moth eyes”; A silicon replacement?
Research on high-performance field-effect transistors; UC Santa Barbara researchers introduce highest performing III-V metal-oxide semiconductor FET
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The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
How to tame data file sizes, address fractured data files creation and streamline data review techniques.