SRC and MIT extend high-resolution lithography; How 19th century physics could change the future of nanotechnology; JILA physicists discover “quantum droplet” in semiconductor
Industry Research Archive
Breakthrough development of flexible 1D-1R memory cell array; Leeds researchers build world’s most powerful terahertz laser chip; Quantum dots provide complete control of photons
Diamond defect boosts quantum technology; Quantum dots provide complete control of photons; New theory may lead to more efficient solar cells
New quantum dots herald a new era of electronics operating on a single-atom level; Cooling microprocessors with carbon nanotubes
Natural 3D counterpart to graphene discovered; A deeper look at interfaces; Energy storage in miniaturized capacitors may boost green energy technology
Battery development may extend range of electric cars; The cyborgs era has started; Nano-capsules show potential for more potent chemo-prevention
SRC launches industry consortium, partners with NSF to research trustworthy and secure semiconductors and systems; Work on growth of novel materials and structures; New center to lead Purdue efforts in computational nanotechnology, materials and devices development
Electron’s shape; Resistance makes waves; High-efficiency electricity delivery
Low-power tunneling transistor for high-performance devices at low voltage; Crystal film growth: nanosheets extend epitaxial growth applications; Graphene-based nano-antennas may enable networks of tiny machines
Thin, flexible solar cells; Polymers can be semimetals; MOF materials
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The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
How to tame data file sizes, address fractured data files creation and streamline data review techniques.