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GF’s 22nm FD-SOI Offering – Where to Get Lots of Excellent Info

Monday, October 5th, 2015

By Adele HARS

A fast-growing body of information is now posted by GlobalFoundries on their new 22nm FD-SOI offering.

After years of asking “where’s FD-SOI on the GF website??”, it’s (finally!) there, front and center. There are some excellent new videos and documents. Here’s a rundown of what you’ll find.

The 22FDX Platform introduction is the currently the lead topic on the GlobalFoundries website.

When you click down the “Technology Solutions” tab and select “Leading Edge Technologies”, here’s how they describe their 22nm FD-SOI offering:

GLOBALFOUNDRIES 22FDX™ platform employs 22nm Fully-Depleted Silicon-On-Insulator (FD-SOI) technology that delivers FinFET-like performance and energy-efficiency at a cost comparable to 28nm planar technologies. While some applications require the ultimate performance of three-dimensional FinFET transistors, most wireless devices need a better balance of performance, power consumption and cost. 22FDX provides the best path for cost-sensitive applications. The 22FDX platform delivers a 20 percent smaller die size and 10 percent fewer masks than 28nm, as well as nearly 50 percent fewer immersion lithography layers than foundry FinFET.

  • Ultra-low power consumption with 0.4V operation
  • Software-controlled transistor body-biasing for flexible trade-off between performance and power
  • Integrated RF for reduced system cost and back-gate feature to reduce RF power up to ~50%
  • 70% lower power than 28HKMG

Here are some of the resources posted on the website as of this writing:

Product Brief: 22FDX™ – a two-page pdf summarizing the platform advantages, the various application-optimized offerings, and basic graphics explaining how body-biasing works and what advantages it provides

FD-SOI Technology Innovations Extend Moore’s Law (white paper) – NEW! Just posted in September 2015, this 8-page white paper covers the basics of the FD-SOI transistor, how body biasing works, the impact the technology has on common circuit blocks (digital, analog & RF, embedded SRAM), and the outlook for future scaling (which goes down to 10nm).

This slide is about 17 minutes into GF’s “How to build ULP chips with 22nm FD-SOI…” webinar.

Webinar: How to Build Ultra Low Power Chips with New 22nm FD-SOI TechnologyNEW! Just posted on September 24, 2015. GF’s Jamie Schaeffer, Ph.D. Leading Edge Product Line Manager is talking to designers here. After a brief overview (he looks at the features, the extensions, the IP suite, and so forth), he gets into the fundamentals of body biasing, the different transistor optimizations, specific advantages for RF & analog, the tools for ultra-low-power design, and what’s in the design starter kits that are available today. Total running time is just under 20 minutes.

This slide is shown about 12 minutes into GF’s “Extending Moore’s Law with FD-SOI” webinar.

Webinar: Extending Moore’s Law with FD-SOI Technology – this is the webinar Jamie Schaeffer gave with ChipEstimate.com the day of the company’s FD-SOI announcement in July 2015. It’s a fairly high level presentation: very useful for designers, but also accessible to those outside the design community. There’s a lot of background on FinFET vs. FD-SOI, cost comparisons, target apps, and actual results seen in silicon. It’s an especially good place to start if FD-SOI is new to you. It runs just over 35 minutes.

Tech Video: Benefits of FD-SOI Technologies – in this short video by Subi Kengeri, GF’s VP of the CMOS Platforms BU, he gives a quick rundown of the benefits of FD-SOI. It runs about 2 minutes.

Another excellent place to get more indepth info on FD-SOI is an interview with Subi Kengeri by SemiEngineering Editor-in-Chief Ed Sperling (click here to see it on YouTube). This video, entitled Tech Talk: 22nm FD-SOI, was made just after the July announcement. Subi really goes into substantial detail, and clearly explains the key differences between FinFETs and FD-SOI. He explains why FD-SOI has less variability than FinFETs, why FinFETs have higher device capacitance, and how only with FD-SOI can you dynamically change Vt. FD-SOI also comes out better in terms of dynamic power, thermal budget and RF integration. Highly recommended – it runs just over 20 minutes.

You might also want to check out GF CEO Sanjay Jha’s Shanghai FD-SOI Forum presentation, The Right Technology at the Right Time, on the SOI Consortium website. (There are lots of others there, too!) Taking a bird’s eye view of the semiconductor industry drivers and requirements, he concludes, “22FDX and RFSOI have the power, performance, and cost to drive growth in mobile, pervasive, and intelligent computing.”

Which is great news for the SOI ecosystem and the entire industry.

ST’s FD-SOI Tech Available to All Through GF

Monday, October 8th, 2012

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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In the spring of 2012, STMicroelectronics announced the company would be manufacturing ST-Ericsson’s next-generation (and very successful) NovaThor ARM-based smartphone/tablet processors using 28nm FD-SOI process technology. With first samples coming out this fall, ASN talks to Jean-Marc Chery, Executive Vice President, General Manager Digital Sector, Chief Technology & Manufacturing Officer, STMicroelectronics about the manufacturing process and the expected results.

Jean-Marc Chery, Executive Vice President, General Manager Digital Sector, Chief Technology & Manufacturing Officer, STMicroelectronics (Photo credit: Artechnic)

Advanced Substrate News (ASN): You taped out ST-Ericsson’s 28nm FD-SOI NovaThor in the beginning of September. Did that go as you expected?

Jean-Marc Chery, STMicroelectronics (JMC): 28nm FD-SOI is a pretty exciting technology, allowing better design optimization (for higher speed and power efficiency) than traditional bulk technologies, still reusing most of manufacturing bricks of planar 28nm LP technology and the same design flow and methodology.

Adoption of 28nm FD-SOI for ST-Ericsson’s NovaThor has not introduced any major difficulty in its design, and the FD-SOI version has been taped out shortly after the Low-Power bulk version. Of course special care has been dedicated to further optimize power, exploiting FD-SOI exceptional flexibility and low-power capabilities.

On the manufacturing side, FD-SOI does not introduce additional complexity: on the contrary, process steps are reduced and thus cycle time.

ASN: Can you talk about the results you expect to see or have seen in the chip? Is there anything about it, or perhaps about the ARM core in particular, that makes it especially well-suited to FD-SOI? Is there anything about the transistor back-biasing capability (which enables significant performance enhancements and power optimization) in the design that makes it challenging to manufacture?

JMC: The wide supply range (ranging from 1.2V down to 0.6V) with excellent performance, and extended back-biasing capability (allowing dynamic modulation of the transistor threshold voltage) offered by 28nm FD-SOI technology have allowed us to exploit the ARM implementation to offer an improved maximum frequency and reach an overall power reduction for the various operating modes of the SoC.

About back biasing, this is a standard feature of FD-SOI technology with no particular challenges for manufacturing. Of course, its dynamic usage to optimize operating points for power (or speed) requires an appropriate device architecture to fully benefit from it.

ASN: In the press, STMicroelectronics has indicated that the 28nm FD-SOI has better power and performance than the industry’s first-gen bulk 22nm FinFETs. Would you say that your choice of FD-SOI puts you in a position of strength, in that you’ll have the mobile industry’s leading technology for 28nm and a choice of mature technologies at 14nm?

JMC: 28nm FD-SOI technology is a unique offer in the SOC industry, allowing the introduction of a fully-depleted technology with a low-cost solution and in a timely manner.

28nm FD-SOI is a planar technology derived from 28nm LP bulk technology, with the same design rules and allowing direct layout reuse (or simplified porting) of basic building blocks and IPs, benefiting from inheriting their maturity level. Also on the manufacturing side, 28nm FD-SOI technology uses the same equipment as Low Power bulk CMOS in a simplified process flow. In ST/Crolles facility we are reaching yield levels comparable to 28nm LP bulk ones, proving that FD-SOI process does not introduce major yield detractors.

A smooth library and IP migration flow coupled with rapid availability for manufacturing is driving the success of this 28nm technology.

Looking at the technology roadmap, the same incremental step for the 14nm node is under development and is on track.

The STMicroelectronics fab in Crolles, France. (Photo credit: Artechnic)

ASN: The plan was to start production in your fab in Crolles, then shift to GlobalFoundries for high-volume production in 2013 — is this still the schedule? From a manufacturing standpoint, what does it take to get a fab ready for FD-SOI production (does it take much longer than a typical bulk scaling transition)? Are there any special tools or other preparations needed?

JMC: For manufacturing, 28nm FD-SOI technology uses the same toolset as for 28nm LP bulk. Process development is complete, and ST/Crolles fab is now working to bring yield at production levels and complete the qualification of the technology, as done for any other.

Phase-in of the technology at GlobalFoundries is planned to start Q1 2013, with process qualified and with production level yield foreseen for Q4 2013.

The ST Crolles fab is highly automated, and already runs a broad mix of products in addition to the new FD-SOI chips. The accumulated assets the company has invested in this fab will increase capacity to 4500 wafers/week by the end of 2014. (Photo credit: Artechnic)

ASN: Let’s talk about the Crolles fab for a minute. Although it may be considered small compared to the big pure-play foundries, some aspects you share with the big foundries – like a large mix of product and advanced automation, right?

JMC: Crolles’ technology mix encompasses Advanced CMOS 28/40 nm, Imaging Sensors, embedded Non Volatile Memories starting at 55nm for Microcontroller and Analog on CMOS 110nm. This mix optimizes very well the accumulated assets we have invested in this Fab toward 4500 wafers week capacity over the next two years.

ASN: How do you see the impact of STMicroelectronics’s decision on the industry? Do you expect others to follow? Will other companies be able to leverage your technology at your foundry partners?

JMC: We would like very much for others to follow us. Through GlobalFoundries, ST is making its FD-SOI technology available to anyone in the microelectronics industry. The ST wide set of silicon-proven 28nm foundation libraries and IPs, encompassing not only basic libraries (std-cells, srams, I/Os) but also complex AMS IPs, is also available to be licensed to those customers aiming for quick access to the technology.

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Roundup: FD-SOI, Ecosystem Shine at Semicon West

Tuesday, August 7th, 2012

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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SOI in general and FD-SOI in particular were hot topics at this year’s Semicon West in San Francisco. A panel discussion by industry thought-leaders gathered to discuss the current challenges facing the mobile industry was among the highlights.  It featured an impressive line-up of key players from the ecosystem at the forefront of fully-depleted, SOI based technologies, including:

  • ARM: Ron Moore – Director of Strategic Accounts Marketing, Physical IP Division
  • GlobalFoundries: Subramani Kengeri – Vice President of Design Solutions
  • IBM: Gary Patton – Vice President of the Semiconductor Research and Development Center
  • SOI Industry Consortium: Horacio Mendez – Executive Director
  • Soitec: Steve Longoria – Senior Vice President of World Wide Strategic Business Development
  • STMicroelectronics: Philippe Magarshack – Technology Research and Development Group Vice President
  • UC Berkeley: Chenming Calvin Hu, Ph.D. – TSMC Distinguished Professor at the University of California at Berkeley

FD-SOI figured prominently in a panel on mobile challenges held during Semicon West '12. Left to right: C. Hu (UCBerkeley); R. Moore (ARM); H. Mendez (SOI Consortium); G. Patton (IBM); P. Magarshack (ST); S. Kengeri (GF); S. Longoria (Soitec)

Setting the scene, Soitec’s Longoria noted that, “Our industry is now driven by SOCs (where in the past it was CPUs) and we are on much shorter product cycles driven by consumer applications.”

As the first to be bringing out products based on ultra-thin layers of both SOI and insulator, ST’s Magarshack spoke extensively about their planar FD-SOI technology, which will be taping out at 28nm this summer.  He said that they were very confident and would be sharing the results at the end of the year.  He also emphasized their full commitment and close work with GF to enable the ecosystem, which was echoed in comments by GF’s Kengari.

With respect to 28nm, said Mendez of the SOI Consortium, “…the analysis says the cost [of FD-SOI] is equivalent to or even lower [than bulk silicon].”

IBM’s  Patton concurred, saying that, “When you’re dealing with an FD-SOI wafer, we see a big key advantage in manufacturability and time to market.”

Asked how FD-SOI would impact end-users, ARM’s Moore responded that mobile is about saving power.   FD-SOI provides a low-power bedrock, and with the headroom, the back-biasing option lets you add incredible performance.  “We see a valuable flow with FD-SOI & FinFET from devices down to servers,” he said.

In conclusion, UCBerkeley’s Hu said, “I’m very confident FD-SOI and FinFET are going to serve the industry quite well.”

The panel was followed by a great party held by leading SOI wafer manufacturer Soitec, to celebrate their 20th anniversary.

Earlier in the day, the show’s TechXpot series lead off with Enabling Sub-22nm with New Materials and Processes.  It was packed – with all the chairs taken, people were sitting on the floor in the aisles and crowded four-deep all around the edges. In his presentation on the  “Convergence of Engineered Substrates and IC Devices for Mobile Applications”,  Soitec CTO Dr. Carlos Mazure reminded us that mobile is really many technologies: in addition to the digital side, there’s RF, imaging, MEMS and memories – all of which can (and many do) benefit from SOI and other advanced engineered substrates. They’re not all on the leading edge, but when it comes to battery life, they all count.

At another presentation, Leti’s FD-SOI Manager with the IBM Alliance Maud Vinet covered their leading-edge research on FD-SOI.  She says that they’ll be presenting exciting results at IEDM in December, so watch this page for that.

All in all, it was a good show for the SOI ecosystem, full of energy and renewed enthusiasm.

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Leti Looks at Using Strain with FD-SOI for High-Perf Apps

Friday, June 29th, 2012

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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The researchers at Leti working on FD-SOI have extremely deep expertise in it. One of the areas they’ve looked at is performance boosters. With the interest in FD-SOI rapidly increasing on the heels of the recent ST-GF announcement, their work becomes even more timely.

A key Leti team wrote a summary of some recent strain work, which first appeared as part of the Advanced Substrate News special edition on FD-SOI industrialization.  In case you missed it there, here it is again.

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Leti: Adding Strain to FD-SOI for 20nm and Beyond

By Olivier FAYNOT, Microelectronic Section Manager, and Francois ANDRIEU, senior research engineer at CEA-LETI.

The outstanding electrostatic performance already reported for planar FD-SOI technology can be improved by the use of ION boosters in order to target-high performance applications, as already demonstrated in the past.

Figure 1: Stressor options for FD-SOI technology

As illustrated in Figure 1, strain can be incorporated at various places in the transistor:

  • In the channel through the use of c-SiGe for PMOS devices and strained SOI (sSOI) material for NMOS.
  • In the source and drain region with the use of SiGe or SiC for P and NMOS respectively.
  • In the Middle-of-Line process with the deposition of tensile or compressive Contact Etch Stop Layers (t- or c-CESL).

First, it is worth noting that local stressors are often more effective on FD-SOI than on bulk at a given geometry because of the mechanical properties of the buried SiO2, which is less stiff than Si[1].

We have assessed different boosters on the FD-SOI architecture. The results are summarized in Figure 2.

For NMOS, one can see that sSOI is the more promising stressor with an ION improvement of 20-35 % for wide devices; and, it can increase up to 50 % for W = 50 nm narrow transistors[2] [1]. Our preliminary results let us predict a better scalability for sSOI than for t-CESL or SMT. Moreover, the compatibility of sSOI was already proved (even if the ION-boosts are not always totally additive) with t-CESL[3] for NMOS and with rotated substrates[2], e-SiGe[4], SiGe channels[5] and (110) substrates[6] for pMOS.

For pMOSFETs, there are several options to enhance the ION, the simpler being the 45° rotated substrates with a 8 % boost[1] and r-SiGe with a 18 % improvement by an access resistance reduction (37 % if a strain can also be generated into the channel)[4]. Once again, the scalability of the global boosters is certainly better than for the local ones (c-CESL and e-SiGe).

Figure 2: Efficiency of stressor techniques for N & PMOS

In conclusion, thanks to all the experiments already run, we are confident in the fact that strain can be incorporated in the planar FDSOI architecture, thus boosting performance even further at 20 nm and beyond.

NOTE: This article was adapted from the Leti presentation, “FD-SOI strain options for 20 nm and below”, given at the SOI Consortium’s 6th FD-SOI Workshop. The complete presentation is available at www.soiconsortium.org.

- – – – -

References:

[1] C. Fenouillet-Beranger, L. Pham Nguyen, P. Perreau, S. Denorme, F. Andrieu, O. Faynot, L. Tosti, L. Brevard, C. Buj, O.Weber, C. Gallon, V. Fiori, F. Boeuf, S. Cristoloveanu, T. Skotnicki, “Ultra compact FDSOI transistors (including Strain and orientation) processing and performance”, ECS Transaction, 2009.

[2] S. Baudot, F. Andrieu, O. Faynot, J. Eymery, “Electrical and diffraction characterization of short and narrow MOSFETs on Fully Depleted strained Silicon-On-Insulator (sSOI)”, Solid State Electronics, 2010.

[3] F. Andrieu, C. Fenouillet-Beranger, O. Weber, S. Baudot, C. Buj, J.-P. Noel, O. Thomas, O. Rozeau, P. Perreau, L. Tosti, L. Brevard, O. Faynot, “Ultrathin Body and BOX SOI and sSOI for Low Power Application at the 22 nm technology node and below”, invited talk at SSDM, 2009.

[4] S. Baudot, F. Andrieu, O. Weber, P. Perreau, J.F. Damlencourt, S. Barnola, T. Salvetat, L. Tosti, L. Brévard, D. Lafond, J. Eymery, O. Faynot, “Fully-Depleted Strained Silicon-On-Insulator p-MOSFETs with Recessed and Embedded Silicon-Germanium Source/Drain”, 2010.

[5] F. Andrieu, T. Ernst, O. Faynot, Y. Bogumilowicz, J.-M. Hartmann, J. Eymery, D. Lafond, Y.-M. Levaillant, C. Dupré, R. Powers, F. Fournel, C. Fenouillet-Beranger, A. Vandooren, B. Ghyselen, C. Mazure, N. Kernevez, G. Ghibaudo and S. Deleonibus, “Co-integrated dual strained channel on fully depleted sSDOI CMOSFETs with HfO2 /TiN gate stack down to 15 nm gate length”, IEEE SOI Conference, p. 223-5, 2005.

[6] T. Mizuno, N. Sugiyama, T. Tezuka, Y. Moriyama, S. Nakaharai, S. Takagi, ”(110)-Surface Strained-SOI CMOS Devices”, IEEE Transaction of Electron Devices, 52, 3, p.367, 2005.

What’s ST’s FD-SOI Technology All About?

Friday, June 22nd, 2012

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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As I blogged here on SemiMD last week, STMicroelectronics has announced that to supplement in-house production at their fab in Crolles, the company has tapped GlobalFoundries for high-volume production of 28nm then 20nm FD-SOI mobile devices.  ST will also open access to its FD-SOI technology to GlobalFoundries’ other customers.  High-volume manufacturing will kick off with ST-Ericsson’s ARM-based 28nm NovaThor.

Prior to the announcement, the STM published a white paper explaining why they were forging ahead on FD-SOI.  It’s an excellent paper, providing benchmarks and design considerations.

As they explained in the Executive Summary: “Planar FD is a promising technology for modern mobile and consumer multimedia chips. It combines high performance and low power consumption, complemented by an excellent responsiveness to power management design techniques. The fabrication process is comparatively simple and is a low-risk evolution from conventional planar bulk CMOS – and there is little disruption at the design level, too. At 28nm, we find that planar FD more than matches the peak performance of “G”-type technology, at the cost and complexity of a low-power type technology, with better power efficiency across use cases than any of the conventional bulk CMOS flavors. Looking further, for 20nm and 14nm, we believe planar FD will be extremely competitive with respect to alternative approaches in terms of performance and power, while being both simpler and more suited to low-power design techniques. In short, a better choice for the type of SOC we offer. Planar fully depleted silicon technology will be ready as early as 2012 to compete in the forthcoming superphones era and in many other consumer segments.”

With the ST/GF news that other GF customers will have access to the ST technology, those in the fabless community will no doubt be wanting to learn more about what’s on offer.  If you have time, you can download the entire ST white paper from the SOI Consortium: Planar fully depleted silicon technology to design competitive SOC at 28nm and beyond.

The ST team that wrote it also wrote a summary version, which first appeared as part of the Advanced Substrate News special edition on FD-SOI industrialization.  In case you missed it there, here it is again.

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ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond

By Philippe FLATRESSE, Program Manager for Fully Depleted SOI Technology, STMicroelectronics; Giorgio CESANA, Director of Technology Marketing at STMicroelectronics; and Xavier CAUCHY, Digital Applications and Strategic Marketing Manager at Soitec.

Having identified that conventional planar bulk CMOS would not meet all the requirements of mobile and consumer multimedia System-on-Chip (SOC) ICs in the coming years, STMicroelectronics assessed alternative options. It is possible to propose a 28nm planar FD solution available as a second generation shortly after readiness of traditional 28nm on bulk silicon, with better time-to-market than waiting for availability of the 20nm node. It is also an excellent learning step to prepare a 20nm planar FD process. Our evaluations show that 20nm planar FD has also a very competitive potential performance-wise vs. FinFET for System-on-Chip applications.

Figure 1: ST’s planar FD device structure features (notional perspective, notional cross-section, TEM cross-section)

Technology overview:

  • Immunity to Short Channel Effects and variability (no channel doping, so no Random Doping Fluctuations / RDF)

  • For the 28nm node, the selected BOX thickness is 25nm.

  • Ultra-thin BOX advantages include:

    - further improved electrostatic control and relaxed thinness requirement of the top silicon,

    - enables back-biasing through the BOX,

    - enables the implantation, during the fabrication process, of heavily doped “ground planes” or “back-planes” under the BOX, for improved electrostatics and/or VT adjustment and/or best-efficiency of back-bias,

    - brings the ability, during the fabrication process, to locally remove the top silicon and BOX to reach the base bulk silicon and co-integrate a few (non geometry-critical) devices on Bulk with devices on SOI – with a small step height between an SOI zone and a Bulk zone, compatible with lithography tools.

  • BOX offers total dielectric isolation of the very thin active layer and naturally ultra-shallow junctions, leading to lower source/drain capacitance, lower leakage and latch-up immunity.

Planar FD technology allows several methods for setting the threshold voltage VT, including engineering the gate stack work function, trimming the gate length and other process engineering techniques. Thanks to this, STMicroelectronics’ 28FDSOI technology is capable of offering 3 VTs (HVT, RVT, LVT), as in traditional bulk CMOS technologies.

Circuit-Level Benchmarking

To assess how the improved planar FD-SOI transistor characteristics translate at the circuit level, STMicroelectronics has benchmarked a number of representative IP blocks, including an ARM Cortex-A9 CPU core. To that aim, we have extracted logic critical paths with associated RC parasitics from placed-and-routed designs and have re-characterized them by swapping 28nm traditional bulk CMOS transistor SPICE models with 28nm planar FD SPICE models.

With test chips in our 28nm planar FD technology becoming available, we are demonstrating that the models predict well the silicon behavior. We are therefore confident that the benchmarks presented below are reliable and will be matched by SOC implementations.

The benchmarks compare the merits at the 28nm node of ST’s planar FD technology (“28FD”) with a state-of-the-art Low-Power technology (“28LP”) and a more performance-oriented, state-of-art General Purpose technology (“28G”). They are all based on evaluation of an ARM Cortex-A9 core. The analysis focuses on the higher end of the range of operating frequencies found in a SOC, since modern mobile and consumer multimedia demand high performance from their master CPU (for example, a Cortex-A9 or the forthcoming A15).

Performance at nominal Vdd : best speed/leakage trade-off: 28FD consistently outperforms both 28LP and 28G (Figure 2).

Figure 2: Best operating frequency for any class of leakage (TT process, 85C)

Excellent speed/leakage ratio maintained at reduced Vdd : reducing Vdd is a very good way to save dynamic power. It is therefore realistic to envisage building 28FD chips that match 28G or 28LP performance at a fraction of the power consumption.

Leading-edge performance across the full Vdd range: 28FD exhibits outstanding performance at all practical Vdd values. In particular, when maximum circuit speed is sought, only the low- and ultra-low-VT flavors of 28G compare with 28FD LVT; however they are much leakier and more limited in terms of, e.g., Vdd overdrive they can withstand without reliability concerns.

Best Power Efficiency Across Use Cases: the 28FD technology is power-efficient across the full Vdd and target frequency range (Figure 3). Contrary to G-type technology, with 28FD a given logic circuit that is power-efficient with Vdd set to reach a certain operating frequency (say, 2GHz range) remains efficient with Vdd set for a different target frequency range (e.g., sub-1.5GHz).

Figure 3: Power efficiency across all use cases (TT process, WC temp)

Focus on SRAM: The bitcells proposed in 28FD technology have very competitive cell current (Icell) vs. standby current ratio, which is representative of the performance/leakage power trade-off for SRAM arrays (Figure 4). This is true for all bit cells flavors: high-density and low-leakage oriented, or high-speed oriented. The footprint of the 4 bitcells proposed in 28FD is the same as that of the 4 bitcells proposed in 28LP.

Figure 4: SRAM memory bit cells performance/leakage. The power supply of 28FD SRAM arrays can be lowered by 100mV from nominal and still match the performance of 28LP SRAM arrays operated at nominal Vdd, while offering a 2x to 5x reduction in leakage power.

Commonalities with 28nm LP Bulk

STMicroelectronics’ strategy when developing the 28nm planar FD technology has been to reuse as much as possible the 28nm low-power bulk CMOS process.

Overall, the Back-End is 100% identical to the traditional 28nm bulk low-power CMOS process, and the Front-End of Line (FEOL) is 80% common with that same process.

The planar FD process saves about 10% of the steps required to fabricate the chips on the wafers. This approximately offsets the cost overhead of the starting wafers. As a result, the 28nm planar FD technology matches the cost of a conventional low-power technology while delivering extremely competitive performance.

Design Considerations

Designing on planar FD requires specific extraction deck and SPICE models. Apart from that, the design flows, methodologies and tools do not need any adaptation that would be specific to planar FD (Figure 5).

Figure 5: ST’s SOC implementation flow outline

SPICE Models: SPICE compact models have been developed for accurately representing planar FD transistors. The model we use is now integrated in all major commercially available simulators, such as Mentor’s ELDO, Synopsys’ HSPICE and XA or Cadence’ SPECTRE. A model card has been extracted for all transistors and other devices available in our 28nm planar FD technology.

Flow and Design Platform: With adequate SPICE models integrated in the PDK, the design flow is identical to that used with conventional 28nm Bulk CMOS technology. We have developed a full design platform for SOC, re-using work done for 28nm Bulk. It consists of standard cell libraries (multi-channel and multi-VT) with power management elements (power switches, level shifters etc.), embedded memories, analog foundation IP (such as PLLs and the likes) and specialty IP (Antifuse etc.).

A design platform developed for bulk CMOS technology can be ported to planar FD by re-characterization using planar FD SPICE models, which we have done for a variety of back-biasing conditions. Only a limited number of critical IPs need to be tuned or redesigned: Analog IP, IOs, Fuse.

At the SOC level, migrating an existing design from bulk to planar FD represents an effort comparable to half-node migration. It brings very worthwhile benefits at reasonable efforts.

All techniques used in low-power designs are applicable to planar FD. Those that can be enhanced with planar FD include: multi-VT, power switches, reverse and forward body bias, and voltage scaling.

Back-biasing consists of applying a voltage just under the BOX of target transistors. Doing so changes the electrostatic control of the transistors and shifts their threshold voltage VT, to either get more drive current (hence higher performance) at the expense of increased leakage current (forward back-bias, FBB) or cut leakage current at the expense of reduced performance. While back-bias in planar FD is somewhat similar to body-bias that can be implemented in bulk CMOS technology, it offers a number of key advantages in terms of level and efficiency of the bias that can be applied.  Back-biasing can be utilized in a dynamic way, on a block-by-block basis. It can be used to boost performance during the limited periods of time when maximum peak performance is required from that block. It can also be used to cut leakage during the periods of time when limited performance is not an issue. In other words, back-bias offers a new and efficient knob on the speed/power trade-off.

Perspectives

28nm: We expect to sign-off designs breaking the 2GHz barrier under worst-case conditions, in a power-efficient and cost-efficient way. For lower performance targets, there is also the opportunity to design ultra-low-power chips that can fulfill their functional specifications using a very low Vdd, for example in the 0.6-0.8V range. The Process Design Kit (PDK) is available, targeting the technology to be open for risk production by mid-2012.

20nm: We intend to scale our planar FD technology to 20nm, introducing a number of improvements to continue pushing the performance and retain a low power consumption. The objective is to bring up a solution that will improve on what mobile-optimized planar bulk CMOS will achieve, and will be extremely competitive vs. potential FinFET-based approaches for SOC – while keeping a simple and cost-efficient approach. The design rules will be compatible with 20nm bulk CMOS. This technology will bridge the gap to 14nm and provide an interesting alternative to the cost and complexity of introducing Extreme-UV and FinFET structures. Evaluation SPICE models are available, and full PDK is scheduled by end of 2012, with risk production for 13Q3.

14nm: Based on the assessments we have performed, we are confident that the planar FD technology is shrinkable to 14nm. Silicon and buried oxide thickness will need to be reduced to within limits that wafer manufacturers and CMOS process technology can handle.

GloFo to Fab 28/20nm FD-SOI for ST; ST Tech Open to GF Customers

Friday, June 15th, 2012

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News

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Two big pieces of news have recently been announced by STMicroelectronics:

  1. to supplement in-house production at Crolles, the company has tapped GlobalFoundries for high-volume production of 28nm then 20nm FD-SOI mobile devices;
  2. ST will open access to its FD-SOI technology to GlobalFoundries’ other customers.

The high-volume manufacturing will kick off with ST-Ericsson’s ARM-based 28nm NovaThor.

Here are other key points from the press release:

  • The 28nm FD-SOI generation, currently in the industrialization phase, is scheduled to be available for prototyping by July 2012.
  • The next node, the 20nm FD-SOI generation, is currently under development and is scheduled to be ready for prototyping by Q3 2013.

What they’re saying:

Joel Hartmann, STMicroelectronics Corporate VP, Front End Manufacturing and Process R&D, Digital Sector: “FD-SOI is ideally suited for wireless and tablet applications, where it provides fully-depleted transistor benefits using conventional planar technology, and this arrangement with GLOBALFOUNDRIES ensures our customers will have a secure source of supply.”

Philippe Magarshack, STMicroelectronics Corporate VP, Design Enablement and Services: “Porting Libraries and Physical IPs from 28nm Bulk CMOS to 28nm FD-SOI is straightforward, and designing digital SoCs with conventional CAD tools and methods in FD-SOI is identical to Bulk, due to the absence of MOS-history-effect. In addition, FD-SOI can be used for either extreme performance or very low leakage on the same silicon, by biasing dynamically the substrate of the circuit. Finally, FD-SOI can operate at significant performance at low voltage with superior energy efficiency versus Bulk CMOS.”

Gregg Bartlett, Chief Technology Officer of GLOBALFOUNDRIES: “We have a longstanding partnership with ST spanning joint R&D and manufacturing, as well as an unmatched heritage of expertise in SOI technology. We’re pleased to be working with ST to bring this next generation of SOI technology to market and enable continued momentum in the mobile revolution.”

While it might seem like all this is happening very fast, ST has been championing FD-SOI technology for about a decade. In fact, one of the company’s top SOI gurus, Advanced Devices Program Director Thomas Skotnicki, first wrote about it for us at Advanced Substrate News back in 2006. And we’ve been covering it regularly ever since.

For an in-depth look at ST’s FD-SOI design and manufacturing strategy and benchmarking results, be sure to check out their white paper. By the way, designers take note: they also indicate in the white paper that the 28nm FD-SOI Process Design Kit (PDK) is available now, targeting risk production by mid-2012. Evaluation SPICE models are now available for the 20nm node, and full PDK is scheduled by end of 2012, with risk production for 13Q3.

For easy access to the dozens of useful and insightful FD-SOI related articles by contributors on the leading-edge that we’ve published over the years, just hit the FD-SOI tag on the ASN website.

Seems like a new door has opened now, doesn’t it?

Fab 8, located in Luther Forest Technology Campus, Saratoga County, New York, USA is GlobalFoundries' new 300 mm Fab dedicated to advanced technologies. Maximum Full Capacity is 60,000 300mm wafers/month. GloFo also runs high-volume SOI at its fabs in Dresden and Singapore (source: Wikipedia).

Chenming Hu: SOI Can Empower New Transistors to 10nm and beyond

Wednesday, May 30th, 2012

The following is a special guest post by Dr. Chenming Hu, TSMC Distinguished Professor at UC Berkeley. He and his team published seminal papers on FinFETs (1999) and UTB-SOI (2000). This post first appeared as part of the Advanced Substrate News special edition on FD-SOI industrialization

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The good, old MOSFET is nearing its limits. Scaling issues and dopant-induced variations are leading to high leakage (Ioff) and supply voltage (Vdd),  resulting in excessive  power consumption and design costs. While these challenges have been increasing over time, they’ve finally gotten painful enough that the industry is ready to embrace new transistor structures.

The essence of the problem is that the leakage current does not flow along the Si-oxide interface, but nanometers below the interface  when the gate lengths (Lg) becomes very small. That leakage path is physically far from the gate even if the oxide were infinitely thin. The gate cannot shut off the leakage as if the oxide were nanometers thick. Essentially the MOSFET becomes a resistor. Ioff and variations got worse and worse with Lg reductions.

The solution is new MOSFET structures, in which there is no Si far (more than nanometers) from the gate(s). In other words, the transistor body must be ultra thin. Body doping becomes optional.

Both FinFETs and FD-SOI devices are ultra-thin-body transistors. As such, compared to traditional planar bulk CMOS, they both provide:

  • Higher speed and lower leakage
  • Lower supply voltage (Vdd) and power consumption
  • Further scaling and lower cost
  • Better sub-threshold swing and scaling
  • No random dopant fluctuation (RDF), less variability
  • Better mobility, especially for future sub-threshold design

FinFET

The FinFET body is a thin fin and the thin body is controlled from three sides instead of just the top.

FinFET is easy to scale because leakage is well suppressed if the fin thickness is equal to or less than Lg. Thin fins can be made with the same gate patterning/etching tools.

While our original FinFET work was on SOI wafers, a few years later (2003), Samsung presented a way to manufacture them on bulk substrates. There is an advantage to continued use of  bulk substrates; however, FinFET on bulk requires heavy implant below the fin to suppress leakage and that requires tradeoffs with FinFET performance.

When built on SOI, the FinFET does not suffer from leakage below the fin. Building FinFETs on SOI also confers certain advantages in simplifying manufacturing. The choice will be made by performance and comparisons.

Planar FD-SOI

Planar FD-SOI requires SOI wafers with a very, very thin top layer of silicon.  When we first invented the concept in 2000, the availability of such SOI substrates was the major obstacle. The final silicon layer thickness had to be about a quarter to a third of the gate length.

However, Soitec has surmounted the wafer challenge and with that, commercial production can now become a reality.

The FD-SOI approach can save the fabs and designers significant investment. Existing chip designs and associated IP can be ported with minimum effort, starting today at the 28nm node.

While FinFETs have a larger Ion, FD-SOI has a good back-gate bias option, which make it particularly interesting for low-power applications.

Conclusion

This is a very exciting time for the industry. Although it may seem that the industry is splitting into FinFETs and FD-SOI camps, both approaches use body thickness as the new scaling parameter, and can use undoped body for high performance chips without RDF. Both allow MOSFETs to be scaled beyond traditional MOSFET’s limit. And both can derive substantial benefits from SOI wafers. Real choice is good news because competition will bring the best out of both new transistor technologies.

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ST-Ericsson 28nm FD-SOI smartphone SOC, Q3 tape-out (interview)

Tuesday, April 24th, 2012

By Adele Hars, Editor-in-Chief, Advanced Substrate News

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ASN recently had a chance to talk to ST-Ericsson’s Chief Chip Architect Louis Tannyeres  about the move to 28nm FD-SOI for smartphones and tablet SOCs.  Take-away message:  FD-SOI solves – with less process complexity – scaling, leakage and variability issues to further shrink CMOS technology beyond 28nm. Here’s what he said.
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Louis Tannyeres, Principal Fellow, Chief Chip Architect and head of System Silicon Development at ST-Ericsson.

Advanced Substrate News (ASN): Can you give us a bit of background on the markets you’re addressing?

Louis Tannyeres (LT): Founded in 2009, ST-Ericsson is an industry leader in design, development and creation of cutting edge mobile platforms and semiconductors across the broad spectrum of wireless technologies.  Today, we are actively engaged with seven of the top nine mobile device OEM manufacturers by revenue.

ST-Ericsson’s portfolio covers all market segments, with an emphasis on mid to high-range smartphones and tablets.

ASN: What are the challenges that the product designers (your clients) face with respect to available technology vs. consumer expectations?

LT: With the recent evolution in smartphone capabilities consumer expectations are rising fast. Ultra-fast multicore Gigahertz processors, stunning 3D graphics, full HD multimedia and high-speed broadband connectivity have become the norm for high-end devices.

Consumers expect these features to be delivered in a device that is slim, light and can last for at least as long as their previous phones did. For our customers, the product designers, this translates into requirements for delivering high performance at low power in a cost effective manner.  FD-SOI is a technology that addresses exactly these requirements.

ASN: What advantages do you expect FD-SOI to bring to the platform?

LT: FD-SOI is a technology that is available for design today and will allow existing designs in 28nm to benefit today already from significant improvements in performance and power. FD-SOI solves – with less process complexity – scaling, leakage and variability issues to further shrink CMOS technology beyond 28nm.

ST-Ericsson's NovaThor™ family is an integrated solution for the mainstream smartphone segment, in which modems and application processors are built into a single piece of silicon. The application engine uses the latest ARM®-based multi-core CPUs optimized to deliver the highest performance and support for advanced 2D & 3D graphics cores.

ASN: How have your customers reacted to this bold move?

LT: True market disruptions are only understood after the fact. We believe FD-SOI is such a disruption and a truely differentiated solution. There is a real opportunity for a FD-SOI 28nm solution and then 20nm as a key technology differentiator.  Our customers have reacted  favorably to hearing that we will be enabling FD-SOI technology in our next generation of products. And since we are enabling this technology in STMicroelectronics’ foundries, we have also minimized our risk with respect to market adoption trends.

ASN: How difficult was it to port the existing design from bulk to FD-SOI?

LT: FD-SOI is a technology that is available for design today and will allow existing designs in 28nm to benefit today already from significant improvements in performance and power. Thanks to fully depleted devices, FD-SOI allows operating at fast speed at extremely low operating voltages – a key characteristic to allow low power operation for mobile devices.

A design platform developed for bulk CMOS technology can be ported to planar FD by re-characterization using planar FD SPICE models. Only a limited number of critical IPs need to be tuned or redesigned.

ASN: What was the impact on design flow?

LT: The equations describing the electrical behavior of fully depleted transistors are different from those used for conventional bulk CMOS, so designing on planar FD requires specific extraction deck and SPICE models. The model we use is now integrated in all major commercially available simulators.  Apart from that, the design flows, methodologies and tools do not need any specific adaptations.

ASN: Do you foresee any major challenges in fast-ramping to high volumes?

LT: 28nm planar FD manufacturing technology has a lot of commonalities with traditional 28nm Low-Power CMOS technology and STMicroelectronics’ strategy has been to reuse as much as possible the 28nm low-power bulk CMOS process. The Back-End part of the process is a direct copy of the 28nm bulk technology. The Front-End part of the process also relies in majority on a direct re-use of equivalent process modules from the bulk technology. Only a few steps have been optimized, added or removed. Overall, the Back-End is 100% identical to the traditional 28nm bulk low-power CMOS process, and the Front-End of Line (FEOL) has 80% in common with that same process.

ASN: When do you expect to have the first prototypes available?

LT: FD-SOI will be introduced into next generation products from ST-Ericsson. At this time, our first 28nm FD-SOI products are scheduled to tape out in Q3 2012 with production start anticipated in 2013.


Louis Tannyeres, Principal Fellow, Chief Chip Architect and head of System Silicon Development at ST-Ericsson, has 30 years of experience in wireless communications and semiconductors. He was TI Senior Fellow at Texas Instruments, where he architected and designed the world’s first digital baseband SoC integrating a DSP core, a microcontroller and  ASIC on a single die.

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ST-Ericsson NovaThor This Year, 28nm FDSOI, Soitec Wafers

Wednesday, March 14th, 2012

By Adele Hars, Editor-in-Chief, Advanced Substrate News

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Big and official FD-SOI news: Soitec has announced that the company is supplying the FD-SOI wafers for ST-Ericsson’s next-generation of NovaThor 8540 smartphone/tablet processors. Starting at the 28nm node, this marks the industry’s first industrialization of the new planar, fully-depleted technology on ultra-thin SOI wafers.

Soitec has just issued an official press release, but ST-Ericsson President-CEO Didier Lamouche had already heralded the news to analysts at the Barcelona Mobile World Congress last month. (You can see/hear the presentation here.)

His Slide 29 from the Barcelona event pretty much says is it all:

Slide 29 from ST-Ericsson’s Analysts & Media Briefing at Mobile World Congress in Barcelona (28 February 2012)

This architecture is essential in implementing transistor technology that solves – with less process complexity – the scaling, leakage and variability issues that are associated with shrinking CMOS technology from 28nm to 14nm.

ST-Ericsson’s planar FD-SOI technology is supplied by STMicroelectronics.  As Lamouche said in his presentation, “The world needs to go fully-depleted.” Choosing this flavor of fully-depleted, planar SOI technology (as opposed to a 3D fully-depleted technology such as FinFETs) puts ST-Ericsson a full two-years ahead of the competition, he estimates.

With the NovaThor platform, ST-Ericsson’s been wracking up some nice wins lately – with Samsung, Nokia and Sony, to name a few. So this is a high-volume endeavor.

Wafer manufacturer Soitec has been working on these wafers with key partners for years. The wafers for planar FD-SOI require an extremely thin and incredibly uniform (+/- 5 Angstroms!) layer of silicon on top of a very thin layer of insulating buried oxide (BOX). Soitec sells them under the banner “FD-2D”; they’re now ready to roll in volume.

“We are positioned to provide the volume of qualified wafer manufacturing required to enable the industry to speed the adoption of planar fully depleted technology into mainstream mobile applications,” says Soitec COO Paul Boudre.

In case you missed it, STM went into significant detail on the advantages of the technology and announced a 28nm product line at the SOI Consortium’s recent FD-SOI workshop (see Important News Comes Out of Recent FD-SOI Workshop in ASN online).

The key planar FD-SOI advantages cited by ST-Ericsson include:

  • a fully-depleted architecture that is cost-competitive with bulk
  • simplified processing (10 percent few steps)
  • 35 percent lower power consumption at maximum performance
  • big performance boost – double (!) when supply voltage is at 0.6V
  • designers can leverage powerful back-biasing techniques to further boost performance or lower power
  • it’s processed with standard fab tools

(Look for more about these and other features in a soon-to-be-published white paper.)

Key Quotes

From the Soitec announcement, here are the key quotes from the parties involved:

ST-Ericsson’s chief chip architect Louis Tannyeres: “Next-generation mobile consumer devices will need to deliver an even better user experience and higher performance without sacrificing battery life. Together with innovations in overall platform system design, advances in process technology are key to delivering next-level performance and higher power efficiency. The results of our work with ST on FD-SOI have demonstrated that this technology is able to deliver these benefits in a cost-effective manner, while allowing us to differentiate our solutions.”

STMicroelectronics’ assistant general manager, Technology R&D, Joël Hartmann: “STMicroelectronics and its partners Leti, Soitec and IBM have invested several years of development in FD-SOI technology, and ST has recently demonstrated the strong differentiation of  this technology versus conventional bulk CMOS, both for high-performance and low-power features on several IPs at 28nm and below.  This combination makes FD-SOI particularly suitable for wireless and tablet applications where it essentially provides the fully depleted transistor benefits of FinFETs on a planar conventional technology, while allowing advanced back bias techniques, which are not available with FinFETs. We are delighted that it could be adopted by ST-Ericsson for their next generation of products.”

Soitec’s COO, Paul Boudre: “FD provides a low-risk option for semiconductor companies such as ST-Ericsson that are seeking to take advantage of the benefits of a fully depleted transistor architecture while leveraging existing design and manufacturing capabilities.”

Clearly this is a very significant and exciting moment for the industry. It’s the first major fully-depleted announcement since Intel/FinFETs. Might it be the first shot across the bow in the next round of the transistor wars?

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32nm SOI is GloFo Fab 8′s 1st Silicon

Wednesday, January 18th, 2012

By Adele HARS, Editor-in-Chief, Advanced Substrate News

Excellent news for the fast-growing SOI community:  the first chips produced at GlobalFoundries’ “Fab 8″ in upstate New York are based on IBM’s latest, 32nm SOI chip technology. In a joint press release, the two companies announced that the chips will be used by customers in networking, gaming and graphics.

While the new chips began initial production at IBM’s 300mm fab in East Fishkill, GF’s Fab 8 in Saratoga County will ramp production in the second half of 2012. With 300,000v ft2 of cleanroom space, overall capacity will total about 60,000 wafers/month.

GlobalFoundries new Fab 8 campus, located in the Luther Forest Technology Campus about 100 miles north of the IBM campus in East Fishkill, stands as one of the most technologically advanced wafer fabs in the world and the largest leading-edge semiconductor foundry in the United States. (Courtesy: GlobalFoundries)

“GlobalFoundries’ Fab 8 running IBM’s 32nm SOI technology represents a terrific opportunity for accelerating SOI innovation into broader markets,” explains Horacio Mendez, Executive Director of the SOI Consortium.  “SOI is a cost-effective technology, and a huge facility like Fab 8 enables an even wider segment of the design community to benefit from the increased performance and lower power it offers.”

SOI: Front and Center

The press release put SOI front and center, saying, “The technology vastly improves microprocessor performance in multi-core designs and speeds the movement of graphics in gaming, networking, and other image intensive, multi-media applications.”  IBM’s 32nm SOI technology was jointly developed with GF and other members of IBM’s Process Development Alliance, with early research at the University at Albany’s College of Nanoscale Science and Engineering.

(By the way, they’re sticking with “gate first” HKMG here, which they say both boosts performance and cuts costs.)

The release also notes that the chips rolling off this new line feature IBM’s embedded DRAM (eDRAM).  ASN readers will remember that IBM’s eDRAM guru Subu Iyer wrote in ASN about the role that SOI plays therein back in 2006.   He noted that while eDRAMs had previously been done in bulk silicon, “The complexity adder is about half in SOI compared to bulk for deep trench based eDRAMs.”

Interesting, too, that the announcement cites networking, gaming and graphics.  IBM, of course,  has its own successful SOI foundry business, and owns the high-end gaming market, fabbing SOI-based chips for the big three: Sony PS3, Microsoft Xbox 360 and Nintendo Wii (and the upcoming Wii U).

For its part, GF has all the AMD SOI-based business, including all the Opterons, the FX and the “A-series” APUs – including the upcoming “Trinity” for desktops & high-end laptops, with the new Bulldozer core.

Deep Roots, High Gear

“Today’s announcement is a natural extension of our longstanding partnership with IBM that includes production of 65nm and 45nm chips at our fabs in Singapore and Germany,” said GlobalFoundries CEO Ajit Manocha. “With the addition of our newest factory in New York, we will now be jointly producing chips with IBM at four fabs on three continents.”

GlobalFoundries Fab 8 Clean Room, NY

Workers prep Global Foundries' newest semiconductor factory, "Fab 8" in Saratoga County, New York State. The fab comes on line for the first time with a maiden production run of microprocessors based on IBM's latest, 32nm SOI. The chips will be used by manufacturers in networking, gaming and graphics. (Courtesy: GlobalFoundries and IBM)

The New York-Dresden-Singapore SOI triumvirate goes way back.  IBM launched SOI in Fishkill back in 1998.  AMD followed with 130nm SOI out of Dresden in 2001.  Singapore – which was first Chartered – started turning out 90nm SOI chips for IBM back in 2004, and adopted AMD’s highly touted Automation Precision Manufacturing (APM) in 2005.

Would it then be fair to surmise that the SOI foundry business is now into high gear?  GF’s been turning out 32nm SOI chips at its other fabs since June ’11.

It makes good business sense to have a leading technology like 32nm SOI available in a pure-play foundry scenario at key locations across the globe.  If GF’s new Fab 8 chose 32nm SOI for its first silicon, the technology must now be robust, and demand in North America and elsewhere on the rise, don’t you think?

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