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Smart Power on SOI

By Adele Hars, Editor-in-Chief, Advanced Substrate News

What if you had to reduce power dissipation by 40x?

That’s exactly the task that fell to STMicroelectronics, under an EU program called Smart Power Management.

At the recent ISPSD (International Symposium on Power Semiconductor Devices and ICs) conference, ST and partners (GE Vingmed Ultrasound and Sintef) presented a paper on how they did it, using ST’s latest SOI-based Smart Power technology.

Paola Galbiati, ST’s Director of the BCD Technology Line, Technology R&D covered this project in her recent ASN article, “Smart Power Saves Power”.

As she notes, ST has been solving critical power management challenges with SOI-BCD (Bipolar-CMOS-DMOS) processes for almost a decade now. The technology they developed under the SmartPM project is a next-generation variation of their BCD smart power technology, combining SOI with 0.16-micron lithography.

Cross section of N-Channel (left) and P-Channel (right ) power MOS. (Courtesy: STMicroelectronics)

While the technology is applicable to chargers for electric car batteries, the first proof point was done for ultrasound probes.

Transesophageal probes,which are inserted into the esophagus via the throat, send a beam across the esophageal wall to image the heart structures. The constraints on space and power consumption for the embedded electronics are extremely stringent. (Courtesy: GE Vingmed Ultrasound AS)

The trend toward 3D ultrasound using internal probes imposes draconian limits on power. After all, you can’t have the doctor putting something hot and bulky down your throat in order to image your heart.

2D probes typically have a couple hundred channels, consuming a total of about 3W of power. But for advanced 3D imagery, thousands of channels are needed – with total power consumption cut to 1.8W: about 40 times less.

This was not possible with discrete components, but it is with technology like ST’s SOI-BCD, which enables chip designers to combine high-density logic circuitry (1.8V and 3.3V CMOS) with full dielectric isolation and a component portfolio. They can include power MOSFET transistors that can operate up to 300V, low noise devices and high-value resistors, leading to ASICs that couldn’t be implemented using conventional bulk-silicon substrates.

ST’s now got first silicon, so product design engineers can start planning a whole new generation of cutting edge solutions.

Top view of the latest SOI-BCD test chip layout. (Courtesy: STMicroelectronics)

Add this to the fast-growing list of SOI-enabled game changers.

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