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Full Reliability Automation Is Here!

By Frank Feng, Mentor Graphics

Transistor and Gate levels of library design are normally delivered fully vetted for reliability issues such as electrostatic discharge (ESD), latch-up, electrical overstress (EOS), and dielectric breakdown. However, when designers assemble transistors and gates into intellectual property (IP), blocks, or whole chip designs, they encounter a variety of reliability problems generated across interconnect layers or across device regions of PSUB and NWELL bodies, such as:

  • Did the ESD or layout implementation designer pick up the correct ESD cell library during physical implementation?
  • Does the implemented ESD cell contain enough fingers (gate width/length) to protect internal circuit?
  • Are the ESD/power clamp cells placed in appropriate locations, and does the resulting routing path across interconnect meet minimum effective resistance criteria to serve as the designed ESD path?
  • Is there any weak wire segment or via area likely to be blown out due to high current density passing during an ESD event?
  • Are there appropriate charged device model (CDM) ESD protection circuits placed along the path across analog/digital function blocks when receiver gates contain thin gate oxide MOS?
  • Are devices on the input/output (IO) path, or in the neighborhood of IO, well-shielded by P+/N+ guard rings/straps?
  • Is the distance large enough between an Active area that has a path to IO, and near-by NWELL areas that are at a different potential, to prevent latch-up?
  • Is there any path from the top level to inner circuits that can damage the thin gate oxide MOS in the internal circuit?
  • Are wires operating at different potentials placed too close together, causing dielectric breakdown?

There is no existing dynamic simulation tool that can realistically provide a comprehensive reliability analysis on design data from larger IP up to full-chip level. To address such issues, the majority of design houses, independent device manufacturers (IDMs), and foundries use manual checking methodology based on check lists, or place marker shapes inside layout data overlaid with susceptible base-layer shapes of devices and interconnect layer shapes to trigger design rule checking (DRC) tools to check some of these reliability issues. Nevertheless, these manual checking, marker shape assist, and even internal proprietary solutions face the challenges of manual errors caused by the complexity of the modern chip design environment, accuracy issues in checking for the correct physical property throughout the whole design, and eventually, sustaining maintenance issues.

Foundries have been painfully aware of the criticality of these reliability problems at advanced nodes, and the lack of automated tool functionality to analyze and correct them. They documented these issues as checks in the design rule manual, but marked them as “un-checkable” rules, since there were no tools to script these rules into the rule kit/tech file for the designer to use. Alternatively, some foundries simply provided a spreadsheet of checklists for internal use or customer service, but these checklists were frequently too rough to be a true guideline, and simply checking some layout data could not provide enough information to reflect the true purpose of the checks—reliability verification.

To provide a true verification solution for the types of reliability issues listed earlier, a reliability verification tool needs multiple capabilities, such as:

  • Tracing circuit connectivity (to locate desired circuits)
  • Translating identified circuit components (device/cell/net) to the layout side of data
  • Performing geometrical and/or electrical property checks
  • Integrating standard parasitic exchange format (SPEF) connectivity data with a field solver to compute effective resistance/current density along a specified electrical path

Such a tool must also work with some type of integrated database to handle the unification of circuit connectivity searching, DRC, and PEX. In addition, these tools must employ data management strategies that provide reasonable performance when processing extreme large parasitic networks on power/ground networks, or handling millions of pin pairs/paths in a field solver to compute effective resistances, or current density on each resistor node (representing a wire segment or via area).

New EDA tools that can provide the wide range of functionalities needed to handle the full scope of reliability verification are emerging. For example, Mentor’s Calibre PERC tool enables design teams to check their entire design thoroughly at different design assembly stages, including coverage for such essentials as:

  • Complete primary/secondary ESD protection of IO
  • Cross-power domain path CDM ESD protection
  • Power Clamp/Back-to-Back diode protection between Power/Ground
  • Latch-Up triggered by IO across NWELL and PSUB bodies
  • Effective interconnect resistance for desired ESD paths, and current density along ESD paths
  • Electrical overstress (using a static view in combination with user input to identify circuits that shift voltage)
  • Dielectric breakdown between wires of interconnect (using voltage-dependent DRC)

Even better, now that automated reliability verification solutions are available, the foundries can provide rule kits for reliability design solutions to their customers, a mutual benefit to both the foundry service and the design methodology of fabless design house. With the development of new reliability analysis and verification tools, both foundries and designers now have the automated capabilities they need to ensure thorough reliability verification across the entire design verification flow, ensuring that the chips that enter the marketplace meet all performance and reliability expectations.

Author

Frank Feng is a Circuit Verification Methodologist in the Calibre organization at Mentor Graphics in Wilsonville, OR. He is responsible for the development of product functionality to analyze reliability design issues, and to improve the robustness and quality of the design. He also engages with foundries to establish reliability design verification methodology and assist them in converting it into rule kits for designers. Frank holds a PH.D. in Physics from the University of Houston. You can reach Frank at frank_feng@mentor.com.

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