Authors from Novellus Systems and The University of Illinois describe how the quality of PVD deposited barrier/seed interface in copper interconnect metallization was significantly improved by enhancing Cu nucleation on the Ta surface.

Technologists describe a straight port of an existing bulk CMOS design to
FD-SOI at the same node, obtaining the value of fully depleted SOI for a
modest redesign effort.

Two Soitec Group managers — Eric Desbonnets and Stéphane Laurent — describe how SOI wafers support RF technology development.

Via fanout and trace routing solutions for metric pitch ball grid array packages.

Xavier Cauchy, digital applications manager at Soitec, describes the design implications of fully depleted SOI technology at the 22/20 nm node.

Xavier Cauchy of Soitec and François Andrieu at LETI raise some of the technical issues surrounding fully depleted SOI technology. The authors compare FD-SOI to FinFETs, describe how non-digital transistors can be handled, and provide a list of references for further reading.

This Mentor Graphics paper describes the physical signoff challenges seen in advanced node designs.