Intel details 22nm trigate SoC process at IEDM
As you can see from Table 1, we now have six transistor options; the high-voltage transistors use a thicker gate dielectric stack (Fig. 1), and the gate pitch and gate lengths have been tuned to suit the end purpose, and of course there is some (unspecified) source/drain engineering.
logic (top) and high-voltage (bottom) transistors 
If I read the paper correctly, the SoC process can incorporate up to twelve metal layers, with up to six 1Ã?? layers, and an extra 3Ã?? level, but only one 4Ã?? level Fig. 2). When it comes to the passives, the same MIMCAP layer is used as we saw in the CPU together with similar finger capacitors to the 32nm SoC; inductors are also formed in the 6Î¼m thick top metal; and there are precision resistors available.
A bunch of SRAM cells are offered, both six- and eight-transistor varieties, with the 6T cells ranging from the minimal 0.092 to 0.13 Î¼m2. These show the quantization of the transistor size quite nicely — if you look closely at Fig. 3, you can see that the number of fins used for each transistor increases with the size of cell, with the exception of the T3 and T4 PMOS pull-up devices, which only have one fin.
high density / low leakage (HDC), low voltage (LVC), and high performance (HPC) 
Overall Intel claims a 100-200 mV reduction in Vt for all transistor types, leading to a ~40% reduction in dynamic power.
Intel is trying to catch their SoC schedule up with the CPU launches, so we will likely see 22nm SoC chips next year, and the 14nm CPU and SOC processes should be launched in parallel, theoretically by the end of 2013.
 C-H Jan, IEDM 2012 pp. 44-47