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Posts Tagged ‘Texas Instruments’

Cadence Debuts Product for Reducing Test Time, Costs

Tuesday, February 2nd, 2016

By Jeff Dorsch, Contributing Editor

Cadence Design Systems is introducing the Modus Test Solution, a product that it touts as capable of reducing IC testing time and test costs, while improving profit margins for chips.

Modus shares a Tcl scripting and debugging environment with Cadence’s Genus Synthesis Solution, Innovus Implementation Solution, and Tempus Timing Signoff Solution, according to the company.

Its other capabilities include 2D compression, elastic compression, and embedded memory bus support. Modus incorporates automatic test pattern generation, built-in self-test, and design-for-test technologies.

“We’re pretty excited about it,” Paul Cunningham, vice president of research and development at Cadence, says of Modus. The automatic test equipment market is worth about $4 billion a year, yet test technology hasn’t yielded any significant breakthroughs in the 21st century, he asserts.

“Test has been stagnant for the last 15 to 20 years,” he says.

Cadence is trying to work around the challenges of test time and test costs by addressing “actual physical test” and “test logic itself,” Cunningham notes. Just as chip designers are constantly aware of power/performance/area in their projects, Cadence addressed test coverage and chip size in developing Modus, he adds.

ATPG, BIST, and DFT technologies have been around for a long time, and they are regaining substantial interest in the semiconductor industry as system-on-a-chip device designs grow more complex.

“Chip CAGRs are not what they used to be,” Cunningham observes. “Cost and profit are very, very critical. Power/performance/area are really, really critical.”

Chipmakers are constantly looking to “squeeze profit margins out,” and reducing test costs can contribute to that imperative, the Cadence executive says. “There is “real pressure on margins, real pressure on complexity,” he adds.

Cunningham also focuses on the “concept of a single user interface” for Modus and its related design tools. With a common UI, different steps in the chip design, manufacturing, and testing processes can be like “different apps on an iPhone,” he says.

Cadence collected testimonials for Modus from three chip companies.

“Minimizing the cost of test is crucial in high-volume, price-sensitive markets like embedded processing. The Modus Test Solution is showing a 1.7x reduction in digital test time on one of our largest and most complex embedded processor chips without any impact on design closure,” said Roger Peters of Texas Instruments, who is involved in microcontroller silicon development.

Sue Bentlage, director of ASIC design and methodology at GlobalFoundries, said, “The Modus Test Solution demonstrated a 3.6x reduction in test time on a customer networking chip without impacting design routability or fault coverage. This technology definitely reduces production test costs. The evolution of the Modus Test Solution, as well as the Innovus Implementation System, the Tempus Timing Signoff Solution and the Voltus IC Power Integrity Solution, provides a leading edge end-to-end design flow in 14nm and beyond for our worldwide design centers and for our ASIC customers.”

Chris Malkin, baseband IC manager at Sequans Communications, said of Modus, “Test time has a significant impact on semiconductor product costs and production capacity, so reducing test time is important. We have seen the Modus Test Solution achieve a 2x reduction in test time without impacting fault coverage or die size.”

“With the Modus Test Solution, we achieved an impressive 2.6X reduction in compression wirelength and a 2X reduction in scan time. The reduction in compression logic wirelength enabled us to address a key challenge for design closure as we push to smaller process nodes and scale design size,” said Alan Nakamoto, vice president, engineering services at Microsemi Corp.

Wally Rhines of Mentor Graphics Gets Phil Kaufman Award

Monday, November 16th, 2015

By Jeff Dorsch, Contributing Editor

There was a celebrity roast on 4th Street in San Jose, Calif., on Thursday night.

The occasion was the presentation of the annual Phil Kaufman Award to Wally Rhines, chairman and chief executive officer of Mentor Graphics, for his contributions in the field of electronic design automation. Dr. Rhines has served as Mentor’s CEO since 1993 and as chairman of the EDA software and services company since 2000.

The Phil Kaufman Award is presented by the Electronic Design Automation Consortium (EDAC) and the IEEE Council on Electronic Design Automation (CEDA). It honors the memory of Philip A. Kaufman, the EDA industry pioneer, electronics engineer, and entrepreneur, who died in 1992.

Rhines received some gentle ribbing from Craig Barrett, the former Intel chairman and CEO, who once was a Stanford University professor and served on the advisory panel for Rhines’ doctoral thesis.

Barrett said of Rhines, who was a top chip executive at Texas Instruments prior to joining Mentor, “We competed for about 20 years, which is probably why he went to Mentor Graphics.”

He added, “His hairline is receding faster than mine.”

The retired Intel executive later said Rhines’ career has been “fantastic,” adding, “He certainly exceeded all our expectations. You done good, man. Keep it up.”

A video shown before the formal presentation offered Barrett and other top executives showering accolades on Rhines, who turned 69 years old on Wednesday, November 11. Among those praising Rhines were Aart de Geus, chairman and co-CEO of Synopsys, and Lip-Bu Tan, president and CEO of Cadence Design Systems – business rivals and friends.

“He’s actually a cool cat,” de Geus said of Rhines in the video.

In his remarks, Rhines returned the favor to those praising him, saying of de Geus and Tan, “We’ve had enjoyable interactions.

“I’m particularly gratified that my professor, Craig Barrett, came here for my roast,” he said. “He willingly paid for the beer at The Oasis in Menlo Park.”

On a more serious note, Rhines said of Barrett, “He was very critical to my success.”

Rhines recalled the days when chip designers used rubylith sheets to lay out integrated circuits. “We evolved an industry,” he commented. While IC design and layout has become highly automated with EDA software, system design in many industries remains in the rubylith era, Rhines said. He called for a movement to “automate system design the way we automated electronic design.”

The evening drew to a close with a spoof video depicting Rhines as not only a visionary leader in EDA, but also as a race-car mechanic, a sushi chef, and a hair stylist. A good time was had by all.

Solid State Watch: October 31-November 6, 2014

Monday, November 10th, 2014
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