By Mark LaPedus

A group of 19 European companies and academic institutions have launched a three-year, 360 million euro ($464.5 million) pilot-line project to support the industrialization of fully-depleted silicon-on-insulator (FD-SOI) technology.

The project, dubbed Places2Be, is led by one of the biggest proponents of FD-SOI–STMicroelectronics. In addition, STMicroelectronics and GlobalFoundries will provide the manufacturing capabilities for the program. Separately, GlobalFoundries is also joining Imec’s advanced MRAM project.

Meanwhile, Places2Be, which stands for “Pilot Lines for Advanced CMOS Enhanced by SOI in 2x nodes, Built in Europe,” is aimed to support the deployment of FD-SOI pilot lines at 28nm and beyond.  It will also drive the creation of a European microelectronics design ecosystem using this FD-SOI platform and explore the path towards the next step for this technology at 14nm and 10nm.

The FD-SOI manufacturing sources for the project are located in two fabs. The first is the pilot line in STMicroelectronics’ Crolles fab, near Grenoble, France. The dual-source is in GlobalFoundries’ fab 1 in Dresden, Germany. STMicroelectronics and IBM are the biggest proponents for FD-SOI. Not long ago, STMicroelectronics signed an FD-SOI foundry deal with GlobalFoundries.

FD-SOI is a low-power, high-performance alternative to conventional bulk silicon and finFET technologies. The first FD-SOI systems-on-chips are expected to be used in consumer electronics, high-performance computing and networking.

The project includes participation of 19 partners from 7 countries, and the planned involvement of about 500 engineers over three years across Europe. Places2Be is the largest ENIAC Joint Undertaking project to date and is supported as well by the National Public Authorities in the participating countries. The ENIAC JU was set up in 2008 and will allocate grants throughout 2013. The projects selected for funding shall be executed till December of 2017. The total value of the R&D activities generated through ENIAC JU is estimated at 3 billion euros ($3.8 billion).

“The Places2Be project will reinforce the ecosystems of both Grenoble and Dresden clusters, while also positively impacting the whole value chain of microelectronics in Europe–large companies, SMEs, start-ups and research organizations–beyond the direct impact induced by the material and IP investments,” said François Finck, director of ST’s R&D cooperative programs and project coordinator, in a statement.

The Places2Be members include ACREO Swedish ICT AB,  Adixen Vacuum Products,  Axiom IC, Bruco Integrated Circuits, Commissariat à l’énergie atomique et aux énergies alternatives, Dolphin Integration,  Ericsson AB, eSilicon Romania S.r.l., Forschungzentrum Jülich Gmbh, GlobalFoundries Dresden, Grenoble INP, IMEC,  Ion Beam Services, Mentor Graphics France Sarl, Soitec, ST-Ericsson, STMicroelectronics, Université Catholique de Louvain, and the University of Twente.

In a separate move, GlobalFoundries is joining Imec and others to advance STT-MRAM (spin-transfer torque magnetoresistive random access memory) technology. The first IC manufacturer to join Imec’s R&D program on emerging memory technologies, GlobalFoundries completes the value chain of Imec’s research platform.

GlobalFoundries is joining a team with Qualcomm and several worldwide equipment suppliers providing the complete infrastructure necessary for R&D on STT-MRAM. In January, Qualcomm joined Imec’s STT-MRAM program.

STT-MRAM technology is a promising high-density alternative to existing memory technologies, like SRAM and DRAM. Together, imec and the program members aim to explore the potential of STT-MRAM, including performance below 1ns and scalability beyond 10nm for embedded and standalone applications.

By Mark LaPedus
About every five years or so, a new and hot market emerges in the specialty foundry business that resembles a frenetic gold rush.

The last big gold rush occurred around 2008, when more than a dozen foundries jumped into the bipolar-CMOS-DMOS (BCD) market to capitalize on the booming power-management sector. Now, the next gold rush is centering on an emerging technology—the radio frequency (RF) silicon-on-insulator (SOI) market.

Today, IBM, STMicroelectronics and TowerJazz offer RF SOI foundry processes for the merchant market. Over time, analysts estimate that a dozen or more foundries could offer RF SOI. Altis Semiconductor and Grace Semiconductor have announced plans to enter the RF SOI fray. Two others, Lapis Semiconductor and Silanna, have put RF SOI on their foundry roadmaps. And sources indicate that GlobalFoundries, MagnaChip and TSMC are developing RF SOI or evaluating the technology.

Foundries are jumping on the RF SOI bandwagon amid a boom for select parts, particularly within the RF front-end for the latest smartphones and tablets. Typically, the RF front-end consists of power amplifiers (PAs), RF switches, tunable capacitors and filters. Generally, the PA and switch are based on gallium arsenide (GaAs), while the tunable capacitors and filters use various technologies.

RF SOI and its variant, silicon-on-sapphire (SOS), recently have made inroads for the RF switch—at the expense of GaAs. Most PAs are still based on GaAs, but the tide is slowly turning. For example, Peregrine Semiconductor is developing an SOS-based PA for a future smartphone at Apple, according to RBC Capital Markets.

Generally, RF chipmakers make GaAs-based devices in their own fabs. Chips based on RF CMOS, RF SOI and SOS generally are outsourced to the foundries. RF SOI is not a difficult technology to develop, but the real issue is that the sector could meet the same fate as BCD. As it turned out, the BCD market was not big enough to support a dozen foundries, prompting a shakeout in the arena.

In all likelihood, there is room for only a handful of RF SOI foundry players. “I would say IBM and TSMC are the only ones that have the economies of scale (in RF SOI),” said Doug Freedman, an analyst at RBC. “IBM is the leader in RF SOI right now, with TSMC trying to play catch-up. There are some other vendors like TowerJazz in the market, as well.”

From a supply/demand perspective, there is already ample RF SOI capacity to meet demand right now. “I have heard that capacity in RF SOI is adequate,” said Christopher Taylor, an analyst with Strategy Analytics. “I would have my doubts about the prospects of serious shortages barring compelling information to the contrary. Also, in light of the fact that RF SOI does not really push into the CMOS, small-node frontier, there is potentially quite a bit of capacity available from older fabs and foundries at the higher nodes.”

Rushing into RF SOI
The stakes are high, especially as RF content continues to increase in the latest mobile devices. In total, the PA market is expected to grow from $1.7 billion in 2008 to $3.8 billion by 2015, according to RBC. The multi-throw RF switch market is projected to grow from $262 million in 2008 to $1.2 billion by 2015, according to RBC. And the tunable capacitor market is expected to reach $500 million by 2016, it said.

“Driving this growth is rising handset and tablet units, which requires a greater amount of PA ICs,” RBC’s Freedman said. “Principally driving (RF switch) growth is rising radio bands. Driving (tunable capacitor) growth is the wider frequency range of bands and the need to reduce antenna size without performance trade-off.”

There is also an increase in design complexity amid a transition from 3G networks to the next-generation, 4G/LTE wireless standard. “LTE and carrier aggregation are thorny problems even in the best of situations,” said Michael Noonen, executive vice present of global sales, marketing, quality and design at GlobalFoundries. “You also want to be as Spartan as possible in the RF front-end design from a battery consumption standpoint.”

GlobalFoundries, which has been expanding its RF process offerings, is “very much interested” in RF SOI, Noonen said. “We have a lot of experience with SOI, but there are also other approaches in RF,” he said.

Indeed, OEMs face a series of complex device and process choices. For years, GaAs has dominated the RF landscape. GaAs has a larger energy gap and is faster than silicon, but it is more expensive to manufacture. RF CMOS, RF SOI, SOS and silicon-germanium (SiGe) are also in the mix. The RF version of SOI combines CMOS with a highly-resistive, thick-film SOI substrate.

RF SOI is an alternative to GaAs, with equivalent insertion loss and noise isolation characteristics. RF SOI also enables OEMs to integrate various chips on the same die. Another technology, SOS, makes use of an insulating sapphire substrate. And SiGe is built with silicon transistors to create RF circuits.
Meanwhile, after years of promises, RF SOI and its variants are finally cracking the RF front-end. OEMs are moving from GaAs pHEMT to RF SOI and SOS for the RF switch, said Paul Boudre, chief operating officer at Soitec, an SOI wafer supplier. “GaAs pHEMT will not disappear, but it will remain for more specific devices,” Boudre said.

Actually, the buzz started when Apple incorporated Peregrine’s SOS-based RF switches in the iPhone 5. Samsung’s Galaxy S4 and other smartphones are also using SOS-based switches, according to RBC. SOS is a proprietary technology that is only offered by Peregrine. Its SOS chips are made on a foundry basis by Lapis, MagnaChip and Silanna.

Rodd Novak, chief marketing officer of Peregrine, said SOS has better insulating properties than RF SOI. SOS also uses sapphire wafers, making it a more expensive than RF SOI. But the overall cost for SOS is declining. This is because sapphire wafers are ramping up in high-volume markets like LEDs, which will impact the cost of SOS, Novak said.

Peregrine recently rolled out a new version of SOS, based on 0.35-micron technology. “Before, we grew an epi (layer) on top of our sapphire process,” Novak said. “Now, we are taking a very clean silicon substrate and bonding that to the sapphire. That process enables better performance.”

Apple to drive SOI?
The fact that Apple and other OEMs have adopted SOS and RF SOI for the RF switch has given the technology some credence. It also has caused a stampede of foundry players looking to enter the RF SOI sweepstakes.

Now, with help from the foundries, RF chipmakers are looking to displace SOS-based switches with traditional and less-expensive RF SOI technology. “RF switches are typically based on GaAs pHEMT, SOS and SOI, with SOI gaining more and more market share away from the other and more expensive technologies,” said Marco Racanelli, senior vice president and general manager at TowerJazz.

In addition to cost, OEMs are also interested in capacity. In one effort to ensure supply, IBM recently signed a second-source foundry deal for its 0.18-micron, RF SOI process with Altis.

Besides the RF switch, the next big market for RF SOI and SOS could be the PA, with Apple emerging as the possible driving force. “We believe that Peregrine is developing a unique integrated PA solution that is targeting the next generation of Apple’s PA product needs,” said RBC’s Freedman. “(This) could add approximately $1.25 in content, assuming (Apple integrates) five to six single PAs in 3G smartphones. We note that in 4G, PA content opportunity rises to approximately $3.00 due to rising single chip PAs per device.”

In another example, Qualcomm recently rolled out the RF360, an RF front-end that includes a PA based on SOI. Today, however, the jury is still out for PAs based on RF SOI and SOS. For the PA, GaAs still has a higher power-efficiency over CMOS.

Still, the handwriting is on the wall for GaAs. “For the PA, SiGe BiCMOS has strong market share in WiFi, while GaAs HBT has strong market share in cellular. RF CMOS is relegated to the very low-end 2G/2.5G cellular space,” TowerJazz’ Racanelli said. “SOI for the PA is only in R&D and may not deliver the best performance by itself. But combined with switches and other functions, (SOI-based PAs) could become relevant as new architectures are adopted. Our view is that SiGe has the best tradeoff in performance. The cost structure is closer to CMOS/SOI. SiGe is likely to gain more ground in the future.”

Also in the RF front-end, there is a tunable capacitor, which tunes the antennae to boost efficiencies. Peregrine is selling SOS-based tunable devices. Paratek and STMicroelectronics are selling components based on barium strontium titanate (BST). And WiSpry is offering a MEMS solution.

“There are two vectors worth exploring here,” GlobalFoundries’ Noonen said. “If you can do something in CMOS, it will be done in CMOS. We will see other ways to approach the problem. Using a tunable capacitor based on MEMs, for instance, you can attack the problem from an entirely different angle.”

Indeed, in the RF front-end, there is no one-size-fits-all technology; OEMs likely will adopt several types of chips and processes. “We will also see more functionality in the RF subsystem,” Noonen said. “The idea is to bring RF into more of a mainstream technology.”

By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss future lithography challenges with Serge Tedesco, lithography program manager at CEA-Leti; Laurent Pain, lithography lab manager at CEA-Leti; and Raluca Tiron, a senior scientist at CEA-Leti.

SMD: CEA-Leti has two major and separate programs, including one in directed self-assembly (DSA) and another in multi-beam e-beam. Let’s start with DSA. What is CEA-Leti doing in DSA?
Pain: For DSA, we have what we call the ‘Ideal’ program. We are developing 300mm processes. We have materials development with Arkema. Other partners include TEL and Sokudo. We are working with STMicroelectronics to transfer the technology from a process point of view. We are developing this capability for lab scaling to industry production.

SMD: What have you demonstrated with DSA?
Pain: We have demonstrated resolutions down to 18nm half-pitch, which is considered the 7nm logic node. We think we can extend PS-b-PMMA down to the 7nm node. The concept is to enable 7nm to 4nm resolutions with Arkema’s materials.

SMD: The big question is when do you think DSA will move into production?
Pain: From my point of view, it should be 10nm. You will start to see some demonstrations at 14nm.
Tedesco: You can ask me that in July. I still say 2014.

SMD: What are the challenges with DSA?
Pain: There will be some challenges in terms of defectivity and process maturity.
Tiron: For contact shrinks, the processes are here. It’s stable. That means you can absorb a lot of the variations with the block copolymers. But you don’t have pitch or density. If you move to contact doubling, you have the density. But you lose the process window stability. The placement of the contacts is also less certain. But what is important is now we have materials, processes and tracks. What we really need now is some real fabrication. The applications depend on the end-user. What we need is the end-users to tell us: ‘We need this and that and then move in that direction.’ That’s what is missing today.

SMD: What have you accomplished in your DSA process flow?
Tiron: We have implemented a process flow on a 300mm track, which comes from Sokudo. We have a complete DSA process cycle in one track. The track handles the brush coat and block copolymer coating. The track also has high temperature hot plates for block copolymer cure. We also worked with Sokudo to develop a PMMA removal process. We demonstrated different exposure treatments and solvents. What we are trying to do now is address contact hole shrinks and contact multiplication. With the polymers from Arkema, we are able to do resolutions from 20nm period, which means 10nm resolution, to 60nm period, which means 35nm resolution. Contact shrink is possible using both cylindrical and lamellar morphologies.

SMD: What about yield or defects?
Tiron: We have shown good uniformities with three sigma around 2nm. After the optimization of the process, we counted 6,800 divisional points on the wafer. We only found five missing contacts. By using block copolymers, we showed 99.93 % valid contacts on the wafer. This is just using PMMA.

SMD: Let’s move to multi-beam. What is CEA-Leti doing in multi-beam?
Pain: The second program is called Imagine. This program started last year. We have a partnership with (multi-beam e-beam vendor) Mapper Lithography. Other partners include Aselta, JSR, TOK, TSMC, Sokudo, Dow, STMicroelectronics, TEL and Mentor.

SMD: How far along is Mapper’s multi-beam tool?
Pain: The first machine will consist of 1,300 beams. The throughput is one wafer per hour. The tool will arrive the beginning of June. That’s targeted for the 14nm logic node. This machine will be interfaced with the Sokudo track. The first exposures will start in the last quarter of this year. Eventually, the target is to reach 16nm half-pitch. Our goal is to have 13,000 beams with the Mapper tool. We expect to scale the throughput from one wafer per hour to 10 wafers an hour. Then, we plan to push the resolutions down to 10nm half-pitch.

SMD: What is the cost-of-ownership for the Mapper tool?
Pain: The cost is 1 million euros for two wafers per hour. So in other words, that’s 5 million euros for 10 wafers per hour. Our eventual goal is to cluster 10 machines together. That’s 50 million euros for the cluster configuration.

SMD: Isn’t multi-beam taking longer than expected and behind schedule?
Pain: If you take the original roadmap, we are late. Some of the technical achievements have taken a long time.
Tedesco: One of the problems is there is a lack of support from the industry. It’s a shame that there is a lack of support, when you look at what’s being done on the EUV side. That’s one of the reasons that multi-beam is not mature yet. Of course, there is the technical aspect. TSMC, of course, is the one that is pushing this technology. But beyond TSMC, there is a lack of support. But I think the support will eventually come.

SMD: TSMC has stated it wants to do all layers with multi-beam. Is that practical or will multi-beam end up doing traditional direct-write applications like ASICs?
Tedesco: It could be a challenge to do all layers with multi-beam. But a maskless tool could be useful in terms of ASICs or prototyping. It’s ideal for the foundries. But the first applications for multi-beam will likely be contact holes and the cut layer.

SMD: How about STMicroelectronics? STMicroelectronics has been involved with direct-write for many years.
Tedesco: ST is a partner of Leti. So they are following Imagine very closely.

SMD: What about funding for multi-beam from the likes of Intel, GlobalFoundries and Samsung?
Tedesco: Good question. What we can say is that they are following us very closely. They know what we are doing. At this point, they are not part of the program.

By Mark LaPedus
Qualcomm has the highest market share for baseband solutions in handsets, resulting in a position far out in front of its competitors. ST-Ericsson has strong products on the market with competitive features. But one analyst at ABI Research questions why ST-Ericsson was broken up just as it finally came out with a highly competitive product, which was based on FD-SOI.

The worldwide semiconductor foundry market totaled $34.6 billion in 2012, a 16.2% increase from 2011, according to final results by Gartner. TSMC maintained the No. 1 spot in the rankings in 2012. Strong performance on 32nm yields and the availability of sub-45nm wafer capacity at the Dresden, Germany, fabs allowed GlobalFoundries to advance to the No. 2 position in 2012. UMC‘s market share decreased due to reduced wafer shipments. Driven by the wafers consumed by Apple, Samsung moved up four spots to the No. 5 position with 175.5% growth in 2012.

At this year’s Symposium on VLSI Technology, Intel will report technical details of its embedded DRAM with 22nm technology on bulk silicon wafers. Intel realized a 0.029mm2 DRAM cell capable of meeting >100us retention at 95 C. In the DC-DC converter session, Intel will present a switched capacitor step-down converter designed in a 22nm tri-gate CMOS technology. The VLSI Symposium is slated for June 11–14 in Kyoto, Japan.

At the VLSI event, STMicroelectronics and CEA-LETI will report six transistor SRAM (6T-SRAM) cells for high-density and low-voltage. The technology is fabricated at the 28nm node using FD-SOI technology for the first time.

At the VLSI Symposium, IBM and GlobalFoundries will report a SiGe channel tri-gate pFET with aggressively scaled fin width and gate length dimensions. It is fabricated using SiGe on an insulator substrate. Excellent electrostatic control down to Lg= 18nm and Wfin<18nm has been reported.

At the event, IMEC and GlobalFoundries will present the first demonstration of strained germanium channel pFETs fabricated on SiGe strain relaxed buffers, which is surrounded by STI region. Also, they introduced raised SiGe source/drain structures (Ge concentration= 75%) with an implant-free quantum well, replacement metal-gate process and germanide in contacts to solve void issues.

In addition, STMicrolectronics, Samsung, GlobalFoundries and IBM will report a 64nm pitch BEOL integration and material strategy. A self-aligned-via (SAV) approach was exploited for single pattern via extendibility, enabling via placement at CPP with a single mask.

SEMI reported that for the quarter ending Dec. 31, 2012, the worldwide photovoltaic manufacturing equipment book-to-bill ratio remained well below parity, at 0.45, for the seventh consecutive quarter. Booking levels continue to be low as PV manufacturers grapple with oversupply across the supply chain.

Khaled Juffali Company (KJC), a Saudi Arabian investment company, and Soitec, signed a memorandum of understanding (MOU) to cooperate in driving solar industry growth in Saudi Arabia and the Middle East. Under the MOU, the two companies will create a joint venture to market and sell concentrator photovoltaic (CPV) systems in the Kingdom of Saudi Arabia.

Hwa Chong Institution emerged as the winner of the Applied Materials Clean Tech Competition in Singapore. The project focused on utilizing calcium carbonate found in clam shells to remove toxic metal ions from waste water.

The separate hardware and software teams in companies are notorious for not being on the same page, thereby putting product development times and cost at risk. Mentor Graphics CEO Walden Rhines outlined some new and practical solutions to the problem.

Mentor Graphics announced the release of the Mentor Embedded Sourcery CodeBench Virtual Edition product, a native software environment for developing embedded systems pre- and post-silicon. The tool provides a tighter connection between hardware and software co-development, but allows software developers to use existing programming tools with extensions.

Cadence announced results for the first quarter of fiscal year 2013. Cadence also completed its previously announced acquisition of Tensilica.

Advantest will acquire W2BI, a provider of system level test automation software focusing on wireless communications.

Shipments of smart glasses may rise to as high 6.6 million units in 2016, up from just 50,000 in 2012, for a total of 9.4 million units for the five-year period, according to an upside forecast from IMS Research.

The worldwide mobile phone market grew 4% year over year in the seasonally slow first quarter of 2013 as smart phones out-shipped feature phones for the first time, according to IDC. Nokia, BlackBerry and HTC have dropped out of the top rankings.

By Mark LaPedus
What impact will Intel have on the overall foundry business? In a research note, Weston Twigg, an analyst with Pacific Crest Securities, said: “Competition between Intel and the foundries, and the foundries and each other, should force high spending at the leading edge over the next two to three years. We remain bullish on equipment demand as long as Intel continues to play an aggressive role in the x86 versus ARM battle and its new foundry effort. We believe Intel is attempting to exploit its manufacturing technology advantage, which should pressure rivals TSMC and Samsung to maintain aggressive node transition plans.”

Staying in the leading-edge process technology race requires deep pockets. At 20nm and beyond, chipmakers will have to raise the CapEx ante to stay in the race. “Capital and production costs are rising faster than historic levels as logic and foundry producers migrate to 20nm and below,” Twigg said. “We expect equipment costs to rise 25% at the 22nm node and 28% at the 14nm node. New gate technologies, along with multiple-patterning steps and pitch-splitting techniques, are driving costs higher.”

GlobalFoundries has announced several milestones in the 2.5D/3D chip arena—a series of events that brings the technology one step closer to mass production.

In coordination with the National Academy of Sciences, GlobalFoundries helped host a conference titled, “New York’s Nanotechnology Model: Building the Innovation Economy” at the Hudson Valley Community College in Troy, N.Y.

Fabless ASIC house Socle Technology named Michael Noonen as its new chairman. Noonen is still the executive vice president of global sales and marketing at GlobalFoundries, which is an investor in Socle.

The Silicon Integration Initiative (Si2) said that the ESD Working Group of the OpenPDK Coalition has released an ESD Protection Design Flow Methodology. The ESD Working Group that developed this document included representatives from IBM, Intel, GlobalFoundries, NXP, Samsung, and STMicroelectronics.

Mentor Graphics announced availability of a comprehensive IP-to-system, UPF-based low-power verification flow.

ARM and Cadence disclosed the details behind their collaboration to implement the first ARM Cortex-A57 processor on TSMC’s 16nm finFET process.

Peregrine Semiconductor said that its UltraCMOS phase locked loop (PLL) frequency synthesizer and prescaler devices are designed into six Globalstar mobile communication satellites that were launched into orbit in February. UltraCMOS is an advanced RF silicon-on-Insulator (SOI) process.

Randhir Thakur, executive vice president and general manager of the Silicon Systems Group at Applied Materials, has been named a fellow of the Institute of Electrical and Electronics Engineers (IEEE).

Sematech executive Raj Jammy has joined Intermolecular as senior vice president and general manager of the semiconductor group.

RF Micro Devices announced the appointment of James Clifford, a former executive at Qualcomm, as vice president of foundry services.

More than one quarter of installed wafer capacity worldwide is dedicated to producing IC devices using process geometries smaller than 40nm, according to IC Insights.

In 2012, Intel retained the No. 1 market share position for the 21st year in a row, according to Gartner. Qualcomm climbed from No. 6 in 2011 to No. 3, and now trails only Intel and Samsung. Texas Instruments retained its fourth-place ranking, although Toshiba slipped to fifth place.

By Mark LaPedus
Sara Volz, 17, of Colorado Springs, Colo., won $100,000—the top award—from the Intel Foundation for her research on algae biofuels. Algae produces oil that can be converted into a sustainable, renewable fuel. Volz, who built a home lab under her loft bed, sleeps on the same light cycle as her algae.

For years, the investment community has demanded that ASM International (ASMI) should break up the company into two pieces. This week, ASMI finally caved in, leaving some to wonder if the company is the next takeover target in the semiconductor equipment business. ASMI intends to sell a stake in ASM Pacific Technology, valued at between 8% to 12%. Following the planned divestment, ASMI will own between 40% and 44% of the shares in ASM Pacific, a supplier of wirebonders.

A TEM image taken at Applied Materials’ Maydan Technology Center shows a series of 20nm-wide trenches in a cross section. What does this all mean? According to Applied, it’s a breakthrough in reflow to push interconnect boundaries beyond 20nm.

Applied Materials was named by the Ethisphere Institute, a business ethics think-tank, as one of the 2013 world’s most ethical companies.

MEMC, a supplier of silicon and SOI wafers, announced a plan, subject to shareholder approval, to change its name to SunEdison. The name change reflects its recent efforts in the solar industry. MEMC competes in both the semiconductor and solar industries. Does the name change reflect that semis are passé or does MEMC have an identity crisis?

Specialty foundry TowerJazz is seeing significant customer engagements and market share gain in the fast growing RF front-end module market. For Skyworks and others, TowerJazz is providing RF SOI, RF CMOS and SiGe processes.

ALTIS Semiconductor announced the finalization of a foundry agreement with IBM Microelectronics. Under the terms, ALTIS will be the foundry partner for the IBM 180nm RF SOI technology.

SEMI reported that worldwide sales of semiconductor manufacturing equipment totaled $36.93 billion in 2012, representing a year-over-year decrease of 15%.

Cadence has agreed to buy Tensilica, setting the battle over IP into high gear among EDA vendors.

Mentor Graphics announced the Nucleus SmartFit product, a cost-effective, binary version of the Nucleus RTOS optimized to fit the limited internal memory of 32-bit MCUs.

ST-Ericsson, a joint venture of STMicroelectronics and Ericsson, announced that Didier Lamouche, president and chief executive, has decided to resign from the company to pursue other opportunities. And following those events, Ericsson and STMicroelectronics this week announced an agreement on the fate of ST-Ericsson. Ericsson will take on the design, development and sales of the LTE multimode thin modem products, including 2G, 3G and 4G multimode. ST will take on the existing ST-Ericsson products, other than LTE multimode thin modems, and related business as well as certain assembly and test facilities. The companies will close down the remaining parts of ST-Ericsson.

China’s Advanced Micro-Fabrication Equipment (AMEC) will make its solid-state lighting market debut with a new multi-reactor metal organic chemical vapor deposition (MOCVD) cluster tool. The Prismo D-Blue MOCVD platform enables high-volume manufacturing of GaN, InGaN and AlGaN structures required for high-brightness LEDs.

Nanoplas announced a new dry-etch process that offers unlimited etch selectivity for removing dielectric films. Nanoplas’s new Atomic-Layer Downstream Etching (ALDE) processing allows etching rate and selectivity to be controlled independently.

According to IHS, the steady increase in PC capabilities that has justified the upgrade cycle and fueled the long-term growth of the PC market is undergoing a historical deceleration.

Household adoption and spending on consumer technology products is shifting faster than expected in favor of gadgets and services that are portable or mobile, according to a recent survey by Gartner.

By Mark LaPedus
Is China set to bail out a U.S. government technology darling? Two Chinese automotive companies, Geely and Dongfeng Motor, are reported to have bid between $200 million and $350 million for a majority stake in Fisker, the maker of plug-in hybrid cars. If that happens Fisker—which has $192 million in U.S. federal government loan guarantees—could be headed to China, according to Lux Research.

Over the years, Apple has moved deeper into IC design. In an e-mail newsletter, Will Strauss, president of Forward Concepts, indicated that Apple could be expanding its efforts in wireless ICs, a move that might impact Broadcom, Qualcomm and others. “There is a rumor published in Israel that Apple will be designing its own baseband and Wi-Fi chips,” Strauss said. “When Texas Instruments dropped out of the cell-phone business, within a week about 100 of the former TI engineers in Israel were hired by Apple. Of course, Apple once hired a bunch of former VLSI Technology wireless engineers, but I understand that that operation came to naught. So, maybe Apple just wanted more engineering talent.”

In a separate research note, Doug Freedman, an analyst with RBC Capital Markets, said: “After talks with management dating back from CES to today (Feb. 25), we believe that Intel is becoming increasingly closer to inking a material foundry design win(s).” Intel is in consideration to be a potential foundry partner for Apple. “Intel’s foundry aspirations may come to light soon,” he said. Apple is also supposedly doing a 20nm foundry deal with TSMC.

Taking the process technology lead in the FPGA market, Achronix Semiconductor is shipping the first in a family of devices based on Intel’s 22nm finFET technology. Achronix’ FPGAs are built using Intel’s foundry services. Achronix says that it has a two- to three-year lead over Altera and Xilinx, which are still shipping 28nm planar devices. The event has prompted two questions. First, will Altera and Xilinx turn up the heat on their FPGA foundry partner, TSMC, to accelerate its finFET efforts? Or second, will Altera and Xilinx turn to Intel over time?

CEA-Leti will coordinate a four-year project aimed at building a European-based supply chain in silicon photonics and speeding up the industrialization of the technology. Mentor Graphics, PhoeniX BV and Si2 will work together to develop a common reference platform. STMicroelectronics, Tyndall-UCC, Aifotec and others are also part of the group.

Mentor Graphics has expanded its automotive business unit by purchasing certain assets from MontaVista. This establishes Mentor as a bigger commercial provider of Linux-based automotive in-vehicle infotainment (IVI) solutions.

Mentor announced the 10.2 release of the Questa functional verification platform. In addition, Tesla Motors has standardized on Mentor’s Capital toolset for 12-volt electrical systems design.

With FD-SOI, STMicroelectronics said that application processors manufactured at its fab are capable of operating at 3 GHz.

Soitec and Sumitomo Electric have signed a licensing and technology-transfer agreement. Sumitomo will use Soitec’s Smart Cut technology to manufacture engineered gallium nitride (GaN) substrates. GaN substrates are used in high-performance light-emitting diode (LED) lighting applications.

GlobalFoundries announced enhancements to its 55nm Low-Power Enhanced (LPe) process technology platform. The so-called 55nm LPe 1V has been qualified with next-generation memory and logic IP solutions from ARM.

Are happy days here again for fab tool vendors? The book-to-bill ratio is above parity for the first time in recent memory. North America-based manufacturers of semiconductor equipment posted a book-to-bill ratio of 1.14 in January, according to SEMI. This compares to a ratio of 0.92 in December.

Intersil cut its global work force by approximately 18%. This comes on the heels of the resignation of the company’s CEO.

Sony introduced the PlayStation 4, which is based on AMD’s single-chip, eight-core custom processor. The x86 processor, dubbed Jaguar, is a 28nm device built by TSMC.

Five IC suppliers are expected to hold one-third of 300mm wafer capacity in 2013, according to IC Insights. Samsung was by far the leader in 2012, having about 61% more 300mm capacity than second-place SK Hynix. Intel was the only other company that held a double-digit share of 300mm capacity at the end of 2012.

Qualcomm dominated the LTE cell-phone modem market with a staggering 86% share in 2012, according to Forward Concepts. In total, Qualcomm shipped 47 million FDD-LTE cell-phone modems last year. Samsung followed with 9% of the shipments in 2012, while GCT Semiconductor managed to grab 3% of the market, primarily through LG handsets, according to the firm. Renesas Mobile and Nvidia-Icera each garnered 1% market shares.

The number of China Mobile 4G subscribers is forecast to reach 228.8 million in 2017, representing 52 percent of China’s 439.9 million total 4G users, according to IHS. In comparison, 4G users from China Unicom and China Telecom, the country’s two other major telecommunications operators, will number 114.4 million and 96.8 million, respectively.

By Mark LaPedus
The IC industry entered the finFET era in 2011, when Intel leapfrogged the competition and rolled out the newfangled transistor technology at the 22nm node.

Intel hopes to ramp up its second-generation finFET devices at 14nm by year’s end, with plans to debut its 11nm technology by 2015. Hoping to close the gap with Intel, silicon foundries are accelerating their efforts to introduce their initial finFET processes at 14nm. And the foundries are already defining their next-generation finFETs at 10nm.

Chipmakers face numerous challenges in terms of ramping up their first- and next-generation finFETs. But the challenges, and costs, could pale in comparison when vendors extend finFET technology to the 7nm and 5nm nodes—or perhaps beyond.

Starting at 7nm, chipmakers plan to inject finFETs with various and exotic III-V materials in the channels to boost the mobility, which refers to how fast the electrons can move through a device. Currently, the industry has narrowed the options down to about five leading candidates for the high-mobility finFET era: finFETs with germanium (Ge) for the PFET; finFETs with Ge for both PFET and NFET; and finFETs with Ge for PFET and III-V materials for NFET.

The two possible spoilers are tunnel field-effect transistors (TFETs) and nanowire-based gate-all-around finFETs. “Conventional thinking currently suggests that we will see a Ge PFET and an InGaAs NFET at 7nm,” said Dean Freeman, an analyst with Gartner. “If the industry could make a silicon nanowire, and create a transistor using silicon and high-k/metal-gate, then we could see the industry move in that direction.”

The III-V materials themselves exist today, but many of the associated manufacturing techniques are in their infancy or simply don’t exist. Bringing up compound semiconductor materials in silicon fabs is a monumental task. And the ability to design and integrate III-V finFETs in a cost-effective manner is easier said than done. “This is not a straightforward process,” said Luc Van den hove, chief executive of IMEC. “We are talking about materials with different lattice constants.”

The challenges leave some observers wondering whether chipmakers should skip the high-mobility finFET era and move directly to the more exotic technologies like carbon nanotubes and graphene. Perhaps the best avenue is the pursuit of stacked 2.5D/3D devices.

Looking into his crystal ball, Gary Patton, vice president of IBM’s Semiconductor Research and Development Center, predicts the two 3D-like approaches, finFETs and stacked die, will have a long and viable future. “The 3D era should carry us well into the 2020 timeframe,” Patton said. “I expect finFETs will last a decade. But then at some point, we hit the atomic dimension limit. Then, we’re talking about silicon nanowires and carbon nanotubes. And to deal with the interconnect issues, we have to talk about integrating photonics on the chip and stacking multiple chips together. That’s really in the next decade.”

Take III-V
Today, the industry is moving towards an inflexion point. For foundries, 20nm represents the last node in the planar era, because planar is beginning to suffer from undesirable short-channel effects. So, at 14nm, foundries will introduce finFETs, which have better short-channel electrostatic characteristics than planar.

Today’s finFETs will likely scale at least two generations to 10nm, said Subramani Kengeri, vice present of advanced technology architecture at GlobalFoundries. Then, at 7nm, the industry is looking at next-generation finFETs based on III-V materials to provide a mobility boost, Kengeri said.

The next roadblock is that today’s strained-silicon technology is under stress. For some time, chipmakers have used a silicon-germanium (SiGe) alloy stressor in the channel to boost carrier mobility. “Starting from the 90nm and 65nm nodes, the source-drain areas have been grown using a SiGe epi process in order to bring strain into the device,” said IMEC’s Van den hove. “With strain, we can increase the drive current and device mobility. In the finFET structure, we can do that as well. But this space is very limited, because of the [difficulties] to introduce enough strain into those tiny channels. An alternative way to boost the drive current is by using materials that have intrinsically higher mobilities. This will reduce power consumption.”

The first of these high-mobility devices is expected to appear at 7nm, with the emergence of a finFET with Ge in the p channel and tensile silicon in the n channel. Ge has an electron mobility of 3,900cm-square-over-Vs, compared to 1,400cm-square-over-Vs for silicon.

“But germanium in the p channel is not a straightforward process,” said Aaron Thean, director of the logic program at IMEC. “Germanium tends to move around once exposed to temperature. So the challenges are defects and the structural stability of the device. The surface passivation (for the high-k/metal-gate stack) is also very tricky.”

Following this device, the industry will move to a next-generation high-mobility finFET at 7nm. The first option is a finFET with Ge for both the p and n channels. The second option is Ge for the p channel and indium gallium arsenide (InGaAs) for the n channel. InGaAs has an electron mobility of 12,000cm-square-over-Vs.

“Those two options are competing,” Thean said. “The germanium-germanium option requires compressively strained Ge in the p channel and relaxed Ge in n channel. There are issues with the gate stack and dopant activation.”

Intel and others are leaning toward the Ge-InGaAs option. “InGaAs is our front-up option. It can offer mobilities up to 10X and higher. It’s a better-understood III-V material. I wouldn’t say InGaAs is easy in terms of processing, but it is not as challenging of a material to handle,” Thean said.

The other 7nm candidate is the gate-all-around (GAA) finFET, which can have two or more gates that are wrapped around by a nanowire channel. Purdue University, for one, recently demonstrated GAA finFET with 20nm channel lengths and a sub-threshold swing of 63mV/decade. “There are still lots of challenges with GAA,” said Jiangjiang Gu, a Ph.D. candidate at the Department of Electrical and Computer Engineering at Purdue. “We still need to address the source/drain contact issue. The surface roughness needs to be improved and the variability issues need further study.”

Intel and others also have shown interest in the TFET, which may appear at 5nm. In TFET, a tunnel barrier is created at the source-channel contact to increase the drive currents. Using III-V materials, the TFET promises to scale the supply voltage beyond 0.5 volts, said Mark Bohr, senior fellow of the technology and manufacturing group at Intel. “TFETs enable steeper sub-threshold voltages,” he said.

There are other options, such as exotic III-V materials for both NFET and PFET. Other III-V materials, including indium antimonide (InSb), are still in R&D. The Sb materials are promising, but have narrow band gaps.

Tool gaps
All of the futuristic, high-mobility finFET devices suffer from the same problem—they are expensive and difficult to manufacture. The most obvious problem is lithography. It’s still unclear if extreme ultraviolet (EUV) lithography will be ready for the 7nm node, meaning the industry may need to extend 193nm immersion and multiple patterning.

Patterning is only one piece of the finFET puzzle. “Lithography has been the story for at least the last 10 years,” said Mike Splinter, chairman and chief executive of Applied Materials. “Now, we are seeing many of the bottlenecks in interface engineering, precision materials and how are you going to get the low-k values.”

For example, RF chipmakers have been fabricating III-V chips in trailing-edge fabs at smaller wafer sizes. At 7nm, the challenge is to grow III-V materials on 300mm or 450mm silicon wafers with good yields and throughput.

It’s unclear which technology, bulk or FD-SOI, will prevail at 7nm and beyond. STMicroelectronics says FD-SOI can extend to at least 10nm and perhaps beyond. “We are continuing to look at SOI,” said IMEC’s Thean. “The nice thing about fully-depleted devices on SOI is that they have excellent isolation.”

In one emerging SOI effort, Ed Nowak, device chief designer at IBM, recently described a fin-on-oxide (Fox) technology that could scale to 5nm. Fox enables a finFET technology with oxide dielectric isolation. Like SOI, Fox enables the finFET manufacturer to produce a controlled fin height, thereby reducing variability. Silicon wafer maker MEMC recently rolled out SOI substrates based on Fox.

The integration between III-V and silicon is perhaps the biggest issue. “In III-V, for example, we use gold as a contact material,” said Raj Jammy, vice president of emerging technologies at Sematech. “Gold is a poisonous material for silicon. So, you need to come up with a new contact metal scheme.”

There is also a need for new metrology tools to find defects in III-V finFETs. New tools are also are required for GAA finFETs with nanowires. “When it comes to gate all-around, you need selective ALD processes,” Jammy said. “For fin/gate fidelity, this requires selective III-V/Ge epi. For etch, we might not be able to use the processes we have today. We are looking into ALD etch.”

The industry is making progress on one front. “One of the areas we are looking at is a low damage conformal 3D doping technique, which we call monolayer doping,” he said. “This enables selective and very shallow junctions. We have solutions with arsenic and phosphorous. What is exciting about this is that the fins that have monolayer doping don’t have any damage.”

All told, high-mobility finFETs promise to enable chip scaling, but the challenges and costs are steep. “There is no free lunch,” he added.

By Mark LaPedus

The recent Nano Job Fair in New York exceeded the 800 registrant capacity. Due to the overwhelming response, and the need to fill an additional 300 jobs, another job fair will be scheduled in the next few months. The fair itself filled more than 300 current and future openings at the CNSE, including positions with the Global 450mm Wafer Consortium (G450C).

China’s transition from a low-cost manufacturing hub to an innovation hotspot with growing foreign ambitions represents both a threat and an opportunity, according to Lux Research. Foreign acquisitions worth $28 billion are just the beginning of China’s global ambitions, according to the firm.

The Chinese IC market is forecast to have a 2012 to 2017 compound annual growth rate (CAGR) of 13%, five points higher than the 8% CAGR forecast for the total IC market during this same time period, according to IC Insights. By 2017, China is expected to represent 38% of the worldwide IC market, up from 23% in 2007, according to the firm.

Skyworks announced its results for the quarter. The company has also garnered some RF antenna tuning design wins, some of which are based on silicon-on-insulator (SOI) technology, said David Aldrich, president and CEO of the RF chip maker, on the Seeking Alpha Web site.

STMicroelectronics announced its results for the quarter. During a conference call, Carlo Bozotti, president and CEO of ST, said the company is developing ASICs for various applications using FD-SOI technology. ST also is looking at strategic options for ST-Ericsson, the cell-phone chip venture with Ericsson, he said. The venture recently rolled out a chip based on FD-SOI.

Following the announcement of STMicroelectronics’ intention to exit as a shareholder of ST-Ericsson, Ericsson is also exploring various strategic options for the venture.

Kilopass, a provider of semiconductor intellectual property (IP), will demonstrate its one-time programmable (OTP) memory IP on IBM’s 45nm, silicon-on-insulator (SOI) technology at the Common Platform Technology Forum. The event, which is on Feb. 5, will take place in Santa Clara, Calif.

Mentor Graphics announced the latest release of its HyperLynx product for superior high-speed design and analysis.

Chipmakers must explore, and embrace, new design methodologies to cut costs and boost cycle times. One way to bolster the design flow is to rethink the register-transfer level (RTL) synthesis process.

Applied Materials said that George Davis, executive vice president and chief financial officer, will depart the company effective March 8. The company expects to name a successor in the coming weeks. Davis will become CFO for Qualcomm.

SEMI and the U.S. Photovoltaic Manufacturing Consortium (PVMC) announced the signing of a memorandum of understanding (MOU) to enhance their cooperation in the areas of standards and roadmap activities for the solar thin film industry.

Renesas continues to cut costs. The company has sold its backend operations to J-Devices.

American Semiconductor has a process that transforms standard silicon wafers into flexible wafers. The technology is now available on TowerJazz’ CMOS foundry process.

Worldwide tablet shipments outpaced predictions, reaching a record total of 52.5 million units worldwide in the fourth quarter of 2012, according to IDC. Samsung is gaining ground on Apple, according to the firm.

VLSI Research says the IC industry will grow 10.1% in 2013. “We expect (the IC industry) to be an ASP-driven upturn,” according to the firm. “Even though the Chinese New Year is still weeks away, chipmakers are becoming more optimistic about 2013. This is driven in part by a modest improvement that is taking place at the macro level. The visibility for the U.S. economy has improved considerably. China’s macro data has also been positive and the European debt crisis appears to be fading.”

Chip inventory held by semiconductor suppliers reached alarmingly high levels in the third quarter of 2012 amid weak market conditions, according to IHS iSuppli.

By Mark LaPedus
Apple apparently is switching foundry vendors from Samsung to TSMC. Still, Samsung is moving forward with its U.S. fab plans. The company announced that a $4 billion fab investment at its Austin, Texas, site is on schedule for production of mobile application processors within the second half of 2013. The remodeled fab line will produce mobile application processors on 300mm wafers at the 28nm node. C.J. Muse, an analyst with Barclays, said Samsung will cut its capex by 50% in 2012 over 2011. “The actual range is likely to be down 30%-50% year-over-year, with a bigger cut on the logic side (due to the likely loss of the Apple business) and a more muted cut on the memory side.”

In a decision that will support nearly 10,000 high-tech jobs, the Export-Import Bank of the United States (Ex-Im Bank) has approved a $1.03 billion loan to GlobalFoundries to finance the export of American-made semiconductor manufacturing equipment to Germany. Applied Materials is one of the exporters involved in the transaction. “The ability of our customer GlobalFoundries to access this financing benefits Applied Materials’ manufacturing and R&D in the United States, as well as our supply chain, at a time of tremendous global competition for high-tech jobs,” said Mike Splinter, chairman and CEO of Applied, in a statement.

GlobalFoundries has added a 10nm finFET process to its roadmap and expanded its technology platform offerings. The foundry vendor plans to go from 20nm planar in 2013, to 14nm finFET in 2014, to 10nm finFET in 2015, and 7nm finFET in 2017.

At the SOI Consortium’s event at IEDM, Jeff Watt, a fellow at Altera, presented an evaluation and benchmark of planar fully depleted SOI technology. A simulation showed that 20nm FD-SOI provided a 5X reduction in power over 28nm bulk, Watt said. However, Altera has not made a commitment to SOI for FPGAs and is currently evaluating the technology, he said. “We are looking at all options,” he said. For 20nm, Altera plans to use a bulk technology at TSMC. At 14nm, the FPGA house will likely go with bulk finFETs at TSMC. However, Altera is also exploring SOI.

STMicroelectronics unveiled the results of its 28nm production silicon chips using FD-SOI technology, which it claims offers a 30% improvement in speed over bulk CMOS while using less power.

STMicroelectronics took another step towards the availability of its 28nm FD-SOI technology platform. The technology is now open for pre-production from its Crolles 300mm manufacturing facility.

SEMI praised Congressional leadership as the U.S. Senate passed legislation (92-4 vote) to normalize trade relations with Russia. This allows American companies to receive the full benefits of Russia’s recent accession to the World Trade Organization (WTO) by wavering an outdated, Cold War-era amendment that restricted trade.

SEMI reported that worldwide semiconductor manufacturing equipment billings reached $9.06 billion in the third quarter of 2012. The billings figure is 12% lower than the second quarter of 2012 and 15% lower than the same quarter a year ago.

Mentor Graphics announced the new T3Ster DynTIM tester, a method of measuring thermal characteristics of thermal interface materials.

MIPS determined that a new proposal from CEVA to acquire the company constitutes a “superior proposal” to the merger agreement with Imagination Technologies. MIPS is prepared to continue negotiations with Imagination if it adjusts the terms of the merger agreement.

Rudolph Technologies has acquired Azores. The move will enable Rudolph to enter the back-end advanced packaging lithography market.

Test handler specialist Cohu has agreed to acquire Ismeca Semiconductor from Schweiter Technologies for $54.5 million, plus acquired cash, to be funded out of Cohu’s existing cash reserves.

Worldwide semiconductor revenue is projected to total $311 billion in 2013, a 4.5 percent increase from 2012 revenue, according to Gartner.

The solar industry is reeling from overcapacity and supply outstrips demand by two to one. It needs to drive costs lower in order to overcome diminished subsidies and regain profitability, according to Lux Research. Module prices have fallen precipitously over the past four years to a low of $0.70/W but the cost of goods sold (COGS) for modules has not reached this level, resulting in massive losses for most module manufacturers. Solar modules production costs could fall as low as $0.48/W in 2017, according to the firm.