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AI Chips: Challenges and Opportunities

Wednesday, September 12th, 2018

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By Pete Singer, Editor-in-Chief

The exploding use of Artificial Intelligence (AI) is ushering in a new era for semiconductor devices that will bring many new opportunities but also many challenges. Speaking at the AI Design Forum hosted by Applied Materials and SEMI during SEMICON West in July, Dr. John E. Kelly, III, Senior Vice President, Cognitive Solutions and IBM Research, talked about how AI will dramatically change the world. “This is an era of computing which is at a scale that will dwarf the previous era, in ways that will change all of our businesses and all of our industries, and all of our lives,” he said. “This is the era that’s going to power our semiconductor industry forward. The number of opportunities is enormous.”

Also speaking at the event, Gary Dickerson, CEO of Applied Materials, said AI “needs innovation in the edge and in the cloud, in generating data on the edge, storing the data, and processing that data to unlock the value.  At the same time Moore’s Law is slowing.” This creates the “perfect opportunity,” he said.

Ajit Manocha, President and CEO of SEMI, calls it a “rebirth” of the semiconductor industry. “Artificial Intelligence is changing everything – and bringing semiconductors back into the deserved spotlight,” he notes in a recent article. “AI’s potential market of hundreds of zettabytes and trillions of dollars relies on new semiconductor architectures and compute platforms. Making these AI semiconductor engines will require a wildly innovative range of new materials, equipment, and design methodologies.”

”Hardware is becoming sexy again,” said Dickerson. “In the last 18 months there’s been more money going into chip start ups than the previous 18 years.” In addition to AI chips from traditional IC companies such as Intel and Qualcomm, more than 45 start-ups are working to develop new AI chips, with VC investments of more than $1.5B — at least five of them have raised more than $100 million from investors. Tech giants such as Google, Facebook, Microsoft, Amazon, Baidu and Alibaba are also developing AI chips.

Dickerson said having the winning AI chip 12 months ahead of anyone else could be a $100 billion opportunity. “What we’re driving inside of Applied Materials is speed and time to market. What is one month worth?  What is one minute worth?”

IBM’s Kelly said there’s $2 trillion of decision support opportunity for artificial intelligence on top of the existing $1.5-2 billion information technology industry. “Literally every industry in the world is going to be impacted and transformed by this,” he said.

AI needed to analyze unstructured data

Speaking at an Applied Materials event late last year during the International Electron Devices Meeting, Dr. Jeff Welser, Vice President and Director of IBM Research’s – Almaden lab, said the explosion in AI is being driven by the need to process vast amounts of unstructured data, noting that in just two days, we now generate as much data as was generated in total through 2003. “Somewhere around 2020, the estimate is maybe 50 zettabytes of data being produced. That’s 21 zeros,” he said.

Welser — who will be delivering the keynote talk at The ConFab 2019 in May — noted that 80% of all data is unstructured and growing 15 times the rate of structured data. “If you look at the growth, it’s really in a whole different type of data. Voice data, social media data, which includes a lot of images, videos, audio and text, but very unstructured text,” he said. And then there’s data from IoT-connected sensors.

There are various ways to crunch this data. CPUs work very well for structed floating point data, while GPUs work well for AI applications – but that doesn’t mean people aren’t using traditional CPUs for AI.  In August, Intel said it sold $1 billion of artificial intelligence processor chips in 2017. Reuters reported that Navin Shenoy, its data center chief, said the company has been able to modify its CPUs to become more than 200 times better at artificial intelligence training over the past several years. This resulted in $1 billion in sales of its Xeon processors for such work in 2017, when the company’s overall revenue was $62.8 billion. Naveen Rao, head of Intel’s artificial intelligence products group, said the $1 billion estimate was derived from customersthat told Intel they were buying chips for AI and from calculations of how much of a customer’s data center is dedicated to such work.

Custom hardware for AI is not new. “Even as early as the ‘90s, they were starting to play around with ASICS and FPGAs, trying to find ways to do this better,” Welser said. Google’s Tensor Processing Unit (TPU), introduced in 2016, for example, is a custom ASIC chip built specifically for machine learning applications, allowing the chip to be more tolerant of reduced computational precision, which means it requires fewer transistors per operation.

It really was when the GPUs appeared in the 2008-2009 time period when people realized that in addition to the intended application – graphics processing – they were really good for doing the kind of math needed for neural nets. “Since then, we’ve seen a whole bunch of different architectures coming out to try to continue to improve our ability to run the neural net for training and for inferencing,” he said.

AI works by first “training” a neural network where weights are changed based on the output, followed by an “inferencing” aspect where the weights are fixed. This may mean two different kinds of chips are needed. “If you weren’t trying to do learning on it, you could potentially get something that’s much lower power, much faster, much more efficient when taking an already trained neural net and running it for whatever application. That turns out to be important in terms of where we see hardware going,” he said.

The problem with present day technology – whether it’s CPUs, GPUs, ASICs or FPGAs — is that there is still a huge gap between what processing power is required and what’s available now. “We have a 1,000x gap in performance per watt that we have to close,” said Applied Materials’ Dickerson.

There’s a need to reduce the amount of power used in AI processors not only at data centers, but for mobile applications such as automotive and security where decisions need to be made in real time versus in the cloud. This also could lead to a need for different kinds of AI chips.

An interesting case in point: IBM’s world-leading Summit supercomputer, employs 9,216 IBM processors boosted by 27,648 Nvidia GPUs – and takes a room the size of two tennis courts and as much power as a small town!

New approaches

To get to the next level in performance/Watt, innovations being researched at the AI chip level include:

  • low precision computing
  • analog computing
  • resistive computing

In one study, IBM artificially reduced the precision in a neural net and the results were surprising. “We found we could get down the floating point to 14 bit, and we really were getting exactly the same precision as you could with 16 bit or 32 bit or 64 bit,” Welser said. “It didn’t really matter at that point.”

This means that some parts of the neural net could be high precision and some parts that are low precision. “There’s a lot of tradeoffs you can make there, that could get you lower power or higher performance for that power, by giving up precision,” Welser said.

Old-school analog computing has even lower precision but may be well suited to AI. “Analog computing was extremely efficient at the time, it’s just you can’t control the errors or scale it in any way that makes sense if you’re trying to do high precision floating point,” Welser said. “But if what you really want is the ability to have a variable connection, say to neurons, then perhaps you could actually use an analog device.”

Resistive computing is a twist on analog computing that has the added advantage of eliminating the bottleneck between memory and compute. Welser said to think of it as layers of neurons, and the connections between those neurons would be an analog resistive memory. “By changing the level of that resistive memory, the amount of current that flows between one neuron and the next would be varied automatically. The next neuron down would decide how it’s going to fire based on the amount of current that flowed into it.

IBM experimented with phase change memory for this application. “Obviously phase change memory can go to a low resistance or a high resistance (i.e., a 1 or a 0) but there is no reason you can’t take it somewhere in between, and that’s exactly what we would want to take advantage of here,” Welser said.

“There is hope for taking analog devices and using them to actually be some of the elements and getting rid of the bottleneck for the memory as well as getting away from the precision/power that goes on with trying to get to high precision for those connections,” he added.

A successful resistive analog memory ultimately winds up being a materials challenge. “We’d like to have like a thousand levels for the storage capacity, and we’d like to have a very nice symmetry in turning it off and on, which is not something you’d normally think about,” Welser said. “One of the challenges for the industry is to think about how you can get materials that fit these needs better than just a straight memory of one bit on or off.”

Sundeep Bajikar, head of market intelligence at Applied Materials, writing in a blog, said “addressing the processor-to-memory access and bandwidth bottleneck will give rise to new memory architectures for AI, and could ultimately lead to convergence between logic and memory manufacturing process technologies. IBM’s TrueNorth inference chip is one such example of a new architecture in which each neuron has access to its own local memory and does not need to go off-chip to access memory. New memory devices such as ReRAM, FE-RAM and MRAM could catalyze innovation in the area of memory-centric computing. The traditional approach of separating process technologies for high-performance logic and high-performance memory may no longer be as relevant in a new AI world of reduced precision computing.”

Logic Densities Advance at IEDM 2017

Monday, December 18th, 2017

By Dave Lammers

The 63rd International Electron Devices Meeting brought an optimistic slant to transistor density scaling. While some critics have declared the death of Moore’s Law, there was little evidence of that — on the density front at least — at the IEDM, held Dec. 2-6 in San Francisco.

And an Intel engineering manager gave a presentation at IEDM that took a somewhat optimistic view of EUV lithography readiness, auguring further patterning improvements, starting with contacts and vias.

GlobalFoundries, which is skipping the 10nm node, presented its 7nm logic technology, expects to move into manufacturing in mid-2018. John Pellerin, vice president of global R&D, said the foundry has worked closely with its two lead customers, AMD and IBM, to define a high-performance-computing 7nm logic technology that achieves a 2.8X improvement of routed logic density compared with its 14nm technology.

Pellerin said the current 7nm process of record (POR) delivers “the right mix of performance, power, and area (PPA),” adding that GlobalFoundries plans to bring in EUV patterning at an undefined later point in the 7+ generation for further improvements.

Contact Over Active Gate

Chris Auth, director of advanced transistor development at Intel Corp., described a 10nm logic technology that sharply increased the transistor density compared with the 14nm generation, partly due to a contact-over-active-gate (COAG) architecture. The 10nm ring oscillator performance was improved by 20 percent compared with the comparable 14nm test vehicle.

Chris Auth, who presented Intel’s 10nm technology paper at IEDM, was surrounded by questioners following the presentation.

Auth said the COAG approach was a key contributor to Intel’s ability to increase its transistor density by 2.7 times over the company’s previous generation, to 100 million transistors per square millimeter of silicon. While the traditional approach puts the contact via over the isolation area, COAG places the contact via directly over the gate. Auth said the approach does require a second etch stop layer and other process complexities, but contributes “a sizable 10 percent reduction in area.” Elimination of the dummy gate for cell boundary isolation, and the use of cobalt at three layers (see related story), also contributed.

While there has been much hand wringing in the industry over the costs involved with multi-level patterning, Auth didn’t appear phased by it. Intel used a self-aligned quad patterning (SAQP) scheme to create fins with a tight pitch. The SAQP approach required two sacrificial layers, with lithography defining the first large pattern and four additional steps to remove the spacers and create the final lines and spaces.

The Intel 10nm fins are 46nm in height.

The SAQP approach starts by exposing a 130nm line, depositing the two spacers, halving the pattern to 68nm, and again to 34nm. “It is a grating and cut process similar to what we showed at 22nm, except it is SAQP instead of SADP,” using patterning to form a grating of fins, and cutting the ends of the fins with a cut mask.

“There were no additional lithography steps required. The result was fins that are tighter, straighter, and taller, with better drive current and matching” than Intel’s 14nm-generation fins, he said. Intel continued to use self-aligned double patterning (SADP) for M 2-5, and for gate patterning.

GlobalFoundries — which has been in production for 18 months with the 14nm process used by AMD, IBM, and others — plans to ramp its 7nm logic generation starting in mid-2018. The 7nm high-density SRAM cell measures .0269 um2, slightly smaller than TSMC’s published 7nm cell, while Intel reported a .0312 um2 cell size for its 10nm process.

Intel argues that the traditional way of calculating density improvements needs to be replaced with a metric that combines NAND and scan flip-flop densities. (Source: Intel)

GlobalFoundries chief technology officer Gary Patton said, “all of us are in the same zip code” when it comes to SRAM density. What is increasingly important is how the standard cells are designed to minimize the track height and thereby deliver the best logic cell technology to designers, Patton said.

EUV Availability Needs Improvements

Britt Turkot, senior principal engineer at Intel, discussed the readiness of EUV lithography at an IEDM session, giving a cautiously bullish report. With any multi-patterning solution for leading-edge silicon, including etch and CMP steps, placement error is the biggest challenge. With quad patterning, Turkot said multiple masks are involved, creating “compounded alignment errors.”

EUV has its own challenges, including significant secondary ions from the EUV photons. The key challenge for much of the decade, source power, seems to be partially resolved. “We are confident that the 250 Watts of source power needed for volume manufacturing will be ready once the field tools are upgraded,” she said.

Pellicles may be another challenge, with ASML expected to have a polysilicon-based pellicle ready in time for EUV production. However, she said a polysilicon membrane “does give quite a hit to the transmissivity” of the mask. “The transmissivity impact is quite significant,” she acknowledged during the Q&A period following her talk.

Intel has succeeded in repairing some mask defects, Turkot said, and implements pattern shifting so that other defects do not impinge on the patterned wafer.

Asked by a member of the audience about EUV availability or up-time, Turkot said “one day, availability can be great,” and less than good on other days, with “long unscheduled downs.” Intel is predicting 88 percent availability next year, she said in response to a question.

Pellicle Needed for Wiring Layers

Scotten Jones, president of semiconductor cost consultancy IC Knowledge (Boston), said companies may be able to get by without a pellicle for EUV patterning of contacts and via layers late next year. However, a pellicle will be needed for patterning the lower-level wiring layers, absorbing 10-15 percent of the photons and impacting EUV patterning throughput accordingly.

“Companies can do the contacts and vias without a pellicle, but doing the metal layers will required a pellicle and that means that a ton of work still needs to be done. And then at 5nm, the dose you need for the resist goes up dramatically,” Jones said, adding that while it will take some time for ASML to roll out the 250 W source, “they should be able to do it.”

GlobalFoundries will take possession of its second EUV scanner in December 2017, while Intel is believed to own four EUV systems.

Pellerin said GlobalFoundries defined the ground rules for its 7nm process so that the foundry can do a phased implementation of EUV without causing its customers “design discontinuity, bringing a benefit to design costs.”

John Pellerin, v.p. of R&D, said GlobalFoundries plans a phased implementation of EUV without “design discontinuity.”

The foundry will first do the hole levels and then move into the tight-pitch metal levels as mask defectivity improves. “The mask ecosystem needs to evolve,” Pellerin said.

Cost-per-Function on Track

In a keynote speech at IEDM, Lisa Su, the CEO of Advanced Micro Devices, said over the last 10 years the semiconductor industry has succeeded in doubling transistor density every 2-2.4 years. But she said the performance gains have been much smaller. “We are making progress, but it is taking a tremendous amount of work,” said Su, who received a best paper award at the IEDM 25 years earlier.

About 40 percent of the CPU performance improvement now comes from pure process technology, Su said, while the remainder comes from better microarchitectures, power management, and integration of system components such as an on-chip memory controller. While instructions per cycle are increasing at a 7 percent annual clip, Su said “the tricks have run out.”

Overall, the leading semiconductor companies seem to continue to make progress on transistor density. And costs per transistor may also be on track. Kaizad Mistry, co-director of logic technology development at Intel, contends that with its Intel’s 10nm process Intel’s per-transistor costs are actually better than the historical  curve.

Jones said the IC Knowledge cost analysis of TSMC’s processes indicates TSMC also is hewing to historical improvements on the per-transistor cost front. However, the foundries are catching up to Intel.

Intel Cadence Lagging

“What really strikes me is that Intel brought out its 45nm process in 2007, 32nm in 2009, and 22nm in 2011, but then it took three years to do 14nm. We are about to be in the year 2018, and Intel still doesn’t have its 10nm process done. It is a very nice process, but it is not out yet, and TSMC’s 7nm process is ramping right now. By the time Intel gets to 7nm, the foundries may be at 3nm. GlobalFoundries skipped a generation but is ramping its 7nm next year. All will have processes competitive to Intel at the same time, or even earlier,” Jones said.

While foundries such as GlobalFoundries, Samsung, and TSMC may be able to quickly offer advanced logic platforms, the wider semiconductor industry faces design cost challenges, Jones said. “Yes, the cost-per-transistor is going down, and that’s nice, but the cost of a design with finFETs is in the 100-million-dollar range. Intel can do it, but many smaller companies can’t afford to design with FinFETs.”

That is why both GlobalFoundries and Samsung are offering FD-SOI based platforms that use planar transistors, reducing design costs.

“The Internet of Things market is going to be nine million things, at relatively low volumes. IoT companies are finding it hard to justify the cost of a FinFET design, but with the cheaper design costs, SOI gives them an economical path,” Jones said.

Deep Learning Joins Process Control Arsenal

Friday, December 8th, 2017

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By David Lammers

At the 2017 Advanced Process Control (APC 2017) conference, several companies presented implementations of deep learning to find transistor defects, align lithography steps, and apply predictive maintenance.

The application of neural networks to semiconductor manufacturing was a much-discussed trend at the 2017 APC meeting in Austin, starting out with a keynote speech by Howard Witham, Texas operations manager for Qorvo Inc. Witham said artificial intelligence has brought human beings to “a point in history, for our industry and the world in general, that is more revolutionary than a small, evolutionary step.”

People in the semiconductor industry “need to take what’s out there and figure out how to apply it to your own problems, to figure out where does the machine win, and where does the brain still win?” Witham said.

At Seagate Technology, a small team of engineers stitched together largely packaged or open source software running on a conventional CPU to create a convolution neural network (CNN)-based tool to find low-level device defects.

In an APC paper entitled Automated Wafer Image Review using Deep Learning, Sharath Kumar Dhamodaran, an engineer/data scientist based at Seagate’s Bloomington, Minn. facility, said wafers go through several conventional visual inspection steps to identify and classify defects coming from the core manufacturing process. The low-level defects can be identified by the human eye but are prone to misclassification due to the manual nature of the inspections.

Each node in a convolutional layer takes a linear combination of the inputs from nodes in the previous layer, and then applies a nonlinearity to generate an output and pass it to nodes in the next layer. Source: Seagate

“Some special types of low-level defects can occur anywhere in the device. While we do have visual inspections, mis-classifications are very common. By using deep learning, we can solve this issue, achieve higher levels of confidence, and lower mis-classification rates,” he said.

CNNs, Hadoop, and Apache

The deep learning system worked well but required a fairly extensive training cycle, based on a continuously evolving set of training images. The images were replicated from an image server into an Apache HBASE table on a Hadoop cluster. The HBASE table was updated every time images were added to the image server.

To improve the neural network training steps, the team artificially created zoomed-in copies of the same image to enlarge the size of the training set. This image augmentation, which came as part of a software package, was used so that the model did not see the same image twice, he said.

“Our goal was to demonstrate the power of our models, so we did no feature engineering and only minimal pre-processing,” Dhamodaran said.

A Convolution Neural Network (CNN)

Neural networks are trained with many processing layers, which is where the term deep learning comes from. The CNN’s processing layers are sensitive to different features, such as edges, color, and other attributes. This heterogeneity “is exploited to construct sophisticated architectures in which the neurons and layers are connected, and plays a primary role in determining the network’s ability to produce meaningful results,” he said.

The model was trained initially with about 7,000 images over slightly less than six hours on a conventional CPU. “If training the model had been done on a high-performance GPU, it would have taken less than a minute for several thousand images,” Dhamodaran said.

The team used commercially available software, writing code in Python and using Ubuntu, Tensorflow, Keras and other data science packages.

After the deep learning system was put into use, the rate of false negatives on incoming images was excellent. Dhamodaran said the defect classification process was much better than the manual system, with 95 percent of defects correctly classified and the remaining five percent mis-classifications. With the manual system, images were correctly classified only 60 percent of the time.

“None of the conventional machine learning models could do what deep learning could do. But deep learning has its own limitations. Since it is a neural network it is a black box. Process engineers in a manufacturing setting would like to know ‘How does this classification happen?’ That is quite challenging.”

The team created a dashboard so that when an unseen defect occurs the system can incorporate feedback from the operator, feedback which can be incorporated in the next training cycle, or used to create the training set for different processes.

The project involved fewer than six people, and took about six months to put all the pieces together. The team deployed the system on a workstation in the fab, achieving better-than-acceptable decision latency during production.

While Dhamodaran said future implementations of deep learning can be developed in a shorter time, building on what the team learned in the first implementation. He declined to detail the number of features that the initial system dealt with.

Seagate engineer Tri Nguyen, a co-author, said future work involves deploying the deep learning system to more inspection steps. “This system doesn’t do anything but image processing, and the classification is good or bad. But even with blurry images, the system can achieve a high level of confidence. It frees up time and allow operators to do some root cause analysis,” Nguyen said.

Seagate engineers Tri Nguyen and Sharath Kuman Dhamodaran developed a deep learning tool for wafer inspection that sharply reduced mis-classifications.

Python, Keras, TensorFlow

Jim Redman, president of consultancy Ergo Tech (Santa Fe, N.M.), presented deep learning work done with a semiconductor manufacturer to automate lithography alignment. Redman was unabashedly positive about the potential of neural networks for chip manufacturing applications. The movement toward deep learning, he said, “really started” from the date — 9 November 2015 – when the TensorFlow software, developed within the Google Brain group, was released under an Apache 2.0 open source license.

Other tools have further eased the development of deep learning applications, Redman added, including Keras, a high-level neural network API, written in Python and capable of running on top of TensorFlow, for enabling fast experimentation.

In just the last year or so, the application of neural networks in the chip industry has made “huge advances,” Redman said, arguing that deep learning is “a wave that is coming. It is a transformative technology that will have a transformative effect on the semiconductor industry.”

In image processing and analysis, what is difficult to do with conventional techniques often can be handled more easily by neural networks. “The beauty of neural networks is that you can take training sets and teach the model something by feeding in known data. You train the model with data points, and then you feed in unknown data.”

While Redman’s work involved lithography alignment, he said “there is no reason the same learning shouldn’t apply to etch tools or electroplaters. It is the basically the same model.”

Less Code, Lower Costs

Complex FDC modeling can involve Ph.ds with domain expertise, while deep learning can involve models with “30-40 lines of Python code,” he said, noting that the “minimal number of lines of code translates to lower costs.”

Humans, including engineers, are not adapted to look for small details in hundreds or thousands of metrology images or SPC charts. “Humans don’t do that well. Engineers still see what they want to see. We should let computers do that. When it comes to wafer analysis and log files, it is getting too complex (for human analysis). The question now is: Can we leverage these advances in machine learning to solve our problems?”

After training a model to detect distortions for a particular stepper, based on just 35 lines of Python code, Redman said the model provided “an extremely good match between the predicted values and the actual values. We have a model that lines up exactly. It is so good it is almost obscene.”

Redman said similar models could be applied to make sure etchers or electroplating machines were performing to expectations. And he said models can be continuously trained, using incoming flows of data to improve the model itself, rather than thinking of training as distinct from the application of the system.

“Most people talk about the training phase, but in fact we can train continuously. We run data through a model, and we can feed that back into the model, using the new data to continuously train,” he said.

Machine Learning for Predictive Maintenance

Benjamin Menz, of Bosch Rexroth (Lohr am Main, Germany), addressed the challenge of how to apply machine learning to predictive maintenance.

To monitor a machine’s vibration, temperature threshold, power signal, and other signals, companies have developed model-based rules to answer the question: Will it break in the next couple of days? Metz said

“Machine learning can do this in a very automatic way. You don’t need tons of data to train the network, perhaps fifty measurements. A very nice example is a turning machine. The network learned very quickly that the tool is broken, even though the human cannot see it. The new approach is clearly able to see a drop in the health index, and stop production,” he said.

XPoint NVM Array Process Engineering

Wednesday, October 18th, 2017

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By Ed Korczynski, Sr. Technical Editor

Now that TECHINSIGHTS has published a teardown of a 3D XPoint array, we have seen cross-section transmission electron micrographs (TEM) of the device. From first principles of process engineering, we can make educated guesses as to the process flows and challenges in creating this type of non-volatile memory (NVM) integrated circuit (IC). Evolution of device technology over more than fifteen years has resulted in cross-point arrays connecting precise stacks of chalcogenide materials. Intel with “Optane” and Micron with “QuantX” branded ICs can now claim success in commercializing what has always looked good in R&D but was notoriously difficult to make in high-volume manufacturing (HVM).

Figure 1 shows the TEM cross-section, parallel to the wordline direction, of a XPoint memory cell array taken from an Intel Optane product. There are two levels of cross-point cell-stacks, connected in the middle by bitlines (orthogonal to the wordlines). The upper- and lower-wordlines have been analyzed as tungsten (W) metal with tungsten-nitride (WN) barriers. The memory cell material is a variant on a germanium-antimony-teluride (GeSbTe or “GST”) chalcogenide glass, while the selector material is made with arsenic-silicon-germanium-selenide.

Fig. 1: Cross-section TEM of Intel XPoint NVM array in the wordline direction, showing two levels of memory cell stacks separated by bitline arrays. (Source: greyscale image by TechInsights, color commentary by Ed Korczynski)

Details about the device architecture and memory circuitry are included in the Solid State Technology online blog post by TechInsights’ senior technical fellow Dr. Jeongdong Choe, “Comparing XPoint memory architecture with NAND and DRAM products”. In his presentation at the 2017 Flash Memory Summit, Choe disclosed that the composition of the memory material is Ge0.12Sb0.29Te0.54:Si0.05 and the selector material is As0.29Si0.17Ge0.10Se0.44 while there have been no public mentions yet of what materials are used as buffers to electrodes.

As explained in the Ed’s Threads blog post on June 22nd of this year under the title “PCM + ReRAM = OUM as XPoint,” there has been confusion regarding used of Phase-Change Memory (PCM) material in a device that has a completely different architecture, different switching mechanism, and different performance than what are now known as standard PCM ICs. In standard PCM chips, high current-flow through a bit cell heats up a small mass of material until it changes phase (from crystalline to amorphous or vice-versa). In XPoint arrays, a small current-flow through a bit cell causes ions and atoms to re-arrange following voltage potentials until it changes resistivity, while it is not yet public knowledge how much change happens in material phase. Intel has said that the resistance change is not due to conductive “filament” formation in the GeSbTe:Si but due to some change in the “bulk” of the material.

Processing Speculations

From a HVM perspective, all cross-bar memory architectures share similar constraints and opportunities to design for relatively low-cost and high-yield:

1)     Use PVD blanket layers of complex material stacks as memory and selector and buffers,

2)     Use lithography to mask memory cells in a regular two-dimensional array,

3)     Use ion-beam or chemically-neutral plasma to etch pillars of complex material stacks,

4)     Use ALD/CVD and spin-on-dielectrics to gap-fill electrical isolation around pillars, and

5)     Use dielectric CMP to prepare for metal deposition.

Physical Vapor Deposition (PVD) or “sputtering” processing is based on sublimating a solid material “target” inside a vacuum chamber, which provides a relatively fast and inexpensive way to coat surfaces. Thickness uniformity is typically excellent wafer-to-wafer, while within-wafer uniformity is controlled by process chamber and target geometries. The major concern with PVD using multi-component targets—such as the four element GeSbTe:Si—is that different elements sublimate at different rates such that targets “age” and experience slight predictable composition changes over time. PVD target aging can be compensated for by cleverly varying the ratio of the different elements through the thickness of the target.

When integrating PCM materials into NVM devices, the ability to use a blanket 2D PVD deposition is an inherent advantage over ALD into nano-scale 3D features:  faster, cheaper, and potentially more repeatable if target aging can be managed. Patterning of the memory cell stack requires excellent control over ion directionality to prevent sidewall erosion within the material stack. As can be seen in Figure 1, the sidewalls of the GST:Si are slightly recessed from the thin dark layers directly above and below, indicating a well-controlled process with relatively higher removal rate during etching/milling.

Dielectric gap-fill into what appears to be ~10:1 aspect-ratio features is certainly one of the integration challenges of this process flow. The cross-section shows at least one conformal barrier layer is used in the dielectric isolation between array elements and between bitlines. Dielectric ALD is likely used for barrier formation, while spin-on dielectric (SOD) technology likely provides the gap-filling capability. If the metal interconnects for the CMOS circuitry below the array are built using copper, then a 400°C upper limit on process temperatures would be required for all array fabrication.

Future R&D

Milind Weling, expert in materials/device innovation and senior vice president of programs and operations for Intermolecular, presented at the 2017 Flash Memory Summit on the company’s ability to accelerate the pace of R&D experimentation for the complex materials stacks needed in XPoint memory arrays. In an exclusive interview with SemiMD, Weling discussed the inherent challenges of finding the ideal material within a multi-element compositional space.

“We’ve been working on selectors, and a single-element material is almost useless. What you need is at least a binary, maybe a quaternary, and some people experiment with targets composed of up to seven elements! Once we find a composition that is interesting in our R&D tool, our customers create large targets for their HVM tools.” Figure 2 shows a wafer with 28 isolated circular regions within which different PVD compositions can be independent controlled in a custom R&D tool made by Intermolecular. This tool allows a complete design-of-experiments within a ternary compositional space to be run on a single 300mm-diameter silicon wafer.

Fig. 2: Site-isolated circular regions on a 300-mm silicon wafer A) can each have a different composition within B) a ternary phase diagram when deposited in a special PVD R&D tool. Chalcogenide alloys explored as memory and selector materials in cross-bar NVM arrays may have more than three elements. (Source: Intermolecular)

The materials stack is necessarily complex to be able to form chalcogenide-based NVM cells, and even more complex when buffers are added to allow for integration with CMOS-compatible materials. “Each memory cell is two electrodes sandwiching a GST-type of material, and the selector is two electrodes with one ‘magic’ layer,” explained Weling. “Except for the novel ‘magic’ selector, most of the other materials used in the stack have precedent as unit-process steps in HVM of DRAM or NAND. The difficulty is in tuning the compositions of all layers simultaneously.”

—E.K.

[DISCLOSURE:  Ed Korczynski has no ongoing business relationship with nor owns any equity in Intermolecular.]

EUVL Materials Readiness for HVM

Friday, June 2nd, 2017

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By Ed Korczynski, Sr. Technology Editor

Extreme-Ultra-Violet Lithography (EUVL)—based on ~13.5nm wavelength EM waves bouncing off mirrors in a vacuum—will finally be used in commercial IC fabrication by Intel, Samsung, and TSMC starting in 2018. In a recent quarterly earning calls ASML reported a backlog of orders for 21 EUVL tools. At the 2017 SPIE Advanced Lithography conference, presentations detailed how the source and mask and resist all are near targets for next year, while the mask pellicle still needs work. Actinic metrology for mask inspection still remains a known expensive issue to solve.

Figure 1 shows minimal pitch line/space grids and contact-hole arrays patterned with EUVL at global R&D hub IMEC in Belgium, as presented at the recent 2017 IMEC Technology Forum. While there is no way with photolithography to escape the trade-offs of the Resolution/Line-Width-Roughness/Sensitivity (RLS) triangle, patterning at the leading edge of possible pitches requires application-specific etch integration. The bottom row of SEMs in this figure all show dramatic improvements in LWR through atomic-scale etch and deposition treatments to patterned sidewalls.

Fig.1: SEM plan-view images of minimum pitch Resolution and Line-Width-Roughness and Sensitivity (RLS) for both Chemically-Amplified Resist (CAR) and Non-Chemically-Amplified Resist (NCAR, meaning metal-oxide solution from Inpria) formulations, showing that excessive LWR can be smoothed by various post-lithography deposition/etch treatments. (Source: IMEC)

ASML has recently claimed that as an indication of continued maturity, ASML’s NXE:33×0 steppers have now collectively surpassed one million processed wafers to date, and only correctly exposed wafers were included in the count. During the company’s 1Q17 earnings call, it was reported that three additional orders for NXE:3400B steppers were received in Q1 adding  to a total of 21 in backlog, worth nearly US$2.5B.

At $117M each NXE:3400B, assuming 10 years useful life it costs $32,000 each day and assuming 18 productive hours/day and 80 wafers/hour then it costs $22 per wafer-pass just for tool depreciation. In comparison, a $40M argon-fluoride immersion (ArFi) stepper over ten years with 21 available hours/day and 240 wafers/hour costs $2.2 per wafer-pass for depreciation. EUVL will always be an expensive high-value-add technology, even though a single EUVL exposure can replace 4-5 ArFi exposures.

Fabs that delay use of EUVL at the leading edge of device scaling will instead have to buy and facilitize many more ArFi tools, demanding more fab space and more optical lithography gases. SemiMD spoke with Paul Stockman, Linde Electronics’ Head of Market Development, about the global supply of specialty neon and xenon gas blends:  “Xenon is only a ppm level component of the neon-blend for Kr and Ar lasers, so there should be no concerns with Xenon supply for the industry. In our modeling we’ve realized the impact of multi-patterning on gas demand, and we’ve assumed that the industry would need multi-patterning in our forecasts.” said Stockman.

“From the Linde perspective, we manage supply carefully to meet anticipated customer demand,” reminded Stockman. “We recently added 40 million liters of neon capacity in the US, and continue to add significant supply with partners so that we can serve our customers regardless of the EUV scenario.” (Editor’s note: reported by SemiMD here.)

At SPIE Advanced Lithography 2017, SemiMD discussed multi-patterning process flows with Uday Mitra and Regina Freed of Applied Materials. “We need a lot of materials engineering now,” explained Freed. “We need new gap-fills and hard-masks, and we may need new materials for selective deposition. Regarding the etch, we need extreme selectivity with no damage, and ability to get into the smallest features to take out just one atomic layer at a time.”

Reminding us that IC fabs must be risk-averse when considering technology options, Mitra (formerly with Intel) commented, “You don’t do a technology change and a wafer size change at the same time. That’s how you risk manage, and you can imagine with something like EUVL that customers will first use it for limited patterning and check it out.”

Figure 2 lists the major issues in pattern-transfer using plasma etch tools, along with the process variables that must be controlled to ensure proper pattern fidelity. Applied Materials’ Sym3 etch chamber features hardware that provides pulsed energy at dual frequencies along with low residence time of reactant byproducts to allow for precise tuning of process parameters no matter what chemistry is needed.

Fig.2: Patterning issues and associated etch process variables which can be used for control thereof. (Source: Applied Materials)

Andrew Grenville, CEO of resist supplier Inpria, in an exclusive interview with SemiMD, commented on the infrastructure readiness for EUVL volume production. “We are building up our pilot line facility in Corvallis, Oregon. The timing for that is next year, and we are putting in place plans to continue to scale up the new materials at the same times as the quality control systems such as functional QC.” The end-users ask for quality control checks of more parameters, putting a burden on suppliers to invest in more metrology tools and even develop new measurement techniques. Inpria’s resist is based on SnOx nanoparticles, which provide for excellent etch resistance even with layers as thin as 20nm, but required the development of a new technique to measure ppb levels of trace metals in the presence of high tin signals.

“We believe that there is continued opportunity for improvement in the overall patterning performance based on the ancillaries, particularly in simplifying the under-layers. One of the core principles of our material is that we’re putting the ‘resist’ back in the resist,” enthused Grenville. “We can show the etch contrast of our material can really improve the Line-Width Roughness of the patterns because of what you can do in etch, and it’s not merely smoothing the resist. We can substantially improve the outcome by engineering the stack and the etch recipe using completely different chemistry than could be used with chemically-amplified resist.”

The 2017 EUVL Workshop (2017 International Workshop on EUV Lithography) will be held June 12-15 at The Center for X-ray Optics (CXRO) at Lawrence Berkeley National Laboratory in Berkeley, CA. This workshop, now in its tenth year, is focused on the fundamental science of EUV Lithography (EUVL). Travel and hotel information as well as on-line registration is available at https://euvlitho.com/.

[DISCLOSURE:  Ed Korczynski is also Sr. Analyst for TECHCET responsible for the Critical Materials Report (CMR) on Photoresists, Extensions & Ancillaries.]

—E.K.

Mechanistic Modeling of Silicon ALE for FinFETs

Tuesday, April 25th, 2017

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With billions of device features on the most advanced silicon CMOS ICs, the industry needs to be able to precisely etch atomic-scale features without over-etching. Atomic layer etching (ALE), can ideally remove uniform layers of material with consistent thickness in each cycle, and can improve uniformity, reduce damage, increase selectivity, and minimize aspect ratio dependent etching (ARDE) rates. Researchers Chad Huard et al. from the University of Michigan and Lam Research recently published “Atomic layer etching of 3D structures in silicon: Self-limiting and nonideal reactions” in the latest issue of the Journal of Vacuum Science & Technology A (http://dx.doi.org/10.1116/1.4979661). Proper control of sub-cycle pulse times is the key to preventing gas mixing that can degrade the fidelity of ALE.

The authors modeled non-idealities in the ALE of silicon using Ar/Cl2 plasmas:  passivation using Ar/Cl2 plasma resulting in a single layer of SiClx, followed by Ar-ion bombardment to remove the single passivated layer. Un-surprisingly, they found that ideal ALE requires self-limited processes during both steps. Decoupling passivation and etching allows for several advantages over continuous etching, including more ideal etch profiles, high selectivity, and low plasma-induced damage. Any continuous etching —when either or both process steps are not fully self-limited— can cause ARDE and surface roughness.

The gate etch in a finFET process requires that 3D corners be accurately resolved to maintain a uniform gate length along the height of the fin. In so doing, the roughness of the etch surface and the exact etch depth per cycle (EPC) are not as critical as the ability of ALE to be resistant to ARDE. The Figure shows that the geometry modeled was a periodic array of vertical crystalline silicon fins, each 10nm wide and 42nm high, set at a pitch of 42 nm. For continuous etching (a-c), simulations used a 70/30 mix of Ar/Cl gas and RF bias of 30V. Just before the etch-front touches the underlying SiO2 (a), the profile has tapered away from the trench sidewalls and the etch-front shows some micro-trenching produced by ions (or hot neutrals) specularly reflected from the tapered sidewalls. After a 25% over-etch (b), a significant amount of Si remains in the corners and on the sides of the fins. Even after an over-etch of 100% (c), Si still remains in the corners.

FIGURE CAPTION: Simulated profiles resulting from etching finFET gates with (a)–(c) a continuous etching process, or (d)–(f) an optimized ALE process. Time increases from left to right, and images represent equal over-etch (as a percentage of the time required to expose the bottom SiO2) not equal etch times. Times listed for the ALE process in (d)–(f) represent plasma-on, ignoring any purge or dwell times. (Source: J. Vac. Sci. Technol. A, Vol. 35, No. 3, May/Jun 2017)

In comparison, the ALE process (d-f) shows that after 25% over-etch (e) the bottom SiO2 surface would be almost completely cleared with minimal corner residues, and continuing to 100% over-etch results in little change to the profile. The ALE process times shown here do not include the gas purge and fill times between plasma pulses; to clear the feature using ALE required 200 pulses and assuming 5 seconds of purge time between each pulse results in a total process time of 15–20 min to clear the feature. This is a significant increase in total process time over the continuous etch (2 min).

One conclusion of this ALE modeling is that even small deviations from perfectly self-limited reactions significantly compromise the ideality of the ALE process. For example, having as little as 10 ppm Cl2 residual gas in the chamber during the ion bombardment phase produced non-idealities in the ALE. Introducing any source of continuous chemical etching into the ALE process leads to the onset of ARDE and roughening of the etch front. These trends have significant implications for both the design of specialized ALE chambers, and also for the use of ALE to control uniformity.

—E.K.

Lithographic Stochastic Limits on Resolution

Monday, April 3rd, 2017

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By Ed Korczynski, Sr. Technical Editor

The physical and economic limits of Moore’s Law are being approached as the commercial IC fab industry continues reducing device features to the atomic-scale. Early signs of such limits are seen when attempting to pattern the smallest possible features using lithography. Stochastic variation in the composition of the photoresist as well as in the number of incident photons combine to destroy determinism for the smallest devices in R&D. The most advanced Extreme Ultra-Violet (EUV) exposure tools from ASML cannot avoid this problem without reducing throughputs, and thereby increasing the cost of manufacturing.

Since the beginning of IC manufacturing over 50 years ago, chip production has been based on deterministic control of fabrication (fab) processes. Variations within process parameters could be controlled with statistics to ensure that all transistors on a chip performed nearly identically. Design rules could be set based on assumed in-fab distributions of CD and misalignment between layers to determine the final performance of transistors.

As the IC fab industry has evolved from micron-scale to nanometer-scale device production, the control of lithographic patterning has evolved to be able to bend-light at 193nm wavelength using Off-Axis Illumination (OAI) of Optical-Proximity Correction (OPC) mask features as part of Reticle Enhancement Technology (RET) to be able to print <40nm half-pitch (HP) line arrays with good definition. The most advanced masks and 193nm-immersion (193i) steppers today are able to focus more photons into each cubic-nanometer of photoresist to improve the contrast between exposed and non-exposed regions in the areal image. To avoid escalating cost and complexity of multi-patterning with 193i, the industry needs Extreme Ultra-Violet Lithography (EUVL) technology.

Figure 1 shows Dr. Britt Turkot, who has been leading Intel’s integration of EUVL since 1996, reassuring a standing-room-only crowd during a 2017 SPIE Advanced Lithography (http://spie.org/conferences-and-exhibitions/advanced-lithography) keynote address that the availability for manufacturing of EUVL steppers has been steadily improving. The new tools are close to 80% available for manufacturing, but they may need to process fewer wafers per hour to ensure high yielding final chips.

Figure 1. Britt Turkot (Intel Corp.) gave a keynote presentation on "EUVL Readiness for High-Volume Manufacturing” during the 2017 SPIE Advanced Lithography conference. (Source: SPIE)

The KLA-Tencor Lithography Users Forum was held in San Jose on February 26 before the start of SPIE-AL; there, Turcot also provided a keynote address that mentioned the inherent stochastic issues associated with patterning 7nm-node device features. We must ensure zero defects within the 10 billion contacts needed in the most advanced ICs. Given 10 billion contacts it is statistically certain that some will be subject to 7-sigma fluctuations, and this leads to problems in controlling the limited number of EUV photons reaching the target area of a resist feature. The volume of resist material available to absorb EUV in a given area is reduced by the need to avoid pattern-collapse when aspect-ratios increase over 2:1; so 15nm half-pitch lines will generally be limited to just 30nm thick resist. “The current state of materials will not gate EUV,” said Turkot, “but we need better stochastics and control of shot-noise so that photoresist will not be a long-term limiter.”

TABLE:  EUVL stochastics due to scaled contact hole size. (Source: Intel Corp.)

CONTACT HOLE DIAMETER 24nm 16nm
INCIDENT EUV PHOTONS 4610 2050
# ABSORBED IN AREAL IMAGE 700 215

From the LithoGuru blog of gentleman scientist Chris Mack (http://www.lithoguru.com/scientist/essays/Tennants_Law.html):

One reason why smaller pixels are harder to control is the stochastic effects of exposure:  as you decrease the number of electrons (or photons) per pixel, the statistical uncertainty in the number of electrons or photons actually used goes up. The uncertainty produces line-width errors, most readily observed as line-width roughness (LWR). To combat the growing uncertainty in smaller pixels, a higher dose is required.

We define a “stochastic” or random process as a collection of random variables (https://en.wikipedia.org/wiki/Stochastic_process), and a Wiener process (https://en.wikipedia.org/wiki/Wiener_process) as a continuous-time stochastic process in honor of Norbert Wiener. Brownian motion and the thermally-driven diffusion of molecules exhibit such “random-walk” behavior. Stochastic phenomena in lithography include the following:

  • Photon count,
  • Photo-acid generator positions,
  • Photon absorption,
  • Photo-acid generation,
  • Polymer position and chain length,
  • Diffusion during post-exposure bake,
  • Dissolution/neutralization, and
  • Etching hard-mask.

Figure 2 shows the stochastics within EUVL start with direct photolysis and include ionization and scattering within a given discrete photoresist volume, as reported by Solid State Technology in 2010.

Figure 2. Discrete acid generation in an EUV resist is based on photolysis as well as ionization and electron scattering; stochastic variations of each must be considered in minimally scaled areal images. (Source: Solid State Technology)

Resist R&D

During SPIE-AL this year, ASML provided an overview of the state of the craft in EUV resist R&D. There has been steady resolution improvement over 10 years with Photo-sensitive Chemically-Amplified Resists (PCAR) from 45nm to 13nm HP; however, 13nm HP needed 58 mJ/cm2, and provided DoF of 99nm with 4.4nm LWR. The recent non-PCAR Metal-Oxide Resist (MOR) from Inpria has been shown to resolve 12nm HP with  4.7 LWR using 38 mJ/cm2, and increasing exposure to 70 mJ/cm2 has produced 10nm HP L/S patterns.

In the EUVL tool with variable pupil control, reducing the pupil fill increases the contrast such that 20nm diameter contact holes with 3nm Local Critical-Dimension Uniformity (LCDU) can be done. The challenge is to get LCDU to <2nm to meet the specification for future chips. ASML’s announced next-generation N.A. >0.5 EUVL stepper will use anamorphic mirrors and masks which will double the illumination intensity per cm2 compared to today’s 0.33 N.A. tools. This will inherently improve the stochastics, when eventually ready after 2020.

The newest generation EUVL steppers use a membrane between the wafer and the optics so that any resist out-gassing cannot contaminate the mirrors, and this allow a much wider range of materials to be used as resists. Regarding MOR, there are 3.5 times more absorbed photons and 8 times more electrons generated per photon compared to PCAR. Metal hard-masks (HM) and other under-layers create reflections that have a significant effect on the LWR, requiring tuning of the materials in resist stacks.

Default R&D hub of the world imec has been testing EUV resists from five different suppliers, targeting 20 mJ/cm2 sensitivity with 30nm thickness for PCAR and 18nm thickness for MOR. All suppliers were able to deliver the requested resolution of 16nm HP line/space (L/S) patterns, yet all resists showed LWR >5nm. In another experiment, the dose to size for imec’s “7nm-node” metal-2 (M2) vias with nominal pitch of 53nm was ~60mJ/cm2. All else equal, three times slower lithography costs three times as much per wafer pass.

—E.K.

Deep Learning Could Boost Yields, Increase Revenues

Thursday, March 23rd, 2017

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By Dave Lammers, Contributing Editor

While it is still early days for deep-learning techniques, the semiconductor industry may benefit from the advances in neural networks, according to analysts and industry executives.

First, the design and manufacturing of advanced ICs can become more efficient by deploying neural networks trained to analyze data, though labelling and classifying that data remains a major challenge. Also, demand will be spurred by the inference engines used in smartphones, autos, drones, robots and other systems, while the processors needed to train neural networks will re-energize demand for high-performance systems.

Abel Brown, senior systems architect at Nvidia, said until the 2010-2012 time frame, neural networks “didn’t have enough data.” Then, a “big bang” occurred when computing power multiplied and very large labelled data sets grew at Amazon, Google, and elsewhere. The trifecta was complete with advances in neural network techniques for image, video, and real-time voice recognition, among others.

During the training process, Brown noted, neural networks “figure out the important parts of the data” and then “converge to a set of significant features and parameters.”

Chris Rowen, who recently started Cognite Ventures to advise deep-learning startups, said he is “becoming aware of a lot more interest from the EDA industry” in deep learning techniques, adding that “problems in manufacturing also are very suitable” to the approach.

Chris Rowen, Cognite Ventures

For the semiconductor industry, Rowen said, deep-learning techniques are akin to “a shiny new hammer” that companies are still trying to figure out how to put to good use. But since yield questions are so important, and the causes of defects are often so hard to pinpoint, deep learning is an attractive approach to semiconductor companies.

“When you have masses of data, and you know what the outcome is but have no clear idea of what the causality is, (deep learning) can bring a complex model of causality that is very hard to do with manual methods,” said Rowen, an IEEE fellow who earlier was the CEO of Tensilica Inc.

The magic of deep learning, Rowen said, is that the learning process is highly automated and “doesn’t require a fab expert to look at the particular defect patterns.”

“It really is a rather brute force, naïve method. You don’t really know what the constituent patterns are that lead to these particular failures. But if you have enough examples that relate inputs to outputs, to defects or to failures, then you can use deep learning.”

Juan Rey, senior director of engineering at Mentor Graphics, said Mentor engineers have started investigating deep-learning techniques which could improve models of the lithography process steps, a complex issue that Rey said “is an area where deep neural networks and machine learning seem to be able to help.”

Juan Rey, Mentor Graphics

In the lithography process “we need to create an approximate model of what needs to be analyzed. For example, for photolithography specifically, there is the transition between dark and clear areas, where the slope of intensity for that transition zone plays a very clear role in the physics of the problem being solved. The problem tends to be that the design, the exact formulation, cannot be used in every space, and we are limited by the computational resources. We need to rely on a few discrete measurements, perhaps a few tens of thousands, maybe more, but it still is a discrete data set, and we don’t know if that is enough to cover all the cases when we model the full chip,” he said.

“Where we see an opportunity for deep learning is to try to do an interpretation for that problem, given that an exhaustive analysis is impossible. Using these new types of algorithms, we may be able to move from a problem that is continuous to a problem with a discrete data set.”

Mentor seeks to cooperate with academia and with research consortia such as IMEC. “We want to find the right research projects to sponsor between our research teams and academic teams. We hope that we can get better results with these new types of algorithms, and in the longer term with the new hardware that is being developed,” Rey said.

Many companies are developing specialized processors to run machine-learning algorithms, including non-Von Neumann, asynchronous architectures, which could offer several orders of magnitude less power consumption. “We are paying a lot of attention to the research, and would like to use some of these chips to solve some of the problems that the industry has, problems that are not very well served right now,” Rey said.

While power savings can still be gained with synchronous architectures, Rey said brain-inspired projects such as Qualcomm’s Zeroth processor, or the use of memristors being developed at H-P Labs, may be able to deliver significant power savings. “These are all worth paying attention to. It is my feeling that different architectures may be needed to deal with unstructured data. Otherwise, total power consumption is going through the roof. For unstructured data, these types of problem can be dealt with much better with neuromorphic computers.”

The use of deep learning techniques is moving beyond the biggest players, such as Google, Amazon, and the like. Just as various system integrators package the open source modules of the Hadoop data base technology into a more-secure offering, several system integrators are offering workstations packaged with the appropriate deep-learning tools.

Deep learning has evolved to play a role in speech recognition used in Amazon’s Echo. Source: Amazon

Robert Stober, director of systems engineering at Bright Computing, bundles AI software and tools with hardware based on Nvidia or Intel processors. “Our mission statement is to deploy deep learning packages, infrastructure, and clusters, so there is no more digging around for weeks and weeks by your expensive data scientists,” Stober said.

Deep learning is driving new the need for new types of processors as well as high-speed interconnects. Tim Miller, senior vice president at One Stop Systems, said that training the neural networks used in deep learning is an ideal task for GPUs because they can perform parallel calculations, sharply reducing the training time. However, GPUs often are large and require cooling, which most systems are not equipped to handle.

David Kanter, principal consultant at Real World Technologies, said “as I look at what’s driving the industry, it’s about convolutional neural networks, and using general-purpose hardware to do this is not the most efficient thing.”

However, research efforts focused on using new materials or futuristic architectures may over-complicate the situation for data scientists outside of the research arena. At the International Electron Devices Meeting (IEDM 2017), several research managers discussed using spin torque magnetic (STT-MRAM) technology, or resistive RAMs (ReRAM), to create dense, power-efficient networks of artificial neurons.

While those efforts are worthwhile from a research standpoint, Kanter said “when proving a new technology, you want to minimize the situation, and if you change the software architecture of neural networks, that is asking a lot of programmers, to adopt a different programming method.”

While Nvidia, Intel, and others battle it out at the high end for the processors used in training the neural network, the inference engines which use the results of that training must be less expensive and consume far less power.

Kanter said “today, most inference processing is done on general-purpose CPUs. It does not require a GPU. Most people I know at Google do not use a GPU. Since the (inference processing) workload load looks like the processing of DSP algorithms, it can be done with special-purpose cores from Tensilica (now part of Cadence) or ARC (now part of Synopsys). That is way better than any GPU,” Kanter said.

Rowen was asked if the end-node inference engine will blossom into large volumes. “I would emphatically say, yes, powerful inference engines will be widely deployed” in markets such as imaging, voice processing, language recognition, and modeling.

“There will be some opportunity for stand-alone inference engines, but most IEs will be part of a larger system. Inference doesn’t necessarily need hundreds of square millimeters of silicon. But it will be a major sub-system, widely deployed in a range of SoC platforms,” Rowen said.

Kanter noted that Nvidia has a powerful inference engine processor that has gained traction in the early self-driving cars, and Google has developed an ASIC to process its Tensor deep learning software language.

In many other markets, what is needed are very low power consumption IEs that can be used in security cameras, voice processors, drones, and many other markets. Nvidia CEO Jen Hsung Huang, in a blog post early this year, said that deep learning will spur demand for billions of devices deployed in drones, portable instruments, intelligent cameras, and autonomous vehicles.

“Someday, billions of intelligent devices will take advantage of deep learning to perform seemingly intelligent tasks,” Huang wrote. He envisions a future in which drones will autonomously find an item in a warehouse, for example, while portable medical instruments will use artificial intelligence to diagnose blood samples on-site.

In the long run, that “billions” vision may be correct, Kanter said, adding that the Nvidia CEO, an adept promoter as well as an astute company leader, may be wearing his salesman hat a bit.

“Ten years from now, inference processing will be widespread, and many SoCs will have an inference accelerator on board,” Kanter said.

Edge Placement Error Control in Multi-Patterning

Thursday, March 2nd, 2017

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By Ed Korczynski, Sr. Technical Editor

SPIE Advanced Lithography remains the technical conference where the leading edge of minimum resolution patterning is explored, even though photolithography is now only part of the story. Leading OEMs continue to impress the industry with more productive ArFi steppers, but the photoresist suppliers and the purveyors of vacuum deposition and etch tools now provide most of the new value-add. Tri-layer-resist (TLR) stacks, specialty hard-masks and anti-reflective coatings (ARC), and complex thin-film depositions and etches all combine to create application-specific lithography solutions tuned to each critical mask.

Multi-patterning using complementary lithography—using argon-fluoride immersion (ArFi) steppers to pattern 1D line arrays plus extreme ultra-violet (EUV) tools to do line cuts—is under development at all leading edge fabs today. Figure 1 shows that edge placement error (EPE) in lines, cut layers, and vias/contacts between two orthogonal patterned layers can result in shorts and opens. Consequently, EPE control is critical for yield within any multi-patterning process flow, including litho-etch-litho-etch (LELE), self-aligned double-patterning (SADP) and self-aligned quadruple-patterning (SAQP).

Fig.1: Plan view schematic of 10nm half-pitch vertical lines overlaid with lower horizontal lines, showing the potential for edge-placement error (EPE). (Source: Y. Borodovsky, SPIE)

Happening the day before the official start of SPIE-AL, Nikon’s LithoVision event featured a talk by Intel Fellow and director of lithography hardware solutions Mark Phillips on the big picture of how the industry may continue to pattern smaller IC device features. Regarding the timing of Intel’s planned use of EUV litho technology, Phillips re-iterated that, “It’s highly desirable for the 7nm node, but we’ll only use it when it’s ready. However, EUVL will remain expensive even at full productivity, so 193i and multi-patterning will continue to be used. In particular we’ll need continued improvement in the 193i tools to meet overlay.”

Yuichi Shibazaki— Nikon Fellow and the main architect of the current generation of Nikon steppers—explained that the current generation of 193i steppers, featuring throughputs of >200 wafers per hour, have already been optimized to the point of diminishing returns. “In order to improve a small amount of performance it requires a lot of expense. So just improving tool performance may not decrease chip costs.” Nikon’s latest productivity offering is a converted alignment station as a stand-alone tool, intended to measure every product wafer before lithography to allow for feed-forward tuning of any stepper; cost and cost-of-ownership may be disclosed after the first beta-site tool reaches a customer by the end of this year.

“The 193 immersion technology continues to make steady progress, but there are not as many new game-changing developments,” confided Michael Lercel, Director of Strategic Marketing for ASML in an exclusive interview with SemiMD. “A major theme of several SPIE papers is on EPE, which traditionally we looked at as dependent upon CD and overlay. Now we’re looking at EPE in patterning more holistically, with need to control the complexity with different error-variables. The more information we can get the more we can control.”

At LithoVision this year, John Sturtevant—SPIE Fellow, and director of RET product development in the Design to Silicon Division at Mentor Graphics—discussed the challenges of controlling variability in multi-layer patterning. “A key challenge is predicting and then mitigating total EPE control,” reminded Sturtevant. “We’ve always paid attention to it, but the budgets that are available today are smaller than ever. Edge-placement is very important ” At the leading edge, there are multiple steps within the basic litho flow that induce proximity/local-neighbor effects which must be accounted for in EDA:  mask making, photoresist exposure, post-exposure bake (PEB), pattern development, and CD-SEM inspection (wherein there is non-zero resist shrinkage).

Due to the inherent physics of EUV lithography, as well as the atomic-scale non-uniformities in the reflective mirrors focusing onto the wafer, EUV exposure tools show significant variation in exposure uniformities. “For any given slit position there can be significant differences between tools. In practice we have used a single model of OPC for all slit locations in all scanners in the fab, and that paradigm may have to change,” said Sturtevant. “It’s possible that because the variation across the scanner is as much as the variation across the slit, it could mean we’ll need scanner-specific cross-slit computational lithography.” More than 3nm variation has been seen across 4 EUVL steppers, and the possible need for tool-specific optical proximity correction (OPC) and source-mask optimization (SMO) would be horrible for managing masks in HVM.

Thin Films Extend Patterning Resolution

Applied Materials has led the industry in thin-film depositions and etches for decades, and the company’s production proven processing platforms are being used more and more to extend the resolution of lithography. For SADP and SAQP MP, there are tunable unit-processes established for sidewall-spacer depositions, and chemical downstream etching chambers for mandrel pull with extreme material selectivity. CVD of dielectric and metallic hard-masks when combined with highly anisotropic plasma etching allows for device-specific and mask-specific pattern transfers that can reduce the line width/edge roughness (LWR/LER) originally present in the photoresist. Figure 2 from the SPIE-AL presentation “Impact of Materials Engineering on Edge Placement Error” by Regina Freed, Ying Zhang, and Uday Mitra of Applied Materials, shows LER reduction from 3.4 to 1.3 nm is possible after etch. The company’s Sym3 chamber features very high gas conductance to prevent etch byproducts from dissociation and re-deposition on resist sidewalls.

Fig.2: 3D schematics (top) and plan view SEM images (bottom) showing that control of plasma parameters can tune the byproducts of etch processes to significantly reduce the line-width roughness (LWR) of minimally scaled lines. (Source: Applied Materials)

TEL’s new SAQP spacer-on-spacer process builds on the work shown last year, using oxide as first spacer and TiO2 as second spacer. Now TEL is exploring silicon as the mandrel, then silicon-nitride as the first spacer, and titanium-oxide as second spacer. This new flow can be tuned so that all-dry etch in a single plasma etch chamber can be used for the final mandrel pull and pattern transfer steps.

Coventor’s 3D modeling software allows companies to do process integration experiments in virtual space, allowing for estimation of yield-losses in pattern transfer due to variations in side-wall profiles and LER. A simulation of 9 SRAM cells with 54 transistors shows that photoresist sidewall taper angle determines both the size and the variability of the final fins. The final capacitance of low-k dielectric in dual-damascene copper metal interconnects can be simulated as a function of the initial photoresist profile in a SAQP flow.

—E.K.

Innovations at 7nm to Keep Moore’s Law Alive

Thursday, January 19th, 2017

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By Dave Lammers, Contributing Editor

Despite fears that Moore’s Law improvements are imperiled, the innovations set to come in at the 7nm node this year and next may disprove the naysayers. EUV lithography is likely to gain a toehold at the 7nm node, competing with multi-patterning and, if all goes well, shortening manufacturing cycles. Cobalt may replace tungsten in an effort to reduce resistance-induced delays at the contacts, a major challenge with finFET transistors, experts said.

While the industry did see a slowdown in Moore’s Law cost reductions when double patterning became necessary several years ago, Scotten Jones, who runs a semiconductor consultancy focused on cost analysis, said Intel and the leading foundries are back on track in terms of node-to-node cost improvements.

Speaking at the recent SEMI Industry Strategy Symposium (ISS), Jones said his cost modeling backs up claims made by Intel, GlobalFoundries, and others that their leading-edge processes deliver on die costs. Cost improvements stalled at TSMC for the16nm node due to multi-patterning, Jones said. “That pause at TSMC fooled a lot of people. The reality now may surprise those people who said Moore’s Law was dead. I don’t believe that, and many technologists don’t believe that either,” he said.

As Intel has adopted a roughly 2.5-year cadence for its more-aggressive node scaling, Jones said “the foundries are now neck and neck with Intel on density.” Intel has reached best-ever yield levels with its finFET-based process nodes, and the foundries also report reaching similar yield levels for their FinFET processes. “It is hard, working up the learning curve, but these companies have shown we can get there,” he said.

IC Knowledge cost models show the chip industry is succeeding in scaling density and costs. (Source: Scotten Jones presentation at 2017 SEMI ISS)

TSMC, spurred by its contract with Apple to supply the main iPhone processors, is expected to be first to ship its 7nm products late this year, though its design rules (contacted poly pitch and minimum metal pitch) are somewhat close to Intel’s 10nm node.

While TSMC and GlobalFoundries are expected to start 7nm production using double and quadruple patterning, they may bring in EUV lithography later. TSMC has said publicly it plans to exercise EUV in parallel with 193i manufacturing for the 7nm node. Samsung has put its stake in the ground to use EUV rather than quadruple patterning in 2018 for critical layers of its 7nm process. Jones, president of IC Knowledge LLC, said Intel will have the most aggressive CPP and MPP pitches for its 7nm technology, and is likely to use EUV in 2019-2020 to push its metal pitches to the minimum possible with EUV scanners.

EUV progress at imec

In an interview at the 62nd International Electron Devices Meeting (IEDM) in San Francisco in early December, An Steegen, the senior vice president of process technology at Imec (Leuven, Belgium), said Imec researchers are using an ASML NXE 3300B scanner with 0.3 NA optics and an 80-Watt power supply to pattern about 50 wafers per hour.

“The stability on the tool, the up time, has improved quite a lot, to 55 percent. In the best weeks we go well above 70 percent. That is where we are at today. The next step is a 125-Watt power supply, which should start rolling out in the field, and then 250 Watts.”

Steegen said progress is being made in metal-containing EUV resists, and in development of pellicles “which can withstand hydrogen in the chamber.”

If those challenges can be met, EUV would enable single patterning for vias and several metal layers in the middle of the line (MOL), using cut masks to print the metal line ends. “For six or seven thin wires and vias, at the full (7nm node) 32nm pitch, you can do it with a single exposure by going to EUV. The capability is there,” Steegen said.

TSMC’s 7nm development manager, S.Y. Wu, speaking at IEDM, said quadruple patterning and etch (4P4E) will be required for critical layers until EUV reaches sufficient maturity. “EUV is under development (at TSMC), and we will use 7nm as the test vehicle.”

Huiming Bu was peppered with questions following a presentation of the IBM Alliance 7nm technology at IEDM.

Huiming Bu, who presented the IBM Alliance 7nm paper at IEDM, said “EUV delivers significant depth of field (DoF) improvement” compared with the self-aligned quadruple (SAQP) required for the metal lines with immersion scanners.

A main advantage for EUV compared with multi-patterning is that designs would spend fewer days in the fabs. Speaking at ISS, Gary Patton, the chief technology officer at GlobalFoundries, said EUV could result in 30-day reductions in fab cycle times, compared with multiple patterning with 193nm immersion scanners, based on 1.5 days of cycle time per mask layer.

Moreover, EUV patterns would produce less variation in electrical performance and enable tighter process parameters, Patton said.

Since designers have become accustomed to using several colors to identify multi-patterning layers for the 14nm node, the use of double and quadruple patterning at the 7nm node would not present extraordinary design challenges. Moving from multi-patterning to EUV will be largely transparent to design teams as foundries move from multi-patterning to EUV for critical layers.

Interconnect resistance challenges

As interconnects scale and become more narrow, signals can slow down as electrons get caught up in the metal grain boundaries. Jones estimates that as much as 85 percent of parasitic capacitance is in the contacts.

For the main interconnects, nearly two decades ago, the industry began a switch from aluminum to copper. Tungsten has been used for the contacts, vias, and other metal lines near the transistor, partly out of concerns that copper atoms would “poison” the nearby transistors.

Tungsten worked well, partly because the bi-level liner – tantalum nitride at the interface with the inter-level dielectric (ILD) and tantalum at the metal lines – was successful at protecting against electromigration. The TaN-Ta liner is needed because the fluorine-based CVD processes can attack the silicon. For tungsten contacts, Ti serves to getter oxygen, and TiN – which has high resistance — serves as an oxygen and fluorine barrier.

However, as contacts and MOL lines shrunk, the thickness of the liner began to equal the tungsten metal thicknesses.

Dan Edelstein, an IBM fellow who led development of IBM’s industry-leading copper interconnect process, said a “pinch point” has developed for FinFETs at the point where contacts meet the middle-of-the-line (MOL) interconnects.

“With cobalt, there is no fluorine in the deposition process. There is a little bit of barrier, which can be either electroplated or deposited by CVD, and which can be polished by CMP. Cobalt is fairly inert; it is a known fab-friendly metal,” Edelstein said, due to its longstanding use as a silicide material.

As the industry evaluated cobalt, Edelstein said researchers have found that cobalt “doesn’t present a risk to the device. People have been dropping it in, and while there are still some bugs that need to be worked out, it is not that hard to do. And it gives a big change in performance,” he said.

Annealing advantages to Cobalt

Contacts are a “pinch point” and the industry may switch to cobalt (Source: Applied Materials)

An Applied Materials senior director, Mike Chudzik, writing on the company’s blog, said the annealing step during contact formation also favors cobalt: “It’s not just the deposition step for the bulk fill involved – there is annealing as well. Co has a higher thermal budget making it possible to anneal, which provides a superior, less granular fill with no seams and thus lowers overall resistance and improves yield,” Chudzik explained.

Increasing the volume of material in the contact and getting more current through is critical at the 7nm node. “Pretty much every chipmaker is working aggressively to alleviate this issue. They understand if it’s not resolved then it won’t matter what else is done with the device to try and boost performance,” Chudzik said.

Prof. Koike strikes again

Innovations underway at a Japanese university aim to provide a liner between the cobalt contact fill material and the adjacent materials. At a Sunday short course preceding the IEDM, Reza Arghavani of Lam Research said that by creating an alloy of cobalt and approximately 10 percent titanium, “magical things happen” at the interfaces for the contact, M0 and M1 layers.

The idea for adding titanium arose from Prof. Junichi Koike at Tohoku University, the materials scientist who earlier developed a manganese-copper solution for improved copper interconnects. For contacts and MOL, the Co-Ti liner prevents diffusion into the spacer oxide, Arghavani said. “There is no (resistance) penalty for the liner, and it is thermally stable, up to 400 to 500 degrees C. It is a very promising material, and we are working on it. W (tungsten) is being pushed as far as it can go, but cobalt is being actively pursued,” he said.

Stressor changes ahead

Presentations at the 2016 IEDM by the IBM Alliance (IBM, GlobalFoundries, and Samsung) described the use of a stress relaxed buffer (SRB) layer to induce stress, but that technique requires solutions for the defects introduced in the silicon layer above it. As a result of that learning process, SRB stress techniques may not come into the industry until the 5 nm node, or a second-generation 7nm node.

Technology analyst Dick James, based in Ottawa, said over the past decade companies have pushed silicon-germanium stressors for the PFET transistors about as far as practical.

“The stress mechanisms have changed since Intel started using SiGe at the 90nm node. Now, companies are a bit mysterious, and nobody is saying what they are doing. They can’t do tensile nitride anymore at the NFET; there is precious little room to put linear stress into the channel,” he said.

The SRB technique, James said, is “viable, but it depends on controlling the defects.” He noted that Samsung researchers presented work on defects at the IEDM in December. “That was clearly a research paper, and adding an SRB in production volumes is different than doing it in an R&D lab.”

James noted that scaling by itself helps maintain stress levels, even as the space for the stressor atoms becomes smaller. “If companies shorten the gate length and keep the same stress as before, the stress per nanometer at least maintains itself.”

Huiming Bu, the IBM researcher, was optimistic, saying that the IBM Alliance work succeeded at adding both compressive and tensile strain. The SRB/SSRW approach used by the IBM Alliance was “able to preserve a majority – 75 percent – of the stress on the substrate.”

Jones, the IC Knowledge analyst, said another area of intense interest in research is high-mobility channels, including the use of SiGe channel materials in the PMOS FinFETS.

He also noted that for the NMOS finFETs, “introducing tensile stress in fins is very challenging, with lots of integration issues.” Jones said using an SRB layer is a promising path, but added: “My point here is: Will it be implemented at 7 nm? My guess is no.”

Putting it in a package

Steegen said innovation is increasingly being done by the system vendors, as they figure out how to combine different ICs in new types of packages that improve overall performance.

System companies, faced with rising costs for leading-edge silicon, are figuring out “how to add functionality, by using packaging, SOC partitioning and then putting them together in the package to deliver the logic, cache, and IOs with the right tradeoffs,” she said.

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