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Posts Tagged ‘SiP’

SiPs Simplify Wireless IoT Design

Thursday, February 16th, 2017

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By Dave Lammers, Contributing Editor

It takes a range of skills to create a successful business in the Internet of Things space, where chips sell for a few dollars and competition is intense. Circuit design and software support for multiple wireless standards must combine with manufacturing capabilities.

Daniel Cooley, senior vice president of IoT products at Silicon Labs

Daniel Cooley, senior vice president and general manager of IoT products at Silicon Labs (Austin, Tx.), said three trends are impacting the manufacture of IoT end-node devices, which usually combine an MCU, an RF transceiver, and embedded flash memory.

“There is an explosion in the amount of memory on embedded SoCs, both RAM and non-volatile memory,” said Cooley. Today’s multi-protocol wireless software stacks, graphics processing, and security requirements routinely double or quadruple the memory sizes of the past.

Secondly, while IoT edge devices continue to use trailing-edge technologies, nonetheless they also are moving to more advanced nodes. However, that movement is partially gated by the availability of embedded flash.

Thirdly, pre-certified system-in-package (SiP) solutions, running a proven software stack, “are becoming much more important,” Cooley said. These SiPs typically encapsulate an MCU, an integrated antenna and shielding, power management, crystal oscillators, and inductors and capacitors. While Silicon Labs has been shipping multi-chip modules for many years, SiPs are gaining favor in part because they can be quickly deployed by engineers with relatively little expertise in wireless development, he said.

“Personally, I believe that very advanced SIPs increasingly will be standard products, not anything exotic. They are a complete solution, like a PCB module, but encased with a molding compound. The SiP manufacturers are becoming very sophisticated, and we are ready to take that technology and apply it more broadly,” he said.

For example, Silicon Labs recently introduced a Bluetooth SiP module measuring 6.5 by 6.5 mm, designed for use in sports and fitness wearables, smartwatches, personal medical devices, wireless sensor nodes, and other space-constrained connected devices.

“We have built multi-chip packages – those go back to the first products of the company – but we haven’t done a fully certified module with a built-in antenna until now. A SiP module simplifies the go-to-market process. Customers can just put it down on a PCB and connect power and ground. Of course, they can attach other chips with the built-in interfaces, but they don’t need anything else to make the Bluetooth system work,” Cooley said.

“Designing with a certified SiP module supports better data throughput, and improves reliability as well. The SiP approach is especially beneficial for end-node customers which “haven’t gone through the process of launching a wireless product in in the market,” Cooley said.

System-in-package (SiP) solutions ease the design cycle for engineers using Bluetooth and low low-energy wireless networks. (Source: Silicon Laboratories).

The SiP packages a wireless SoC with an antenna and multiple other components in a small footprint.

Control by voice

The BGM12x Blue Gecko SiP is aimed at Bluetooth-enabled applications, a genre that is rapidly expanding as ecosystems like the Amazon Echo, Apple HomeKit, and Google Home proliferate.

The BGM12x Blue Gecko SiP is aimed at Bluetooth-enabled applications

Matt Maupin is Silicon Labs’ product marketing manager for mesh networking products, which includes SoCs and modules for low-power Zigbee and Thread wireless connectivity. Asked how a home lighting system, for example, might be connected to one of the home “ecosystems” now being sold by Amazon, Apple, Google, Nest, and others, Maupin said the major lighting suppliers, such as OSRAM, Philips, and others, often use Zigbee for lighting, rather than Bluetooth, because of Zigbee’s mesh networking capability. (Some manufactures use Bluetooth low energy (BLE) for point-to-point control from a phone.)

“The ability for a device to connect directly relies on the same protocols being used. Google and Amazon products do not support Zigbee or Thread connectivity at this time,” Maupin explained.

Normally, these lighting devices are connected to a hub. For example, Amazon’s Echo and Google’s Home “both control the Philips lights through the Philips hub. Communication happens over the Ethernet network (wireless or wired depending on the hub).  The Philips hub also supports HomeKit so that will work as well,” he said.

Maupin’s home configuration is set up so the Philips lights connect via Zigbee to the Philips hub, which connects to an Ethernet network. An Amazon Echo is connected to the Ethernet Network by WiFi.

“I have the Philips devices at home configured via their app. For example, I have lights in my bedroom configured differently for me and my wife. With voice commands, I can control these lamps with different commands such as ‘Alexa, turn off Matt’s lamp,’ or ‘Alexa, turn off the bedroom lamps.’”

Alexa communicates wirelessly to the Ethernet Network, which then goes to the Philips hub (which is sold under the brand name Philips Hue Bridge) via Ethernet, where the Philips hub then converts that to Zigbee to control that actual lamps. While that sounds complicated, Maupin said, “to consumers, it is just magic.”

A divided IoT market

Sandeep Kumar, senior vice president of worldwide operations

IoT systems can be divided into the high-performance number crunchers which deal with massive amounts of data, and the “end-node” products which drive a much different set of requirements. Sandeep Kumar, senior vice president of worldwide operations at Silicon Labs, said RF, ultra-low-power processes and embedded NVM are essential for many end-node applications, and it can take several years for foundries to develop them beyond the base technology becoming available.

“40nm is an old technology node for the big digital companies. For IoT end nodes where we need a cost-effective RF process with ultra-low leakage and embedded NVM, the state of the art is 55nm; 40 nm is just getting ready,” Kumar said.

Embedded flash or any NVM takes as long as it does because, most often, it is developed not by the foundries themselves but by independent companies, such as Silicon Storage Technology. The foundry will implement this IP after the foundry has developed the base process. (SST has been part of Microchip Technology since 2010.) Typically, the eFlash capability lags by a few years for high-volume uses, and Kumar notes that “the 40nm eFlash is still not in high-volume production for end-node devices.”

Similarly, the ultra-low-leakage versions of a technology node take time and equipment investments, as well as cooperation from IP partners. Foundry customers and the fabless design houses must requalify for the low-leakage processes. “All the models change and simulations have to be redone,” Kumar said.

“We need low-leakage for the end applications that run on a button cell (battery), so that a security door or motion sensor, for example, can run for five to seven years. After the base technology is developed, it typically takes at least three years. If 40nm was available several years ago, the ultra-low-leakage process is just becoming available now.

“And some foundries may decide not to do ultra-low-leakage on certain technology nodes. It is a big capital and R&D investment to do ultra-low-leakage. Foundries have to make choices, and we have to manage that,” Kumar said.

The majority of Silicon Labs’ IoT product volume is in 180nm, while other non-IoT products use a 55nm process. The line of Blue Gecko wireless SoCs currently is on 90nm, made in 300mm fabs, while new designs are headed toward more advanced process nodes.

Because 180nm fabs are being used for MEMS, sensors and other analog-intensive, high-volume products, there is still “somewhat of a shortage” of 180nm wafers, Kumar said, though the situation is improving. “It has gotten better because TSMC and other foundries have added capacity, having heard from several customers that the 180nm node is where they are going to stay, or at least stay longer than they expected. While the foundries have added equipment and capital, it is still quite tight. I am sure the big MEMS and sensor companies are perfectly happy with 180nm,” Kumar said.

A testing advantage

IoT is a broad-based market with thousands of customers and a lot of small volume customizations. Over the past decade Silicon Labs has deployed a proprietary ultra-low-cost tester, developed in-house and used in internal back-end operations in Austin and Singapore at assembly and test subcontractors and at a few outside module makers as well. The Silicon Labs tester is much more cost effective than commercially available testers, an important cost advantage in a market where a wireless MCU can sell in small volumes to a large number of customers for just a few dollars.

“Testing adds costs, and it is a critical part of our strategy. We use our internally developed tester for our broad-based products, and it is effective at managing costs,” Kumar said.

Managing Dis-Aggregated Data for SiP Yield Ramp

Monday, August 24th, 2015

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By Ed Korczynski, Sr. Technical Editor

In general, there is an accelerating trend toward System-in-Package (SiP) chip designs including Package-On-Package (POP) and 3D/2.5D-stacks where complex mechanical forces—primarily driven by the many Coefficient of Thermal Expansion (CTE) mismatches within and between chips and packages—influence the electrical properties of ICs. In this era, the industry needs to be able to model and control the mechanical and thermal properties of the combined chip-package, and so we need ways to feed data back and forth between designers, chip fabs, and Out-Sourced Assembly and Test (OSAT) companies. With accelerated yield ramps needed for High Volume Manufacturing (HVM) of consumer mobile products, to minimize risk of expensive Work In Progress (WIP) moving through the supply chain a lot of data needs to feed-forward and feedback.

Calvin Cheung, ASE Group Vice President of Business Development & Engineering, discussed these trends in the “Scaling the Walls of Sub-14nm Manufacturing” keynote panel discussion during the recent SEMICON West 2015. “In the old days it used to take 12-18 months to ramp yield, but the product lifetime for mobile chips today can be only 9 months,” reminded Cheung. “In the old days we used to talk about ramping a few thousand chips, while today working with Qualcomm they want to ramp millions of chips quickly. From an OSAT point of view, we pride ourselves on being a virtual arm of the manufacturers and designers,” said Cheung, “but as technology gets more complex and ‘knowledge-base-centric” we see less release of information from foundries. We used to have larger teams in foundries.” Dick James of ChipWorks details the complexity of the SiP used in the Apple Watch in his recent blog post at SemiMD, and documents the details behind the assumption that ASE is the OSAT.

With single-chip System-on-Chip (SoC) designs the ‘final test’ can be at the wafer-level, but with SiP based on chips from multiple vendors the ‘final test’ now must happen at the package-level, and this changes the Design For Test (DFT) work flows. DRAM in a 3D stack (Figure 1) will have an interconnect test and memory Built-In Self-Test (BIST) applied from BIST resident on the logic die connected to the memory stack using Through-Silicon Vias (TSV).

Fig.1: Schematic cross-sections of different 3D System-in-Package (SiP) design types. (Source: Mentor Graphics)

“The test of dice in a package can mostly be just re-used die-level tests based on hierarchical pattern re-targeting which is used in many very large designs today,” said Ron Press, technical marketing director of Silicon Test Solutions, Mentor Graphics, in discussion with SemiMD. “Additional interconnect tests between die would be added using boundary scans at die inputs and outputs, or an equivalent method. We put together 2.5D and 3D methodologies that are in some of the foundry reference flows. It still isn’t certain if specialized tests will be required to monitor for TSV partial failures.”

“Many fabless semiconductor companies today use solutions like scan test diagnosis to identify product-specific yield problems, and these solutions require a combination of test fail data and design data,” explained Geir Edie, Mentor Graphics’ product marketing manager of Silicon Test Solutions. “Getting data from one part of the fabless organization to another can often be more challenging than what one should expect. So, what’s often needed is a set of ‘best practices’ that covers the entire yield learning flow across organizations.”

“We do need a standard for structuring and transmitting test and operations meta-data in a timely fashion between companies in this relatively new dis-aggregated semiconductor world across Fabless, Foundry, OSAT, and OEM,” asserted John Carulli, GLOBALFOUNDRIES’ deputy director of Test Development & Diagnosis, in an exclusive discussion with SemiMD. “Presently the databases are still proprietary – either internal to the company or as part of third-party vendors’ applications.” Most of the test-related vendors and users are supporting development of the new Rich Interactive Test Database (RITdb) data format to replace the Standard Test Data Format (STDF) originally developed by Teradyne.

“The collaboration across the semiconductor ecosystem placed features in RITdb that understand the end-to-end data needs including security/provenance,” explained Carulli. Figure 2 shows that since RITdb is a structured data construct, any data from anywhere in the supply chain could be easily communicated, supported, and scaled regardless of OSAT or Fabless customer test program infrastructure. “If RITdb is truly adopted and some certification system can be placed around it to keep it from diverging, then it provides a standard core to transmit data with known meaning across our dis-aggregated semiconductor world. Another key part is the Test Cell Communication Standard Working Group; when integrated with RITdb, the improved automation and control path would greatly reduce manually communicated understanding of operational practices/issues across companies that impact yield and quality.”

Fig.2: Structure of the Rich Interactive Test Database (RITdb) industry standard, showing how data can move through the supply chain. (Source: Texas Instruments)

Phil Nigh, GLOBALFOUNDRIES Senior Technical Staff, explained to SemiMD that for heterogeneous integration of different chip types the industry has on-chip temperature measurement circuits which can monitor temperature at a given time, but not necessarily identify issues cause by thermal/mechanical stresses. “During production testing, we should detect mechanical/thermal stress ‘failures’ using product testing methods such as IO leakage, chip leakage, and other chip performance measurements such as FMAX,” reminded Nigh.

Model but verify

Metrology tool supplier Nanometrics has unique perspective on the data needs of 3D packages since the company has delivered dozens of tools for TSV metrology to the world. The company’s UniFire 7900 Wafer-Scale Packaging (WSP) Metrology System uses white-light interferometry to measure critical dimensions (CD), overlay, and film thicknesses of TSV, micro-bumps, Re-Distribution Layer (RDL) structures, as well as the co-planarity of Cu bumps/pillars. Robert Fiordalice, Nanometrics’ Vice President of UniFire business group, mentioned to SemiMD in an exclusive interview that new TSV structures certainly bring about new yield loss mechanisms, even if electrical tests show standard results such as ‘partial open.’ Fiordalice said that, “we’ve had a lot of pull to take our TSV metrology tool, and develop a TSV inspection tool to check every via on every wafer.” TSV inspection tools are now in beta-tests at customers.

As reported at 3Dincites, Mentor Graphics showed results at DAC2015 of the use of Calibre 3DSTACK by an OSAT to create a rule file for their Fan-Out Wafer-Level Package (FOWLP) process. This rule file can be used by any designer targeting this package technology at this assembly house, and checks the manufacturing constraints of the package RDL and the connectivity through the package from die-to-die and die-to-BGA. Based on package information including die order, x/y position, rotation and orientation, Calibre 3DSTACK performs checks on the interface geometries between chips connected using bumps, pillars, and TSVs. An assembly design kit provides a standardized process both chip design companies and assembly houses can use to ensure the manufacturability and performance of 3D SiP.

—E.K.

Experts Roundtable: More than Moore – manufacturing challenges for MEMS

Friday, September 27th, 2013

By Sara Verbruggen

Semiconductor Design & Manufacturing discussed ‘More than Moore‘ (MtM) standardization topics and challenges with Peter Himes, VP of marketing and strategic alliances at Silex Microsystems, Dr Eric Mounier, senior analyst, MEMS devices and technologies at Yole Développement, Tom Morrow, chief marketing officer at SEMI and Mike Rosa, senior global product strategic marketing manager – emerging technologies, 200mm components and systems group at Applied Materials. What follows are excerpts of that conversation.

SemiMD: What is the scope and potential for further standardization in MEMS fabrication – for example, consumer markets such as handheld/portable electronics demand MEMS that are smaller and lower in cost, but to what extent does the diversity in MEMS devices in terms of their functionality, applications and manufacturing defy standardization and how can this be overcome?

Peter Himes: In the MEMS industry I would say that the opportunity for standardization today is limited, but the potential for more standardization in certain areas is sure to develop. Think about the mechanical goods and products you use each day. Are all corkscrews identical? Do all blenders look the same? Are they manufactured exactly the same? Yet they all perform the same function. This is where MEMS is today, with differentiation through MEMS design. You can say that for all blenders the motor element can be the same and products can differentiate with functionality and product design, and maybe that is a model for certain classes of MEMS moving forward.

Eric Mounier: Standardization is definitively an issue for MEMS manufacturing. However, standardization can occur at two levels; packaging standardization and front-end process standardization. Both are underway in the MEMS industry.

Referring to packaging standardization, MEMS types of packaging are more complex than most standard IC packages because they require a System-in-Package type of assembly. Additionally, sensor packages are generally quite bulky and can have very specific constraints like a module with a cavity, a hole in the substrate or metal lead for pressure sensors and microphones, an optical window for optical MEMS, or a full vacuum hermeticity at the die level. As a result, standardization is becoming increasingly critical to support the massive volume grow in unit shipments along with decreasing overall costs associated with MEMS and sensor content, in particular related to their packaging. If we look at one specific MEMS example, a microphone for instance, these are all packaged the same way: BGA/LGA laminate PCB substrate + SiP module assembly with wire bonding + metal lid or PCB cap with integrated shielding + “hole” for air access.

Tom Morrow: The history and dynamics of the MEMs industry has not facilitated MEMs manufacturing standardization as we have seen in the semiconductor industry.  This is partly due to the diversity of devices where rapid adoption of some early products  — such as tire pressure monitoring, air bag deployment sensors, ink jet printing heads, and others — initially encouraged the “one product, one process” character of today’s industry.

Early on, the need for advanced and integrated process expertise as a requirement for product development challenged the development of fabless MEMS companies. It also challenged foundries whose expertise and business model depended on a “many products, one process” approach to serve multiple customers necessary to amortize their capital investment. Accelerometers, microphones and optical components are extremely diverse products requiring unique process capabilities, application “know-how” and design tools. MEMs companies were forced to develop new products with their own custom process expertise and/or depend on a manufacturing partner for joint development of new products. Also, as most MEMs manufacturing was on 6” and less wafers with secondary equipment, there was no compelling reason to standardize key equipment types and their supporting integration requirements, as there are in leading-edge semiconductors.

Mike Rosa: Today, the bulk of all high volume MEMS are built on 200mm wafers in order to satisfy the volume/price requirement – this wafer size is currently under a lot of pressure due to ASP erosion 3-5% per quarter on MEMS devices.  This has led a number of segment leaders to explore MEMS development on fully depreciated 300mm toolsets, not for the advanced line width capabilities of 300mm but simply because they can fit more devices per wafer. This combined with advanced packaging techniques will increase the number of die per wafer and reduce the per die footprint. This is currently considered the final incarnation of MEMS on wafer based technologies – beyond this, other manufacturing techniques such as roll-to-roll or large area substrate (akin to glass panel for flat screen TV) are being explored at the R&D level in an effort to support the latest drivers of mega-volume MEMS, such as wearable computing, trillion sensor vision and so on, which will require around two orders of magnitude price reduction over current MEMS devices with equivalent or increased device capability. With specific regard to the diversity in MEMS design/fabrication and its impact on their manufacturability and cost, the segment as a whole is now past this, to a large extent, with all participating vendors now owning the requisite manufacturing tools to make a variety of MEMS devices. Because of this the basic problem has reduced to number of die on a wafer and techniques used to make MEMS smaller (which means due to their requirement for minimum mass, either vertical integration of wafers/die or new sensing materials/techniques to replace current MEMS functions).

How are MEMS foundries standardizing MEMS fabrication processes to deliver faster turnaround, lower costs and reducing time to market for new MEMS device designs?
Mike Rosa: While there is, of course, a lot of discussion around standardization of MEMS processes, the reality is that very little can and is being done in this area. The foundries are usually followers in this space and work to adopt processes that can support the highest volume MEMS devices in the hope that they obtain work orders by second tier suppliers, fabless companies or overflow orders from IDMs. In recent times some of the ‘bright spots’ in standardization have occurred around the licensing of successful MEMS design architectures – fabless company Invensense is an example here, which licensed its fabrication process for Ge/Si integrated devices based on an advanced packaging technique.

Tom Morrow: As the MEMs market has grown, foundries have increasingly improved their processes, IP and technology necessary to support economical, high-volume production. Many MEM foundries have invested millions of dollars over the past several years in preparation for the emergence of a fabless MEMs market and are seeing the benefits of their efforts come to fruition.  They have invested in process capabilities, PDK and design support, are moving from custom manufacturing to platform manufacturing flows, and have leveraged their relationships with packaging and test houses to compete with MEMs IDMs.  Their standardization efforts are focused on internal or proprietary standards — how to move from custom flows to platform flows — to achieve economies of scale and work with their package and test partners on standard, repeatable, back-end business. MEMs process technology is also being increasing licensed further facilitating advanced MEMs capabilities by foundries.

Eric Mounier: We expect that as MEMS companies increasingly move beyond competing on manufacturing technology to competing on functionality, thus more of TSV / WLP packaging solutions will become widely-used platforms. A good example of an “in-house” front-end process standardization is the MIDIS platform from Teledyne Dalsa. Depending on the customer’s request, MIDIS has been developed to have a minimal change of design and process to answer the customer request. But Teledyne Dalsa is not the only one having such a standardized solution. Silex Microsystems and MEMScap have technology platforms. Other MEMS foundries with product platforms include Tronics and XFab.

Peter Himes: Today each foundry has their own efforts in this area. Some offer “standard platforms” but being able to use it depends on an exact fit of the intended design to the process flow. However, even these standard platforms should not imply they are standard across different fabs or foundries.

At Silex we have a methodology of standardizing at the block level which we call the SmartBlock approach. A process flow can be built out of two or three SmartBlock elements, plus product specific processing, to create the final process flow. This does not eliminate the process integration work or need to prove the process flow concept with actual silicon before starting any production qualification, but it does help substantially in de-risking the development, which translates in the long run to lower costs, faster time to market, and fewer unique process development efforts.