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Embedded FPGAs Offer SoC Flexibility

Wednesday, October 4th, 2017

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By Dave Lammers, Contributing Editor

It was back in 1985 that Ross Freeman invented the FPGA, gaining a fundamental patent (#4,870,302) that promised engineers the ability to use “open gates” that could be “programmed to add new functionality, adapt to changing standards or specifications, and make last-minute design changes.”

Freeman, a co-founder of Xilinx, died in 1989, too soon to see the emerging development of embedded field programmable logic arrays (eFPGAs). The IP cores offer system-on-chip (SoC) designers an ability to create hardware accelerators and to support changing algorithms. Proponents claim the approach provides advantages to artificial intelligence (AI) processors, automotive ICs, and the SoCs used in data centers, software-defined networks, 5G wireless, encryption, and other emerging applications.

With mask costs escalating rapidly, eFPGAs offer a way to customize SoCs without spinning new silicon. While eFPGAs cannot compete with custom silicon in terms of die area, the flexibility, speed, and power consumption are proving attractive.

Semico Research analyst Rich Wawrzyniak, who tracks the SoC market, said he considers eFPGAs to be “a very profound development in the industry, a capability that is going to get used in lots of places that we haven’t even imagined yet.”

While Altera, now owned by Intel, and Xilinx, have not ventured publicly into the embedded space, Wawrzyniak noted that a lively bunch of competitors are moving to offer eFPGA intellectual property (IP) cores.

Multiple competitors enter eFPGA field

Achronix Semiconductor (Santa Clara, Calif.) has branched out from its early base in stand-alone FPGAs, using Intel’s 22nm process, to an IP model. It is emphasizing its embeddable Speedcore eFPGAs that can be added to SoCs using TSMC’s 16FF foundry process. 7nm IP cores are under development.

Efinix Inc. (Santa Clara recently rolled out its Efinix Programmable Accelerator (EPA) technology.

Efinix (efinixinc.com) claims that its programmable arrays can either compete with established stand-alone FPGAs on performance, but at half the power, or can be added as IP cores to SoCs. The Efinix Programmable Accelerator technology can provide a look up table (LUT)-based logic cell or a routing switch, among other functions, the company said.

Efinix was founded by several managers with engineering experience at Altera Corp. at various times in their careers — Sammy Cheung, Tony Ngai, Jay Schleicher, and Kar Keng Chua — and has financial backing from two Malaysia-based investment funds.

Flex Logix Technologies, (Mountain View, Calif.) (www.flex-logix.com) an eFPGA startup founded in 2014, recently gained formal admittance to TSMC’s IP Alliance program. It supports a wide array of foundry processes, providing embedded FPGA IP and software tools for TSMC’s 16FFC/FF+, 28HPM/HPC, and 40ULP/LP.

Flex Logix supports several process generations at foundry TSMC. The 16nm test chip is being evaluated. (Source: Flex Logix)

QuickLogic adds SMIC to foundry roster

Menta  (http://www.menta-efpga.com/) is another competitor in the FPGA space. Based in Montpellier, France, Menta is a privately held company founded a decade ago that offers programmable logic IP targeted to both GLOBALFOUNDRIES (14LPP) and TSMC (28HPM and 28HPC+) processes.

Menta offers either pre-configured IP blocks, or custom IPs for SoCs or ASICs. The French company supports its IP with a tool set, called Origami, which generates a bitstream from RTL, including synthesis. Menta said it has fielded four generations of products that in use by customers now “for meeting the sometimes conflicting requirements of changing standards, security updates and shrinking time-to-market windows of mobile and consumer products, IoT devices, networking and automotive ICs.”

QuickLogic, a Silicon Valley stalwart founded in 1988, also is expanding its eFPGA capability. In mid-September, QuickLogic (Sunnyvale, Calif.) (quicklogic.com) announced that its eFPGA IP can now be used with the 40nm low-leakage process at Shanghai-based Semiconductor Manufacturing International Corp. (SMIC). QuickLogic also offers its eFPGA technology on several of the mature GLOBALFOUNDRIES processes, and is participating in the foundry’s 22FDX IP program.

Wawrzyniak, who tracks the SoC market for Semico Research, said an important market is artificial intelligence, using eFPGA gates to add a flexible convolutional neural network (CNN) capability. Indeed, Flex Logix said one of its earliest adopters is an AI research group at Harvard University that is developing a programmable AI processor.

A seminal capability

The U.S. government’s Defense Advanced Projects Agency (DARPA) also has supported Flex Logix by taking a license, endorsing an eFPGA capability for defense and aerospace ICs used by the U.S. military.

With security being such a concern for the Internet of Things edge devices market, Wawrzyniak said eFPGA gates could be used to secure IoT devices against hackers, a potentially large market.

“The major use is in apps and instances where people need some programmability. This is a seminal, basic capability. How many times have you heard someone say, ‘I wish I could put a little bit of programmability into my SoC.’ People are going to take this and run with it in ways we can’t imagine,” he said.

Bob Wheeler, networking analyst at The Linley Group, said the intellectual property (IP) model makes sense for startups. Achronix, during the dozen years it developed and then fielded its standalone FPGAs, “was on a very ambitious road, competing with Altera and Xilinx. Achronix went down the road of developing parts, and that is a tall order.”

While the cost of running an IP company is less than fielding stand-alone parts, Wheeler said “People don’t appreciate the cost of developing the software tools, to program the FPGA and configure the IP.” The compiler, in particular, is a key challenge facing any FPGA vendor.

Wheeler said Achronix https://www.achronix.com/ , has gained credibility for its tools, including its compiler, after fielding its high-performance discrete FPGAs in 2016, made on Intel’s 22nm process.

Achronix offers Speedcore eFPGAs, based on the same architecture as its standalone FPGAs. (Source: Achronix Semiconductor)

And Wheeler cautioned that IP companies face the business challenge of getting a fair return on their development efforts, especially for low-cost IoT solutions where companies maintain tight budgets for the IP that they license.

Achronix earlier this year announced that its 2017 revenues will exceed $100 million, based on a seven-times increase in sales of its Speedster 22i FPGA family, as well as licensing of its Speedcore embedded IP products, targeted to TSMC’s leading-edge 16 nm node, with 7nm process technology for design starts beginning in the second half of this year. Achronix revenues “began to significantly ramp in 2016 and the company reached profitability in Q1 2017,” said CEO Robert Blake.

Escalating mask costs

Flex Logix CEO Geoff Tate

Geoff Tate, now the CEO of Flex Logix Technologies, earlier headed up Rambus for 15 years. Tate said Flex Logix (www.flex-logix.com uses a hierarchical interconnect, developed by co-founder Cheng Wang and others while he earned his doctorate at UCLA. The innovative interconnect approach garnered the Lewis Outstanding Paper award for Wang and three co-authors at the 2014 International Solid-State Circuits Conference (ISSCC), and attracted attention from venture capitalists at Lux Ventures and Eclipse Ventures.

Tate said one of those VCs came to him one day and asked for an evaluation of Wang & Co.’s technology. Tate met with Wang, a native of Shanghai, and found him to be anything but a prima donna with a great idea. “He seemed very motivated, not just an R&D guy.”

While most FPGAs use a mesh interconnect in an X-Y grid of wires, Wang had come up with a hierarchical interconnect that provided high density without sacrificing performance, and proved its potential with prototype chips at UCLA.

“Chips need to be more flexible and adaptable. FPGAs give you another level of programmability,” Tate noted.

Meanwhile, potential customers in networking, data centers, and other markets were looking for ways to make their designs more flexible. An embedded FPGA block could help customers adapt a design to new wireless and networking protocols. Since mask costs were escalating, to an estimated $5 million for 16nm designs and more than double that for 7nm SoCs, customers had another reason to risk working with a startup.

TSMC has supported Flex Logix, in mid-September awarding the company the TSMC Open Innovation Platform’s Partner of the Year Award for 2017 in the category of New IP.

“Our lead customer has a working chip, with embedded FPGA on it. They are in the process of debugging rest of their chip. Overall, we are still in the early stages of market development,” Tate said, explaining that semiconductor companies are understandably risk-averse when it comes to their IP choices.

Asked about the status of its 16nm test chip, Tate said “the silicon is out of the fab. The next step is packaging, then evaluation board assembly.  We should be doing validation testing starting in late September.”

Potential customers are in the process of sending engineers to Flex Logix to look at metrics of the largest 16nm arrays, such as IR drop, vest vectors, switching simulations, and the like. “They making sure we are testing in a thorough fashion. If we screw them over, they’ll tell everybody, so we have got to get it right the first time,” Tate said.

Has SOI’s Turn Come Around Again?

Monday, October 10th, 2016

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By David Lammers, Contributing Editor

When analyst Linley Gwennap is asked about the chances that fully-depleted silicon-on-insulator (FD-SOI) technology will make it in the marketplace, he gives a short history lesson.

First, he makes clear that the discussion is not about “the older SOI,” – the partially depleted SOI that required designers to deal with the so-called “kink effect.” The FD-SOI being offered by STMicroelectronics and Samsung at 28nm design rules, and by GlobalFoundries at 22nm and 12nm, is a different animal: a fully depleted channel, new IP libraries, and no kink effect.

Bulk planar CMOS transistor scaling came to an end at 28nm, and leading-edge companies such as Intel, TSMC, Samsung, and GlobalFoundries moved into the finFET realm for performance-driven products, said Gwennap, founder of The Linley Group (Mountain View, Calif.) and publisher of The Microprocessor Report, said,

While FD-SOI at the 28nm node was offered by STMicrelectronics, with Samsung coming in as a second source, Gwennap said 28nm FD-SOI was not differentiated enough from 28nm bulk CMOS to justify the extra design and wafer costs. “When STMicro came out with 28 FD, it was more expensive than bulk CMOS, so the value proposition was not that great.”

NXP uses 28nm FD-SOI for its iMX 7 and iMX 8 processors, but relatively few other companies did 28nm FD-SOI designs. That may change as 22nm FD-SOI offers a boost in transistor density, and a roadmap to tighter design rules.

“For planar CMOS, Moore’s Law came to a dead end at 28nm. Some companies have looked at finFETs and decided that the cost barrier is just too high. They don’t have anywhere to go; for a few years now those companies have been at 28nm, they can’t justify the move on to finFETs, and they need to figure out how they can offer something new to their customers. For those companies, taking a risk on FD-SOI is starting to look like a good idea,” he said.

A cautious view

Joanne Itow, foundry analyst at Semico Research (Phoenix), also has been observing the ups and downs of SOI technology over the last two decades. The end of the early heyday, marked by PD-SOI-based products from IBM, Advanced Micro Devices, Freescale Semiconductor, and several game system vendors, has led Itow to take a cautious, Show-Me attitude.

“The SOI proponents always said, ‘this is the breakout node,’ but then it didn’t happen. Now, they are saying the Fmax has better results than finFETs, and while we do see some promising results, I’m not sure everybody knows what to do with it. And there may be bottlenecks,” such as the design tools and IP cores.

Itow said she has talked to more companies that are looking at FD-SOI, and some of them have teams designing products. “So we are seeing more serious activity than before,” Itow said. “I don’t see it being the main Qualcomm process for high-volume products like the applications processors in smartphones. But I do see it being looked at for IoT applications that will come on line in a couple of years. And these things always seem to take longer than you think,” she said.

Sony Corp. has publicly discussed a GPS IC based on 28nm FD-SOI that is being deployed in a smartwatch sold by Huami, a Chinese brand, which is touting the long battery life of the watch when the GPS function is turned on.

GlobalFoundries claims it has more than 50 companies in various stages of development on its 22FDX process, which enters risk production early next year, and the company plans a 12nm FDX offering in several years.

IP libraries put together

The availability of design libraries – both foundation IP and complex cores – is an issue facing FD-SOI. Gwennap said GlobalFoundries has worked with EDA partners, and invested in an IP development company, Invecas, to develop an IP library for its FDX technology. “Even though GlobalFoundries is basically starting from scratch in terms of putting together an IP library, it doesn’t take that long to put together the basic IP, such as the interface cells, that their customers need.

“There is definitely going to be an unusual thing that probably will not be in the existing library, something that either GlobalFoundries or the customers will have to put together. Over time, I believe that the IP portfolio will get built out,” Gwennap said.

The salaries paid to design engineers in Asia tend to be less than half of what U.S.-based designers are paid, he noted. That may open up companies “with a lower cost engineering team” in India, China, Taiwan, and elsewhere to “go off in a different direction” and experiment with FD-SOI, Gwennap said.

Philippe Flatresses, a design architect at STMicro, said with the existing FDSOI ecosystem it is possible to design a complete SoC, including processor cores from ARM Ltd., high speed interfaces, USB, MIPI, memory controllers, and other IP from third-party providers including Synopsys and Cadence. Looking at the FD-SOI roadmap, several technology derivatives are under development to address the RF, ultra-low voltage, and other markets. Flatresses said there is a need to extend the IP ecosystem in those areas.

Wafer costs not a big factor

There was a time when the approximately $500 cost for an SOI wafer from Soitec (Grenoble, France) tipped the scales away from SOI technology for some cost-sensitive applications. Gwennap said when a fully processed 28nm planar CMOS wafer cost about $3,000 from a major foundry, that $500 SOI wafer cost presented a stumbling block to some companies considering FD-SOI.

Now, however, a fully-processed finFET wafer costs $7,000 or more from the major foundries, Gwennap said, and the cost of the SOI wafer is a much smaller fraction of the total cost equation. When companies compare planar FD-SOI to finFETs, that $500 wafer cost, Gwennap said, “just isn’t as important as it used to be. And some of the other advantages in terms of cost savings or power savings are pretty attractive in markets where cost is important, such as consumer and IoT products. They present a good chance to get some key design wins.”

Soitec claims it can ramp up to 1.5 million FD-SOI wafers a year with its existing facility in 18 months, and has the ability to expand to 3 million wafers if market demand expands.

Jamie Schaeffer, the FDX program manager at GlobalFoundries, acknowledges that the SOI wafers are three to four times more expensive than bulk silicon wafers. Schaeffer said a more important cost factor is in the mask set. A 22FDX chip with eight metal layers can be constructed with “just 39 mask layers, compared with 60 for a finFET design at comparable performance levels.” And no double patterning is required for the 22FDX transistors.

Technology advantages claimed

Soitec senior fellow Bich-Yen Nguyen, who spent much of her career at Freescale Semiconductor in technology development, claims several technical advantages for FD-SOI.

FD-SOI has a high transconductance-to-drain current ratio, is superior in terms of the short channel effect, and has a lower fringing and effective capacitance and lower gate resistance, due partly to a gate-first process approach to the high-k/metal gate steps, Nguyen said.

Back and forward biasing is another unique feature of FD-SOI. “When you apply body-bias, the fT and fmax curves shift to a lower Vt.  This is an additional benefit allowing the RF designer to achieve higher fT and fmax at much lower gate voltage (Vg) over a wider Vg range.  That is a huge benefit for the RF designer,” she said. Figure 1 illustrates the unique benefit of back-bias.

Figure 1. The unique benefit of back-bias is illustrated. Source: GlobalFoundries.

“To get the full benefit of body bias for power savings or performance improvement, the design teams must consider this feature from the very beginning of product development,” she said. While biasing does not require specific EDA tools, and can be achieve with an extended library characterization, design architects must define the best corners for body bias in order to gain in performance and power. And design teams must implement “the right set of IPs to manage body biasing,” such as a BB generator, BB monitors, and during testing, a trimming methodology.

Nguyen acknowledged that finFETs have drive-current advantages. But compared with bulk CMOS, FD-SOI has superior electrostatics, which enables scaling of analog/RF devices while maintaining a high transistor gain. And drive current increases as gate length is scaled, she said.

For 14/16 nm finFETs, Nguyen said the gate length is in the 25-30 nm range. The 22FDX transistors have a gate length in the 20nm range. “The very short gate length results in a small gate capacitance, and total lower gate resistance,” she said.

For fringing capacitance, the most conservative number is that 22nm FD-SOI is 30 percent lower than leading finFETs, though she said “finFETs have made a lot of progress in this area.”

Analog advantages

It is in the analog and RF areas that FD-SOI offers the most significant advantages, Nguyen said. The fT and fMAX of 350 and 300 GHz, respectively, have been demonstrated by GlobalFoundries for its 22nm FD-SOI technology. For analog devices, she claimed that FD-SOI offers better transistor mismatch, high intrinsic device gain (Gm/Gds ratio), low noise, and flexibility in Vt tuning. Figure 2 shows how 22FDX outperforms finFETs for fT/fMax.

Figure 2. 22FDX outperforms finFETs for fT/fMax. Source: GlobalFoundries.

“FDSOI is the only device architecture that meets all those requirements. Bulk planar CMOS suffers from large transistor mismatch due to random dopant fluctuation and low device gain due to poor electrostatics. FinFET technology improves on electrostatics but it lacks the back bias capability.”

The undoped channel takes away the random doping effect of a partially depleted (doped) channel, reducing variation by 50-60 percent.

Analog designers using FD-SOI, she said, have “the ability to tune the Vt by back-bias to compensate for process mismatch or drift, and to offer virtually any Vt desired. Near-zero Vt can also be achieved in FD-SOI, which enables low voltage analog design for low power consumption applications.”

“If you believe the future is about mobility, about more communications and low power consumption and cost sensitive IoT chips where analog and RF is about 50 percent of the chip, then FD-SOI has a good future.

“No single solution can fit all. The key is to build up the ecosystem, and with time, we are pushing that,” she said.

Blog review March 10, 2014

Monday, March 10th, 2014

Pete Singer is pleased to announce that IBM’s Dr. Gary Patton will provide the keynote talk at The ConFab on Tuesday, June 24th. Gary is Vice President of IBM’s Semiconductor Research and Development Center in East Fishkill, New York, and has responsibility for IBM’s semiconductor R&D roadmap, operations, and technology development alliances.

Nag Patibandla of Applied Materials describes a half-day workshop at Lawrence Berkeley Lab that assembled experts to discuss challenges and identify opportunities for collaboration in semiconductor manufacturing including EUV lithography, advanced etch techniques, compound semiconductors, energy storage and materials engineering.

Adele Hars of Advanced Substrate News reports on a presentation by ST’s Joël Hartmann (EVP of Manufacturing and Process R&D, Embedded Processing Solutions) during SEMI’s recent ISS Europe Symposium. FD-SOI is significantly cheaper, outdoes planar bulk and matches bulk FinFET in the performance/power ratio, and keeps the industry on track with Moore’s Law, she writes.

Phil Garrou reports on the RTI- Architectures for Semiconductor Integration & Packaging (ASIP) conference, which is focused on commercial 3DIC technology. Timed for release at RTI ASIP was the announcement that Novati had purchased the Ziptronix facility outside RTP NC. Tezzaron had been a licensee of the Ziptronix’s direct bonding technologies, ZiBond™ and DBI® and they now have control of the Ziptronix facility to serve as a second source for their processing. In addition Tezzaron’s Robert Patti announced that they were partnering with Invensas on 2.5 and 3DIC assembly.

Vivek Bakshi, EUV Litho, Inc., blogs that most of the papers at this year’s EUVL Conference during SPIE’s 2014 Advanced Lithography program focused on topics relating to EUVL’s entrance into high volume manufacturing (HVM).

On March 2, 2014 SIA announced that worldwide sales of semiconductors reached $26.3 billion for the month of January 2014, an increase of 8.8% from January 2013 when sales were $24.2 billion. After adding in semiconductor sales from excluded companies such as Apple and Sandisk, that total is even higher, marking the industry’s highest-ever January sales total and the largest year-to-year increase in nearly three years. These results are in-line with the Semico IPI index which has been projecting strong semiconductor revenue growth for the 1st and 2nd quarters of 2014.

Blog review February 10, 2014

Monday, February 10th, 2014

Dick James of ChipWorks blogs that when Intel launched their Haswell series chips last June, they stated that the high-end systems would have embedded DRAM, as a separate chip in the package. “It took us a while to track down a couple of laptops with the requisite Haswell version, but we did and now we have a few images that show it’s a very different structure from the other e-DRAMs that we’ve seen,” he notes.

Phil Garrou continues his look at the 2013 Georgia Tech Interposer Conference, focusing on presentations from Amkor and GlobalFoundries. He writes that Ron Huemoeller of Amkor projects that in the high end silicon will dominate; in the mid-end, silicon will be prominent and organic /glass may play a role; in the low end, organic, or low cost glass or silicon if they exist will play a role. Dave McCann of GlobalFoundries examined market needs for interposers.

Semico’s review of the latest and greatest from the Consumer Electronics Show highlights five technologies they think you should pay attention to as game changers: 3D Printing, the Bosch wireless sensor network for IoT; Bionics: Thought-controlled prosthetics; Aging in place: Pain relief; and LED Lighting.

Vivek Bakshi, of EUV Litho, Inc., ponders some interesting questions, such as how important is the semiconductor industry relative to other industries, and how did we get to where we are, the continuation of Moore’s Law and why have there been so few Nobel prizes given to the chip industry?

Karen Lightman of the MEMS Industry Group says the upcoming MEMS Executive Congress Europe “checks all the boxes” with great content and speakers, networking time with MEMS industry execs and OEM users, and an unbeatable location in Munich.

Pete Singer takes a look back at February 1964 through the pages of Solid State Technology, when wafers were small, dreams were big and The Beatles were on the Ed Sullivan show. The issue discussed thermionic energy convertors, the potential of which is still being explored today by Stanford.