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Posts Tagged ‘nanowire’

Tallness Makes Reliable Spindt Tip Cold Cathodes

Monday, November 30th, 2015

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By Ed Korczynski, Sr. Technical Editor

MIT researchers have seemingly found a solution to a half-century-old engineering challenge:  how to make a reliable cold cathode array for vacuum electronic devices. While solid-state technology continues to replace vacuum tubes for most electronic applications—the most recent being light emitting diode (LED) luminaires replacing both incandescent and fluorescent light bulbs—there are still applications where vacuum-based devices provide unmatched performance. At the IEEE’s upcoming annual International Electron Devices Meeting (IEDM www.ieee-iedm.org), Stephen Guerrera will present paper number 33.1 entitled “High Performance and Reliable Silicon Field Emission Arrays Enabled by Silicon Nanowire Current Limiters” on behalf of his team. Since these field emission arrays (FEA) are built in silicon, they can be integrated as cold cathodes with silicon ICs to function as compact RF amplifiers and as sources of terahertz, infrared, and X-ray energy.

Figure 1 shows a 3D illustration of the FEA structure, along with scanning electron microscope (SEM) close-up images of one tip cross-section and the tip array. The array of cold cathodes can be considered as a group of nanoscale electron guns. Each 10µm tall and 100-200nm diameter vertical silicon nanowire is topped by a 6-8nm diameter conical emitter tip.

FIGURE 1: (top) 3D schematic of the FEA device structure showing 50:1 aspect-ratio silicon nanowires, and (bottom) left-side SEM image of one tip cross-section, and right-side plan-view SEM of gate holes showing 1µm spacing and a gate aperture of 350nm.

As can be seen in the bottom left of Figure 1, the researchers used a variation on the now-standard “Bosch” deep reactive ion etch (DRIE, http://www.samcointl.com/tech/03_bosch.php) process to form the nanowires. The Bosch process uses vertical etching with side-wall dielectric deposition in alternating sequences such that cross-sections appear with characteristic scalloped profiles. It appears that the other unit-processes used by the MIT team to create this new device are likewise similar to industry standards.

However, while based on standard processes, the cost of using a Bosch etch and the other steps needed to fabricate the 50:1 aspect-ratio (AR) of these 200nm diameter wires is inherently high. In constrast, 5:1 AR structures can be formed using much less expensive processes, while 1:1 AR cones as used in original Spindt tips can be very inexpensive to make. Why do these nanowires need to be so tall?

SPINDT-TIP TRAUMAS

Decades before organic light emitting diode (OLED) technology was to be the future of flat panel display (FPD) manufacturing, Field Effect Display (https://en.wikipedia.org/wiki/Field_emitter_array FED) technology was explored as a more efficient replacement for liquid crystal displays (LCD). FED have typically been built using “Spindt Tip” Arrays, named after Charles A. Spindt who developed the technology for SRI International as originally published as “A thin-film field-emission cathode,” Journal of Applied Physics, vol. 39, no. 7, pages 3504-3505, 1968. Figure 2 shows how FED use multiple redundant Spindt Tips to light up the phosphor in each color sub-pixel. With ten or more connected in parallel, if one tip fails then the remaining tips in the sub-pixel cluster only have to handle a 10% increase in current…under another tip fails…and another tip will fail over time without a way to limit current.

FIGURE 2: Cross-sectional schematic of a pixel in a field effect display (FED), showing multiple redundant Spindt Tips driving a single phosphor dot.

Though inherently prone to reliability issues, the original Spindt Tip design is extraordinarily manufacturable. After layers of blanked film depositions, the top gate is patterned with uniform holes which serve as masks for both the etching of cavities and the deposition of tips. Each resulting cone-shaped tip concentrates the current to the point, allowing for efficient low voltage operation. The problem with concentrating current is that over time it tends to find a weak spot in grain boundaries resulting in decreased electrical resistance on one side of a tip, such that current flow over-concentrates and run-away heating causes the tip to fail.

In 2002 and still with SRI International, Spindt was co-author on “Spindt cathode tip processing to enhance emission stability and high-current performance” published by the American Vacuum Society [DOI: 10.1116/1.1527954]. The paper describes using the extracted field emission current to controllably heat and recrystallize the surface of Spindt tips to drive off impurities and smooth the tip surface, thereby producing more uniform physical arrays for more reliable functionality.

While alloys and anneals can improve the reliability, the run-away over-heating effect remains an inherent issue with conical tips. Dean et al. from Motorola worked on FEDs for many years, and found that individual tips emit from multiple nano-scale features with fluctuating current levels [DOI: 10.1109/IVMC.2001.939681]. It only takes one of these nano-scale features to preferentially line-up with a grain-boundary for it to draw relatively more current, and with electro-migration the feature can grow from the surface to be relatively closer to the gate compared to the rest of the tip. A protruding nano-spike create an extremely concentrated electrical field, which further concentrates the current flowing to the protrusion until it tends to physically explode.

TALL NANOWIRES LIMIT CURRENT

Having exhausted all easier solutions, it now appears that using DRIE to create 50:1 AR vertical nanowires is the way to make reliable FEA. The nanowires act as current limiters to protect each emitter tip from run-away heating and arcing, and thereby design-in reliability unlike simple Spindt Tip cones. Since high-quality silicon epitaxial layers with controlled dopant levels to ensure uniform electrical resistivity can be commercially sourced, the resistance of nanowire arrays etched from such an epi-layer can be easily controlled. These device reportedly exhibit long lifetimes and low-voltage operation.

The team built emitter arrays as large as 1,000 x 1,000, and have shown ability to handle current density of >100 A/cm2, more than a hundredfold greater than any other field-emission cathode operated in continuous wave mode. These new devices combine the positive aspects of solid state semiconductors (high gain and low noise) with those of vacuum electronics (high power and efficiency). While not likely to appear in commercial FPDs, there seems to be demand for this technology in diverse communications, defense, and healthcare applications.

—E.K.

5nm Node Needs EUV for Economics

Thursday, January 29th, 2015

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By Ed Korczynski, Sr. Technical Editor

#mce_temp_url#

At IEDM 2014 last month in San Francisco, Applied Materials sponsored an evening panel discussion on the theme of “How do we continue past 7nm?” Given that leading fabs are now ramping 14nm node processes, and exploring manufacturing options for the 10nm node, “past 7nm” means 5nm node processing. There are many device options possible, but cost-effective manufacturing at this scale will require Extreme Ultra-Violet (EUV) lithography to avoid the costs of quadruple-patterning.

Fig. 1: Panelists discuss future IC manufacturing and design possibilities in San Francisco on December 16, 2014. (Source: Pete Singer)

Figure 1 shows the panel being moderated by Professor Mark Rodwell of the University of California Santa Barbara, composed of the following industry experts:

  • Karim Arabi, Ph.D. – vice president, engineering, Qualcomm,
  • Michael Guillorn, Ph.D. – research staff member, IBM,
  • Witek Maszara, Ph.D. – distinguished member of technical staff, GLOBALFOUNDRIES,
  • Aaron Thean, Ph.D. – vice president, logic process technologies, imec, and
  • Satheesh Kuppurao, Ph.D. – vice president, front end products group, Applied Materials.

Arabi said that from the design perspective the overarching concern is to keep “innovating at the edge” of instantaneous and mobile processing. At the transistor level, the 10nm node process will be similar to that at the 14nm node, though perhaps with alternate channels. The 7nm node will be an inflection point with more innovation needed such as gate-all-around (GAA) nanowires in a horizontal array. By the 5nm node there’s no way to avoid tunnel FETs and III-V channels and possibly vertical nanowires, though self-heating issues could become very challenging. There’s no shortage of good ideas in the front end and lots of optimism that we’ll be able to make the transistors somehow, but the situation in the backend of on-chip metal interconnect is looking like it could become a bottleneck.

Guillorn extolled the virtues of embedded-memory to accelerate logic functions, as a great example of co-optimization at the chip level providing a real boost in performance at the system level. The infection at 7nm and beyond could lead to GAA Carbon Nano-Tube (CNT) as the minimum functional device. It’s limited to think about future devices only in terms of dimensional shrinks, since much of the performance improvement will come from new materials and new device and technology integration. In addition to concerns with interconnects, maintaining acceptable resistance in transistor contacts will be very difficult with reduced contact areas.

Maszara provided target numbers for a 5nm node technology to provide a 50% area shrink over 7nm:  gate pitch of 30nm, and interconnect level Metal 1 (M1) pitch of 20nm. To reach those targets, GLOBALFOUNDRIES’ cost models show that EUV with ~0.5 N.A. would be needed. Even if much of the lithography could use some manner of Directed Self-Assembly (DSA), EUV would still be needed for cut-masks and contacts. In terms of device performance, either finFET or nanowires could provide desired off current but the challenge then becomes how to get the on current for intended mobile applications? Alternative channels with high mobility materials could work but it remains to be seen how they will be integrated. A rough calculation of cost is the number of mask layers, and for 5nm node processing the cost/transistor could still go down if the industry has ideal EUV. Otherwise, the only affordable way to go may be stay at 7nm node specs but do transistor stacking.

Thein detailed why electrostatic scaling is a key factor. Parasitics will be extraordinary for any 5nm node devices due to the intrinsically higher number of surfaces and junctions within the same volume. Just the parasitic capacitances at 7nm are modeled as being 75% of the total capacitance of the chip. The device trend from planar to finFET to nanowires means proportionally increasing relative surface areas, which results in inherently greater sensitivity to surface-defects and interface-traps. Scaling to smaller structures may not help you if you loose most of the current and voltage in non-useful traps and defects, and that has already been seen in comparisons of III-V finFETs and nanowires. Also, 2D scaling of CMOS gates is not sustainable, and so one motivation for considering vertical transistors for logic at 5nm would be to allow for 20nm gates at 30nm pitch.

Kappurao reminded attendees that while there is still uncertainty regarding the device structures beyond 7nm, there is certainty in 4 trends for equipment processes the industry will need:

  1. everything is an interface requiring precision materials engineering,
  2. film depositions are either atomic-layer or selective films or even lattice-matched,
  3. pattern definition using dry selective-removal and directed self-assembly, and
  4. architecture in 3D means high aspect-ratio processing and non-equilibrium processing.

An example of non-equilibrium processing is single-wafer rapid-thermal-annealers (RTA) that today run for nanoseconds—providing the same or even better performance than equilibrium. Figure 2 shows that a cobalt-liner for copper lines along with a selective-cobalt cap provides a 10x improvement in electromigration compared to the previous process-of-record, which is an example of precision materials engineering solving scaling performance issues.

Fig. 2: ElectroMigration (EM) lifetimes for on-chip interconnects made with either conventional Cu or Cu lined and capped with Co, showing 10 times improvement with the latter. (Source: Applied Materials)

“We have to figure out how to control these materials,” reminded Kappurao. “At 5nm we’re talking about atomic precision, and we have to invent technologies that can control these things reliably in a manufacturable manner.” Whether it’s channel or contact or gate or interconnect, all the materials are going to change as we keep adding more functionality at smaller device sizes.

There is tremendous momentum in the industry behind density scaling, but when economic limits of 2D scaling are reached then designers will have to start working on 3D monolithic. It is likely that the industry will need even more integration of design and manufacturing, because it will be very challenging to keep the cost-per-function decreasing. After CMOS there are still many options for new devices to arrive in the form of spintronics or tunnel-FETs or quantum-dots.

However, Arabi reminded attendees as to why the industry has stayed with CMOS digital synchronous technology leading to design tools and a manufacturing roadmap in an ecosystem. “The industry hit a jackpot with CMOS digital. Let’s face it, we have not even been able to do asynchronous logic…even though people tried it for many years. My prediction is we’ll go as far as we can until we hit atomic limits.”


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