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Posts Tagged ‘nanoimprint’

What’s the Next-Gen Litho Tech? Maybe All of Them

Thursday, February 25th, 2016

By Jeff Dorsch, Contributing Editor

The annual SPIE Advanced Lithography symposium in San Jose, Calif., hasn’t offered a clear winner in the next-generation lithography race. It’s becoming clearer, however, that 193i immersion and extreme-ultraviolet lithography will co-exist in the future, while directed self-assembly, nanoimprint lithography, and maybe even electron-beam direct-write technology will fit into the picture, too.

At the same time, plasma deposition and etching processes are assuming a greater interdependence with 193i, especially when it comes to multiple patterning, such as self-aligned double patterning, self-aligned quadruple patterning, and self-aligned octuple patterning (yes, there is such a thing!).

“We’ve got to go down to the sub-nanometer level,” Richard Gottscho, Lam Research’s executive vice president of global products, said Monday morning in his plenary presentation at the conference. “We must reduce the variability in multiple patterning,” he added.

Gottscho touted the benefits of atomic level processing in continuing to shrink IC dimensions. Atomic level deposition has been in volume production for a decade or more, he noted, and atomic level etching is emerging as an increasingly useful technology.

When it comes to EUV, “it’s a matter of when, not if,” the Lam executive commented. “EUV will be complementary with 193i.”

Anthony Yen, director of nanopatterning technology in the Infrastructure Division of Taiwan Semiconductor Manufacturing, followed Gottscho in the plenary session. “The fat lady hasn’t sung yet, but she’s on the stage,” he said of EUV.

Harry Levinson, senior director of GlobalFoundries, gave the opening plenary presentation, with the topic of “Evolution in the Concentration of Activities in Lithography.” He was asked after his presentation, “When is the end?” Levinson replied, “We’re definitely not going to get sub-atomic.”

With that limit in mind, dozens of papers were presented this week on what may happen before the semiconductor industry hits the sub-atomic wall.

There were seven conferences within the symposium, on specific subjects, along with a day of classes, an interactive poster session, and a two-day exhibition.

The Alternative Lithographic Technologies conference was heavy on directed self-assembly and nanoimprint lithography papers, while also offering glimpses at patterning with tilted ion implantation and multiphoton laser ablation lithography.

“Patterning is the battleground,” said David Fried, Coventor’s chief technology officer, semiconductor, in an interview at the SPIE conference. He described directed self-assembly as “an enabler for optical lithography.”

Mattan Kamon of Coventor presented a paper on Wednesday afternoon on “Virtual fabrication using directed self-assembly for process optimization in a 14nm DRAM node.”

DSA could be used in conjunction with SAQP or LELELELE, according to Fried. While some lithography experts remain leery or skeptical about using DSA in high-volume manufacturing, the Coventor CTO is a proponent of the technology’s potential.

“Unit process models in DSA are not far-fetched,” he said. “I think they’re pretty close.  The challenges of EUV are well understood. DSA challenges are a little less clear. There’s no ‘one solution fits all’ with DSA.” Fried added, “There are places where DSA can still win.”

Franklin Kalk, executive vice president of technology for Toppan Photomasks, is open to the idea of DSA and imprint lithography joining EUV and immersion in the lithography mix. “It will be some combination,” he said in an interview, while adding, “It’s a dog’s breakfast of technologies. Don’t ever count anything out.”

Richard Wise, Lam’s technical managing director in the company’s Patterning, Global Products Groups CTO Office, said EUV, when ready, will likely be complementary with multipatterning for 7 nanometer.

Self-aligning quadruple patterning, for example, was once considered “insanity” in the industry, yet it is a proven production technology now, he said.

While EUV technology is “very focused on one company,” ASML Holding, there is a consensus at SPIE that EUV’s moment is at hand, Wise said. Intel’s endorsement of the technology and dedication to advancing it speaks volumes of EUV’s potential, he asserted.

“Lam’s always excelled in lot-to-lot control,” an area of significant concern, Wise said, especially with all of this week’s talk about process variability.

What will be the final verdict on the future of lithography technology? Stay tuned.

Research Alert: June 3, 2014

Tuesday, June 3rd, 2014

Georgia Tech research develops physics-based spintronic interconnect modeling for beyond-CMOS computing

Georgia Institute of Technology researchers collaborating with and sponsored by Intel Corporation through the Semiconductor Research Corporation (SRC) have developed a physics-based modeling platform that advances spintronics interconnect research for beyond-CMOS computing.

Spin-logic aims at reducing power consumption of electronic devices, thereby improving battery life and reducing energy consumption in computing for a whole range of electronic product applications from portable devices to data centers.

“After more than four decades of exponential growth in the performance of electronic integrated circuits, it is now apparent that improving the energy efficiency of computing is a primary challenge,” said Ian A. Young, a collaborator and co-author of the research and a Senior Fellow at Intel Corporation. “There is a global search for information processing elements that use computational state variables other than electronic charge, and these devices are being sought to bring in new functionalities and further lower the power dissipation in computers.”

One of the main motivations behind the search for a next-generation computing switch beyond CMOS (complementary metal oxide semiconductor) devices is to sustain the advancement of Moore’s Law. Nanomagnetic/spintronic devices provide a complementary option to electronics. The added functionality of this option includes the non-volatility of information on-chip, which is in essence a combination of logic and memory functions. However, to benefit from the increase in density of the on-chip devices, there has to be adequate connectivity among the switches—which is the focus of the Georgia Tech research.

Among the potential alternatives, devices based on nanoscale magnets in the field of spintronics have received special attention thanks to their advantages in terms of robustness and enhanced functionality. Magnets are non-volatile: their state remains even if the power to the circuit is switched off. Thus, the circuits do not consume power when not used—a very desirable property for modern tablets and smart phones.

One of the most important aspects of any new information processing element is how fast and power efficient they can communicate over an interconnect system with one another. In today’s CMOS chips, more energy is consumed communicating between transistor logic functions than actually processing of information. The Georgia Tech research has therefore focused on this important aspect of communicating between spin-logic devices and demonstrates that interconnects are an even more important challenge for beyond-CMOS switches.

To analyze spintronic interconnects, the Georgia Tech team and their Intel collaborators have developed compact models for spin transport in copper and aluminum—taking into account the scattering at wire surfaces and grain boundaries that become quite dominant at nanoscale dimensions. The research team has also developed compact models for the nanomagnet dynamic, electronic and spintronic transport through magnet to non-magnet interfaces, electric currents and spin diffusion. These models are all based on familiar electrical elements such as resistors and capacitors and can therefore be analyzed using standard circuit simulation tools such as SPICE.

New cost-effective nanoimprint lithography methodology improves ordering in periodic arrays from block copolymers

Block copolymers (BCPs) are the most attractive alternative to date for the fabrication of well-defined complex periodic structures with length scales below 100nm. Such small structures might be used in a wide range of technological applications but current available methods are very expensive, especially when those structures present length scales under 20nm.

A work led by the Institut Català de Nanociència i Nanotecnologia (ICN2) Phononic and Photonic Nanostructures Group suggests a new method to produce hexagonal periodic arrays with high fidelity while reducing time and costs. ICREA Research Professor Dr Clivia M. Sotomayor Torres and Dr Claudia Simão conducted, together with the authors listed below, a work published in a recent issue of Nanotechnology and featured cover article.

The methodology consists on in situ solvent-assisted nanoimprint lithography of block copolymers, a technique which combines a top-down approach – nanoimprint lithography – with a bottom-up one – self-assembled block copolymers (bottom-up). The process is assisted with solvent vapors to facilitate the imprint and simultaneous self-assembly of high Flory-Huggins parameter BCPs, the ones that yield sub-15nm size features, in what has been called solvent vapors assisted nanoimprint lithography (SAIL).

SAIL is a scalable technique which has shown its efficiency over a large area of up to four square inches wafers. The resulting sample was analysed using different methods, including field emission scanning electron microscopy (FE-SEM) and grazing-incidence small-angle x-ray scattering (GISAXS). The latter was performed at the Diamond synchrotron light source (UK) and allowed characterisation of structural features of the nanostructured polymer surfaces. It is the first time that GISAXS has been used to analyse a direct-nanoimprint BCP sample.

The results obtained with SAIL demonstrated an improvement in ordering of the nanodot lattice of up to 50%. It is a low cost, scalable and fast technique which brings self-assembled BCPs closer to their industrial application. These versatile materials are very interesting for applications such as storage devices, nano-electronics, low-k dielectrics or biochemical applications.

UT Dallas team creates flexible electronics that change shape inside body

Researchers from The University of Texas at Dallas and the University of Tokyo have created electronic devices that become soft when implanted inside the body and can deploy to grip 3-D objects, such as large tissues, nerves and blood vessels.

These biologically adaptive, flexible transistors might one day help doctors learn more about what is happening inside the body, and stimulate the body for treatments.

The research is one of the first demonstrations of transistors that can change shape and maintain their electronic properties after they are implanted in the body, said Jonathan Reeder BS ’12, a graduate student in materials science and engineering and lead author of the work.

“Scientists and physicians have been trying to put electronics in the body for a while now, but one of the problems is that the stiffness of common electronics is not compatible with biological tissue,” he said. “You need the device to be stiff at room temperature so the surgeon can implant the device, but soft and flexible enough to wrap around 3-D objects so the body can behave exactly as it would without the device. By putting electronics on shape-changing and softening polymers, we can do just that.”

Shape memory polymers developed by Dr. Walter Voit, assistant professor of materials science and engineering and mechanical engineering and an author of the paper, are key to enabling the technology.

The polymers respond to the body’s environment and become less rigid when they’re implanted. In addition to the polymers, the electronic devices are built with layers that include thin, flexible electronic foils first characterized by a group including Reeder in work published last year in Nature.

The Voit and Reeder team from the Advanced Polymer Research Lab in the Erik Jonsson School of Engineering and Computer Science fabricated the devices with an organic semiconductor but used adapted techniques normally applied to create silicon electronics that could reduce the cost of the devices.

“We used a new technique in our field to essentially laminate and cure the shape memory polymers on top of the transistors,” said Voit, who is also a member of the Texas Biomedical Device Center. “In our device design, we are getting closer to the size and stiffness of precision biologic structures, but have a long way to go to match nature’s amazing complexity, function and organization.”

The rigid devices become soft when heated. Outside the body, the device is primed for the position it will take inside the body.

During testing, researchers used heat to deploy the device around a cylinder as small as 2.25 millimeters in diameter, and implanted the device in rats. They found that after implantation, the device had morphed with the living tissue while maintaining excellent electronic properties.

“Flexible electronics today are deposited on plastic that stays the same shape and stiffness the whole time,” Reeder said. “Our research comes from a different angle and demonstrates that we can engineer a device to change shape in a more biologically compatible way.”

The next step of the research is to shrink the devices so they can wrap around smaller objects and add more sensory components, Reeder said.