By Mark LaPedus

For years, the DRAM industry has been engulfed in a downturn. Sadly, vendors have grown accustom to overcapacity, falling ASPs and losses. Now, the tide is turning, at least based on the data from Micron Technology. Micron posted a loss this week, but the company provided some surprising and welcomed news about DRAMs. “Despite a weak PC environment and more DRAM capacity from the revised Inotera agreement, Micron is allocating DRAM to some channel and OEM customers. DRAM capacity continues to go offline or transition to NAND, and Micron envisions no new capacity coming online in either 2013 or 2014. This suggests to us that the recent ASP dynamic is here to stay,” said Hans Mosesmann, an analyst with Raymond James. Another chip analyst, Jagadish Iyer of Piper Jaffray, said: “Micron articulated that DRAM capacity likely remains constrained for the next two years as near-term allocation prevails.”

What about NAND flash? “We expect industry supply to be far more rational than years past. Expect NAND ASP trends to strengthen through 2Q ‘13 with handset ramps pending,” said Doug Freedman, an analyst with RBC Capital Markets. Added Monika Garg, an analyst with Pacific Crest: “During our meetings with semiconductor capital equipment companies last month, all companies highlighted that they have not yet received any NAND capacity orders. These comments lend conviction that we should see strong NAND supply-demand balance in 2013.”

Richard Hill, the former chairman and CEO of Novellus, is back in the news. Hill, an outspoken executive who left Novellus after it was acquired by Lam, is leading a committee of independent directors for troubled Tessera. The committee is refocusing Tessera’s DigitalOptics unit. This follows a move by an investment firm to oust Tessera’s CEO and the board.  This week, the board began a search for a new chief executive to replace Robert A. Young, who was ousted. And Hill is the new chairman.

The Saratoga County Industrial Development Agency has approved about $387 million in sales tax exemptions for GlobalFoundries, according to the Saratogian. The tax breaks are for an R&D center and a proposed fab in New York.

In a blog, an investment site discusses its price estimates for Applied Materials. It also gives a fair and balanced analysis of the company.

RF Micro Devices will phase out manufacturing in its Newton Aycliffe, U.K.-based GaAs pHEMT facility and transition most GaAs manufacturing to its GaAs HBT manufacturing facility in Greensboro, N.C. RFMD will also partner with leading GaAs foundries for additional capacity. The U.K.-based GaAs pHEMT facility had been RFMD’s primary source for cellular switches. However, RFMD has transitioned to higher-performance, lower-cost silicon-on-insulator (SOI) technology for the cellular switch.

North American-based manufacturers of semiconductor equipment posted a book-to-bill ratio of 1.10 in February, according to SEMI. This compares to a ratio of 1.11 in January.

SEMI has released the 4th edition of the International Technology Roadmap for PV (ITRPV), the global collaborative process that informs PV cell, module and system manufacturers, equipment and materials suppliers, and other industry stakeholders on key technology trends in the solar field.

Mentor Graphics and Mercedes-Benz Trucks announced the application of the Mentor Capital software suite to the development of Daimler’s flagship heavy truck, the new Actros.

TEL’s Q3 orders were up 27%, above the firm’s original guidance of “slightly up,” according to Chips and Dips, a blog site.

Golden Gate Capital, a venture capital firm, recently sold its e-beam company, Vistec, to two different companies. In one transaction, Raith recently acquired Vistec’s Gaussian e-beam unit, called Vistec Lithography. Vistec Lithography continues to specialize in conventional direct-write applications in the aerospace and military arena. In a separate move, the Heidenhain Group recently acquired Vistec’s variable shaped beam (VSB) e-beam unit. That operation, Vistec Electron Beam, sells a single-beam e-beam tool based on VSB technology.

Samsung’s new Galaxy S4 smartphone is causing a buzz. In a blog DisplaySearch answered a pressing question: How Did Samsung achieve full HD in the AMOLED display?

Spansion and XMC, a Chinese foundry, announced an expanded partnership to develop and manufacture Spansion’s 32nm NOR flash memory. The agreement expands XMC’s current 300mm manufacturing of Spansion’s 65nm and 45nm flash memory technology.

VLSI Research is raising its 2013 fab tool growth forecast to minus 4.6%. Previously, the 2013 forecast was minus 5.3%. “Memory suppliers are beginning to loosen their purse strings. The orders are technology buys. Capacity expansions are not in the radar. Foundry is cooling due to the pull back by Apple along with some inventory buildups,” according to the firm.

Global PC shipments were expected to decline by 7.7% in the first quarter, according to IDC. However, IDC’s February monthly data suggest that the market could see a drop touching double-digits in the first quarter, according to the firm.

A predicted surge of smaller, lower-priced devices in the tablet market has led IDC to increase its 2013 forecast for the worldwide tablet market to 190.9 million, up from its previous forecast of 172.4 million units.

Samsung catapulted to the top of the optoelectronics supplier ranking in 2012 from 12th place in 2011 after it gained full ownership of Samsung LED, a 50-50 joint venture in light-emitting diodes that was created in 2009 between Samsung Electronics and affiliate Samsung Electro-Mechanics, according to IC Insights.

By Mark LaPedus
Ten years ago, Intel Corp. declared that flash memory would stop scaling at 65nm, prompting the need for a new replacement technology.

Thinking the end was near for flash, a number of companies began to develop various next-generation memory types, such as 3D chips, FeRAM, MRAM, phase-change memory (PCM), and ReRAM. Many of these technologies were originally billed as “universal memories.” By definition, a “universal memory” is a single product that could replace all four conventional memory types: DRAM, NAND, NOR and SRAM.

As it turned out, conventional memory has scaled much further than previously thought, pushing out the need for the next-generation technologies. And, in fact, most next-generation memory types are still in R&D. They are expensive to make and difficult to scale.

While there is a frenzy of activity in next-generation memories, the rhetoric surrounding the “universal memory” is fading. Because of the complexity and soaring I/O requirements in today’s systems, there is no single next-generation memory type that has the cost benefits of DRAM, the speed of SRAM, and the non-volatility of flash.

“It is unlikely that we will see a universal memory,” said Gill Lee, a senior director and principal member of the technical staff at Applied Materials. “I do not see a new memory type can replace both NAND and DRAM.”

Clearly, after years of hype, the universal memories have come back down to earth. In possibly the best-case scenario, a next-generation technology could become a mere one-to-one replacement for today’s memory types, Lee said. “We might see them in certain applications and segments,” he said.

Universal niches
In the meantime, HP, Intel, IBM, Micron, SK Hynix, Toshiba, Samsung and others are developing various next-generation memory types. Because it remains unclear which technology will replace DRAM and flash, the larger players are developing most next-generation memory types.

There is a sense of urgency to develop these technologies. DRAM could stop scaling somewhere at the 1nm node. “There is not much room for the floating gate to scale in flash. Nobody really believes that planar NAND can go below 10nm,” Lee added.

In one possible scenario in the next five years (or longer), a next-generation MRAM called spin-torque MRAM (STT-RAM) is the candidate to replace DRAM and SRAM. Also in the distant future, 3D NAND and ReRAM may replace NAND flash and the disk drive.

And PCM could not only displace NOR, but it could also emerge as a new class of so-called storage-class memory. MRAM and ReRAM also are being positioned as storage-class memories, which supposedly fit between the main memory and the processor to alleviate the I/O bottleneck in a system.

Alan Niebel, chief executive of Web-Feet Research, has a different viewpoint. The next-generation memory types are classified as storage-class memories, which can be sub-divided into two groups: memory (DRAM-like) and storage (NAND-like), Niebel said. “Possibly by 2020, one technology may be able to bridge the cost, performance, persistence, and power parameters to satisfy both memory and storage needs,” he said. “In the meantime, the leading replacements for NAND in storage are phase-change and ReRAM. STT-RAM could be a DRAM replacement, but it is too costly for storage.”

NAND and DRAM replacements
If or when planar NAND runs out of gas, the prevailing school of thought is that 3D NAND will replace NAND, followed much later by ReRAM. ReRAM is non-volatile and based on the electronic switching of a resistor element material between two stable resistive states. Startup Adesto is sampling one form of ReRAM, dubbed conductive bridging RAM (CBRAM), which is an EEPROM replacement. HP, Micron, Samsung, SK Hynix and others are working on NAND-replacement ReRAMs.

The first ReRAMs are based on a 1T1R (1 transistor and 1 resistor) structure. Next-generation ReRAMs are based on a 1R structure and consist of various architectures, such as 3D and cross-point arrays. These ReRAMs present several challenges, prompting some to believe that these memories won’t appear until 2015 or so. “Each of the metal layers requires advanced lithography, which is very expensive,” said David Eggleston, senior vice president at Rambus. In 2012, Rambus acquired ReRAM developer Unity Semiconductor.

At a recent event, SK Hynix outlined its strategy, which typifies the roadmap of a NAND vendor. First, SK Hynix will continue to extend planar NAND. “I think scaling NAND to 12nm will be very challenging,” said Sung Wook Park, executive vice president and head of the R&D Center at SK Hynix.

SK Hynix is separately developing a 12nm planar NAND part and 3D NAND. 3D NAND is targeted as the successor to planar NAND, Park said. In addition, the company is also working on next-generation STT-RAM with Toshiba. SK Hynix is separately co-developing PCM with IBM.

The industry also is keeping a close eye on SK Hynix and Hewlett-Packard, which have been jointly working on commercializing HP’s memristor by 2015. A form of ReRAM, memristor is a passive two-terminal electronic device. In memristance, if the flow of a charge is stopped by turning off the applied voltage, this component will “remember” its last resistance.

Initially, devices based on the memristor are aimed for storage, said Janice Nickel, research manager at the Cognitive Research Laboratory at HP Labs. “Then, we will look to move up from there.”

SK Hynix has developed an 8-Mbit test chip based on the memristor. HP itself has demonstrated a 54nm cross-bar structure. “The challenge is the integration of new materials,” Nickel said.

Others hope to ship ReRAMs sooner than later. Micron and Sony, for example, have been co-developing so-called Adaptive ReRAM for possible introduction in 2014. Adaptive ReRAMs are expected to have up to 8-Gbit capacities. Initially, Adaptive ReRAM is geared for cache module applications, said Keiichi Tsutsui, senior manager of advanced memory systems at Sony.

Like NAND, the industry is searching for a DRAM successor. When the DRAM runs out of gas, 3D-based Wide I/0 technology is one possible successor. In addition, Micron and Samsung are developing a 3D DRAM technology called the Hybrid Memory Cube (HMC).

There are several challenges to develop 3D DRAM. Longer term, STT-RAM may replace DRAM. Everspin, IBM-TDK, Qualcomm-TSMC, Samsung, Toshiba and others are working on STT-RAM.

STT-RAM makes use of a spin-transfer torque technology. This is an effect in which the orientation of a magnetic layer in a magnetic tunnel junction (MTJ) can be modified using a spin-polarized current. STT-RAMs are fast and non-volatile, but the challenges include scalability and unstable switching currents in the MTJ memory cell.

“It’s really too early for MRAM to replace DRAM,” said Phillip LoPresti, president and chief executive of Everspin Technologies, an MRAM supplier. “MRAM is always going to be behind in cost and density.”

For now, MRAM is geared for the embedded market. Everspin, for example, is shipping first-generation MRAMs based on a toggle-write technology, mainly for the battery-backed SRAM replacement market. In addition, Everspin is also readying the world’s first STT-RAM. In a slide at a recent event, Everspin called it a ST-RAM or ”SpinRAM.”

Using an alternate method for programming an MTJ element, ST-RAM is mainly geared to replace “battery-backed DRAM” or persistent RAM in hard drives and related storage applications, said Steffen Hellmold, vice president of marketing at Everspin. In an invited paper at the upcoming IEDM, Everspin will describe how they built the largest functional ST-MRAM circuit ever built, a 64-Mbit device with good electrical characteristics.

For main-memory in PCs and other systems, DRAM will remain the dominant technology for some time. “MRAM will not replace DRAM for at least the five years,” Hellmold said. “I am willing to place a bet on it.”

New memory phase
Like MRAM and ReRAM, PCM is in its infancy. PCM is difficult to scale and limited by the power required to change from the crystalline to the amorphous state. Researchers are looking at germanium telluride (GeTe) materials to overcome these limitations, said Jean-Luc Delcarri, general manager of Altatech, a subsidiary of Soitec.

Gary Kotzur, a distinguished engineer at PC maker Dell, said PCM has a potential place in online transaction processing (OLTP) systems. For OLTP, PCM needs to have “faster writes,” he said. “The power must be lower.”

Another application is online analytical processing, but for this application, “we need much higher densities,” he added.

By Mark LaPedus, SemiMD senior editor

The IC market is expected to bounce back in 2012, but capital spending is projected to see a steep double-digit drop this year, according to IC Insights Inc., a market research firm.

Bill McClean, president of IC Insights, predicted that the semiconductor market will hit $343.1 billion in 2012, up 7 percent from 2011. In 2011, the IC market reached $319.5 billion, up 2 percent over 2010, McClean said. “The growth of the IC industry in 2012 is forecast to be highly dependent on GDP growth,” he said during a chip forecast event in Sunnyvale, Calif.

Worldwide GDP is projected to hit 3.4 percent in 2012, compared to 3.3 percent in 2011. Hit by a major debt crisis in select countries, “Europe (is) still the wildcard,” he said. “China and India (are) expected to help drive growth.”

Electronic systems sales are projected to grow 7 percent in 2012, compared to 6 percent in 2011, according to IC Insights. “Good demand is expected for PCs, autos, etc.,” he said.

Capital spending is projected to hit $51.8 billion in 2012, down 16 percent from 2011, he said. In 2011, capital spending reached $61.9 billion, up 15 percent over 2010. The pure-play foundry market is expected to grow by 10 percent in 2012, up from 4 percent in 2011, he said.

In another major trend, flash memory is expected to overtake DRAM in terms of sales for 2012. And the DRAM market is due for another shakeout.

Sky is not falling

Overall, 2012 is expected to be a better year than 2011. “2011 was one of the strangest years that I have ever been involved in,” McClean said during the event. “None of the correlations worked.”

The various correlations or leading indicators – which are used by forecasters to look at the economy – simply fell flat. And there were several market “headwinds” for the worldwide semiconductor market and economy in 2011. For example, the DRAM market was a disaster. Chip inventories swelled. The unrest in the Middle East caused higher oil prices. There was the devastating earthquake in Japan. And there were natural disasters in the United States.

In the early part of 2012, DRAM prices have stabilized to a large degree. Companies that accumulated “inadvertent” IC inventory in the first half of 2011 are burning off their stock piles.

But there were other “headwinds” in 2011 — such as the European debt crisis and the floods in Thailand — which are spilling over into the first part of 2012, McClean said. “The first quarter (of 2012) is not going to be great,” he told SemiMD. “In the second half, we will see a snap back” in demand.

Based on IC Insights’ 7 percent growth forecast, IC sales are expected to fall by 2 percent in the first quarter in 2012, but will grow 5 percent in the second quarter, 11 percent in the third and 4 percent in the fourth, according to the firm.

The fastest growing IC markets in 2012 are expected to be NAND flash (15 percent growth), wireless (15 percent), 32-bit MCU (15 percent), MPU (14 percent), automotive-special purpose logic (11 percent), automotive-application specific analog (11 percent), display drivers (9 percent), PLDs (9 percent), 16-bit MCU (8 percent), wired telecom-special purpose logic (8 percent) and wired telecom-application specific analog (8 percent), according to IC Insights.

The NAND flash market is expected to hit $29.53 billion in 2012, up from $25.791 billion in 2011. Unit ASPs are projected to fall from $3.87 in 2011 to $3.64 in 2012, according to the firm.

The key drivers for NAND are smartphones, tablets, PC SSDs and embedded SSDs. The smartphone business is projected to grow from 475 million units in 2011 to 740 million units in 2012, according to the firm. Tablet PCs are projected to grow from 61 million units in 2011 to 105 million units in 2012, according to IC Insights.

DRAM shakeout

The DRAM market is still soft. The DRAM market is expected to hit $30.3 billion in 2012, down from 3 percent in 2011. In 2011, the DRAM market fell by a whopping 24 percent, according to the firm.

The DRAM market is ripe for more consolidation, according to Brian Matas, an analyst with IC Insights. A consolidation in the vendor base could help firm up average selling prices for DRAMs, he said.

The question is which vendors will be forced out of the business. Japan’s Elpida Memory Inc. is saddled with $6 billion in debt and has suffered losses of some $700 million from April to September of last year, he said.

Elpida is ‘’seeking $500 million in aid from customers,” he said, adding there were reports that Toshiba Corp. would possibly become a white knight for Elpida. Matas believes it’s unlikely Toshiba will buy Elpida, saying Toshiba would not want to step in the cyclical DRAM business.

The Taiwan vendors —ProMOS, Powerchip and Nanya — are also saddled with losses and may have to consolidate or go under. “Many (perhaps all) Taiwanese players will have a very difficult time trying to keep pace with the top group of DRAM suppliers. After investing heavily to bring 50nm — and 40nm — class processes to their 300mm wafer lines, Taiwan‐based suppliers have run short on cash and will have a hard time keeping pace with Samsung, Hynix, Micron, and Elpida when it comes to moving forward to the next process shrink,” according to IC Insights.

“At some point, even these major DRAM suppliers may have to join forces with other companies in order to afford upgrades or all new wafer fabs,” according to the firm.

By Mark LaPedus, SemiMD senior editor

Resistive RAMs (ReRAMs) are one of several next-generation candidates to succeed NAND flash or other memory types, but there are material, production and cost issues associated with the technology.

Elpida, Hynix, IMEC, Micron, Panasonic, Samsung, Sharp and others are working on ReRAM. In fact, Micron and Sony Corp. have quietly forged an alliance in ReRAM. “Micron and Sony have entered into a joint development program (JDP) to co-develop a new non-volatile memory focused on a conductive bridge-type random access memory, ReRAM,” according to a spokesman for Micron.

“Micron entered into the JDP with Sony as part of the company’s regular research and development efforts that involve, among other work, researching various emerging memory technologies,” according to the spokesman.

And this week, IMEC, Macronix, Panasonic and others presented ReRAM papers at IEDM. ReRAM is one of several “universal memory” technologies. Phase-change, MRAM, FRAM and others fall into that category. They are trying to replace DRAM, NAND, NOR or all three. But the problem is the next-generation memory types are still not in production despite years of R&D. They are expensive to make and difficult to scale.

ReRAM is a product that holds potential to replace NAND. “Current charge storage based flash memory technologies are believed to face scaling limitations beyond 18nm,” according to IMEC. “To overcome these, a variety of innovative cell and memory concepts are investigated worldwide. One of the most promising memory concepts is the resistive RAM or RRAM. It is based on the electronic switching of a resistor element material between two stable (low/high) resistive states. The major strengths of RRAM technology are its potential density and speed.”

There are challenges. “However, even if many materials reported to date exhibit good resistive switching properties, the success of a future RRAM technology depends critically on integrability into a conventional, underlying baseline technology, with cost as a key factor,” according to IMEC.

At IEDM, IMEC presented the world’s smallest, fully-functional HfO2-based RRAM cell, with an area of less than 10x10nm². Imec’s RRAM cell features a novel Hf/HfOx resistive element stack. It couples a cell area of less than 10x10nm² with a reliability endurance of more than 109 cycles.

The cell has fast nanosecond-range on/off switching times at low-voltages. It has a large resistive window (>50) and shows no closure of the on/off window after functioning at 200°C for 30 hours. The device even remained operating failure-free functioning for 30 hours with a thermal stress of 250°C. The switching energy per bit is below 0.1pJ, and AC operating voltages are well below 3V. With these characteristics, IMEC’s cell meets the major requirements for device-level nonvolatile memory.

These results were obtained in cooperation with IMEC’s key partners in its core CMOS programs Globalfoundries, Intel, Micron, Panasonic, Samsung, TSMC, Elpida, Hynix, Fujitsu and Sony.

Another IEDM paper was given by the Nanyang Technological University, Institute of Microelectronics, Peking University, A*STAR, National University of Singapore, GlobalFoundries, Soitec and Fudan University: “We report a high performance, forming-free and self-rectifying unipolar HfOx based RRAM fabricated by fab-available materials. Highlight of the demonstrated RRAM include 1) CMOS technology friendly materials and process, 2) excellent self-rectifying behavior in LRS (>103 @ 1 V), 3) forming-free unipolar resistive switching, 4) wide read-out margin for high density cross-point memory devices (number of word-line >106 for worst case condition).”

The big memory houses are also exploring ReRAM. Last year, for example, Hynix Semiconductor Inc. entered into a joint development agreement with HP to develop memristor technology in the form of ReRAM. The two companies will jointly develop new materials and process integration to deliver ReRAM to market by transferring the memristor technology from research to commercial development. Hynix will implement the technology in its R&D fab.

The memristor, short for “memory resistor,” requires less energy to operate, can retain information even when power is off, and is faster than present solid-state storage technologies.

Meanwhile, Micron, along with Sony, are exploring ReRAM. The move into ReRAM represents Micron’s latest effort in next-generation memories. The company entered the phase-change memory race, when it recently acquired Numonyx, a supplier of NOR flash devices.

Numoynx, formerly the NOR flash units of Intel and STMicroelectronics, was developing phase-change memory. Samsung Electronics Co. Ltd. is also separately developing phase-change memory.

Earlier this year, Unity Semiconductor Corp. entered into a joint development agreement with Micron. Micron invested in Unity. For the last eight years, Unity has been developing CMOx, a next-generation memory type. CMOx is designed to scale beyond the limitations of the legacy transistor technology currently used in NAND flash memory.

More recently, Micron rolled out the Hybrid Memory Cube (HMC), a 3D DRAM technology for servers and networking systems. In November, Micron and Singapore’s A*STAR Data Storage Institute (DSI) jointly announced that the two companies entered into an agreement to collaborate on the development of spin transfer torque magnetic random access memory (STT-MRAM), a promising alternative non-volatile memory technology for next-generation storage.

As part of the collaboration, Micron and DSI will invest in joint research to develop high-density STT-MRAM devices during the next three years. Meanwhile, Samsung and Hynix are developing STT-MRAM. In fact, Samsung recently bought Grandis, a developer of STT-MRAM. Toshiba and others are also exploring the technology.

Micron is also looking at all next-generation memories. “Considering Micron’s previous high visibility acquisition of Intel’s phase change memory (PCM) program, these new announcement are likely part of the regular activity of all memory companies to keep abreast of any potentially critical new technologies,” said Bob Merritt, an analyst with Convergent Semicondctors LLC, in a blog.

“However, Micron already has a long history in ReRAM that can be traced back to their 2002 licensing of Axon Technologies’ Programmable Metallization Cell (PMC) technology,” he said.

“While the public perception of memory technologies tends to assume that no new technology will be acceptable until it reaches the same cost per bit of DRAM or NAND, we believe that the continued interest in these new and emerging technologies is based on finding other market entry points and an expectation of providing high value to new applications,” he added.

Axon Technologies Corp. has also been trying to commercialize PMC. Adesto Technologies, which is backed by Applied Materials and others, is developing conductive bridge RAM (CBRAM) memory technology. CBRAM was originally developed at Arizona State University and is also known as PMC.

In response to growing demand in the semiconductor industry, Honeywell Electronic Materials said it will more than double its refining and casting capacity for high-purity copper and tin at its Spokane, Wash.-based facility.

The first phase of the capacity expansion will be completed in the first quarter of next year, with the second phase in place by the middle of next year.

The company did not elaborate. “We cannot elaborate in terms of a specific unit of measurement for this expansion because that information is competitive and proprietary,’’ a Honeywell spokesman said in an e-mail. Honeywell is a supplier of metals to the semiconductor industry.

Copper and tin refining take place in its Spokane plant. “Spokane is primary for casting, too; but we also have back-up casting capabilities in our Fombell, Penn. facility,’’ the spokesman said.

Demand for copper has been growing as new advanced chip designs continue to require high-purity copper. Additional industry growth has come as memory manufacturers transition from aluminum to copper. The use of copper and tin for advanced chip packaging applications is similarly on the rise.

One of the benefits of using copper in integrated circuits is its ability to provide a lower resistivity than aluminum, which has been widely used for interconnects in the industry. Copper has also been embraced for chip packaging applications due to the rapidly increasing costs associated with gold, which is the current industry standard.

Tin has been used increasingly as an alternative to lead for advanced chip packaging applications, providing an option for customers who must comply with regulations against lead-based materials.

– Mark Lapedus

By Ed Sperling

Future memory technology inside of mobile devices will use less power and run faster at each rev of Moore’s Law, but that technology also will look different, use different materials, and will be manufactured with different equipment, processes and technologies.

While this technology will owe its heritage to research and testing of the past few decades, the differences are expected to be dramatic. A panel of vendors, their customers and researchers took a deep dive into the research that will change the memory market of the future at an IEEE International Memory Workshop held Monday in Monterey, Calif. The discussion, chaired by Raman Achutharaman, VP of strategy and marketing for Applied Materials’ silicon systems’ group, pointed to some interesting research, developments and future standards.

What’s next?
Laith Altimime, Imec’s program director for CMOS process technology, said that over the next decade memory makers will require new materials (graphene and/or carbon nanotubes, for example); new techniques, including EUV lithography, air gap insulation and 3D stacking with through-silicon vias; and new structures, including hybrid tunneling field effect transistors (TFETs), VFETs and TANOS cells.

“New materials and device architectures are the key,” said Altimime, noting that 3D stacking will “take over everything in its path.” That includes resistive RAM (RRAM), a non-volatile type of memory now in the research phase that relies on current applied to a filament; 1T-RAM, a higher-density version of RAM; and spin-transfer torque RAM, which changes the magnetization on a thin magnetic layer by running a spin-polarized current across it.

Altimime noted that scaling beyond 16nm most likely will require 3D cell architectures. He said the base material will still be CMOS, but it also will include higher-k dielectrics, metals, and stack engineering.

NAND changes
Sung-Kye Park, of Hynix’s Memory R&D Division, noted that NAND will require a slew of changes to decrease charge loss and increase e-field retention. Those changes will include everything from air gap technology to an increased doping of the control gate. He expects new structures and new materials to start hitting the market within two years.

“3D flash is a possible candidate,” Park said, pointing to Toshiba’s pipe-shaped Bit Cost Scalable technology, Samsung’s Terabit Cell Array Transistor (TCAT), Hynix’s 3D-FG and hybrid chips. But he noted there also are potential hurdles in areas such as process integration, particularly in the areas of multistack deposition and word-line formation.

DRAM shift
Joo Young Lee, strategic planning manager at Samsung, said the goal for DRAM is still a 35% cost reduction each year, but to achieve that will require moving to the next process nodes. DRAM is currently approaching 30nm, he said. He expects it to hit 25nm by 2015 and 14nm by 2020, with DDR4 hitting mainstream in 2013. EUV will be required at 14nm, he said.

Reaching those advanced nodes will require changes in some of DRAM’s basic structures—cell capacitors, cell array transistors and cell node contacts, all of which will need to be re-engineered.

Patterning issues
Yoshitaka Tsunashima, a leading researcher at Toshiba, said his company’s NAND technology already requires double patterning. At 14nm, double patterning and EUV both will be required.

EUV has its own issues, of course—light source performance, mask defect control, optical performance, mask data preparation, and resist performance. But he noted that 11 companies are now working to solve those issues as part of the EUV Infrastructure Development Engineering Center (EIDEC).

“The other way we can get there is 3D NAND,” he said, noting that either approach—lithography or stacking—or both will help reduce bit costs. He said that technology also can be extended to RRAM, organic memory and MEMS memory.

Customer view
Nokia’s Matti Floman said the ideal solution would be universal memory. But given that is an unlikely development, what’s needed from his company’s standpoint are higher bandwidth for DRAM and non-volatile memory, new package solutions, lower power consumption, higher temperature tolerance, pre-developed scalable modules, and standard solutions.

He noted that Wide I/O is seen as a strong candidate for replacing DDR2 and DDR3 in high-end products. Mass memory, meanwhile, is moving toward NAND and embedded MultiMediaCard (eMMC).

by Ed Korczynski

Resistance-change Random Access Memory (RRAM or ReRAM) devices continue to be developed at labs and fabs around the world, as seen by more than 40 papers at the spring Materials Research Society (MRS) spring meeting which was held April 25-29 in San Francisco, California. RRAMs are based on resistive switching in metal oxides, such as titantia and niobia, that show memristor properties. With single-digit nanosecond switching-speeds and 10-year non-volatile data retention, RRAMs may represent the future of solid-state memory after DRAM and Flash devices eventually reach scaling limits below 22nm half-pitch.

Technically, the other devices competing with RRAM for the future of memory are themselves based on changes in resistance. Phase-change memory (PCM) using GST material switches between low- and high-resistance states, but requires large drive currents to heat the material to effect the phase-change. Spin-transfer-torque RAM (STT-RAM) is also read as a change in resistance, but the cell size is relatively large. RRAM devices built using cross-point arrays could provide the smallest, fastest, leanest, and cheapest non-volatile memory chips.

Between oral presentations and posters, the Spring 2011 MRS Meeting showed many different groups using different switching materials for RRAMs:

8 – TiO

7 – NiO

6 – Zn0:metal

4 – SiO:Cu

3 – HfO:metal

3 – TMO:metal

3 – polymers

2 – TaO

2 – SrTiO

1 – CuO

1 – HfSiO

1 – WO

1 – solid electrolyte

42 + 11 more novel materials in session Q10

= 53 total RRAM presentations.

HP Labs RRAM Update

Stan Williams’ group at HP Labs has led the world in memristor and RRAM R&D using the titania family of materials as the switch since 2006. They claim that their champion device switches in <2ns, and has world-record endurance of >1.2E10 cycles. Stan Williams provided a keynote address to an MRS workshop last year, in which he explained how his group finally discovered that the conducting channel consists of a 1-2nm thin TiO2 tunnel barrier adjacent to a ~30nm thick “magneli-phase” Ti4O7 layer. Modulating the width of the tunnel barrier through diffusion of oxygen-vacancies controls the electrical resistance of the stack.

This year, HP Labs updated their titania work by reporting on two different electroforming mechanisms seen in the same 50nm × 50nm crossbar memristive device. A “soft” electroforming step uses <140µAmp at ~5V to create a high-resistance mode, while a “hard” electroforming step uses ~250µAmp at ~9V to create a low resistance mode. The two switching modes possessed opposite switching polarities that shared a metastable intermediate resistance state. The two modes can be explained by two switching layers at the top- and bottom-electrode interfaces:

• intermediate state, the bottom layer is ON with conducting channels made of both oxygen-vacancies and charge-traps, while the top layer consists of a tunnel gap;
• OFF state, both layers consist of tunnel gaps; and
• ON state, the top layer is ON with conducting channels made of oxygen-vacancies, while the bottom layer consists of a tunnel gap.

J. Joshua (Jianhua) Yang, provided an update on HP Labs’s RRAM work by surprisingly stating that titanium-oxides have stability issues which may limit device lifetimes, but that tantalum-oxides are free of such issue. The titania family seems to show issues getting beyond 100-1000 cycles, due to excessive heating inside the switch material due to the tendency to apply overvoltage. The two phases of titania will react with each other during heating, so the ON/OFF resistance differences are not so stable. “You need stability, and larger oxygen stability in the materials,” explained Yang. Presumably, the world-record cycling performance using titania was achieved using careful limits on overvoltage.

To improve lifetime with overvoltage margin, HP now uses a tantalum-oxide switching layer, a platinum bottom-electrode, and a tantalum top-electrode. The company claims that this system should be scalable to <5nm, the switching speed is merely 5ns, and the resistance state should be stable for 10 years. TaOx as deposited is amorphous, and even after heating steps it may retain some amorphous character.

RRAM Electroforming Avoidance

The ability to create functional RRAMs without electroforming would provide a significant cost and yield advantage in manufacturing. Though there is still debate as to the exact nature of the solid-state ion-diffusion mechanism(s) responsible for the change in resistance, it is clear that proper stacks of nano-scale oxides and sub-oxides are needed. Consequently, once trial-and-error has identified an ideal materials stack, it is likely that a wafer-scale process flow will be found to create the desired stack without the need for electroforming. For example, annealing in a reducing ambient or solid-phase gettering techniques may be used to adjust the stoichiometry of thin-films.

Using a tungsten-plug from a 90nm node DRAM process flow as one electrode, researchers from Research Center Juelich (with funding from Intel) used TiO2 thickness of 25nm and a Pt/Ti top electrode to make inherently electroforming-free RRAMs (Session Q8.4). Initially the devices were found to be in an intermediate state, and can be SET with positive bias voltage to the low resistance state (LRS). Without bias the intermediate state undergoes a RESET process to a high resistance state (HRS). Under negative voltage bias both processes can be reversed and the device returns into the intermediate state. This flipping of the SET and RESET process from positive to negative bias voltage polarity and vice versa can repeatedly be adjusted in one device. This versatile switching scenario is possible due to the use of the low-workfunction Ti and W electrodes which result in low barriers to the oxide.

The Juelich process flow is as follows:

1. Plasma etch to clean the W plug,
2. Reactive sputter TiO2 (300W, 46sccm AR, 17 sccm O2), and
3. PVD of top-electrode.

The top-electrode was 30nm Pt with an optional 5nm layer of Ti or W below. “As long as there is a Pt/TiO2 interface we need forming,” explained Rainer Bruchhaus of Juelich. However, when using either W or Ti as a barrier between the Pt and TiO2 (while maintaining W as bottom electrode) they see no need for electroforming. In all cases, the voltage range is limited to +- 1V.

RRAM scalability

Much of the global interest in RRAM structures is due to the ability of cross-point memory architectures to be shrunk far more easily than other device structures. The process flow to make cross-point arrays is particularly attractive from an overlay perspective, since the top- and bottom-electrodes are perpendicular to each other and the switching material is patterned along with the top-electrode.

The world record for the smallest resistive memory element is currently held by the National Nano Device Laboratories (NNDL) in Taiwan, which showed a 9nm half-pitch functional RRAM at IEDM last December (Paper #19.1, “9nm Half-Pitch Functional Resistive Memory Cell with <1 µA Programming Current Using Thermally Oxidized Sub-Stochiometric WO_x Film,” C. Ho et al, National Nano Device Laboratories, Taiwan/University of California at Berkeley). It features the lowest reported programming current to date of just <1µA using tungsten-oxide, compared to ~20mA for phase-change memories. The device was built using nano-injection lithography which employs a chemical reaction activated with a finely controlled electron beam to deposit a hard-mask for etching, but could have used Nano-imprint Lithography (NIL) or other patterning to form the array.

For more details on the physics of these devices, Applied Physics A, Vol.A102, No.4 is a special issue on “Memristive and Resistive Devices and Systems,” and is now available for free download as individual PDFs.