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Posts Tagged ‘memory’

3D-NAND Deposition and Etch Integration

Thursday, September 1st, 2016

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By Ed Korczynski, Sr. Technical Editor

3D-NAND chips are in production or pilot-line manufacturing at all major memory manufacturers, and they are expected to rapidly replace most 2D-NAND chips in most applications due to lower costs and greater reliability. Unlike 2D-NAND which was enabled by lithography, 3D-NAND is deposition and etch enabled. “With 3D-NAND you’re talking about 40nm devices, while the most advanced 2D-NAND is running out of steam due to the limited countable number of stored electrons-per-cell, and in terms of the repeatability due to parasitics between adjacent cells,” reminded Harmeet Singh, corporate vice president of Lam Research in an exclusive interview with SemiMD to discuss the company’s presentation at the Flash Memory Summit 2016.

“We’re in an era where deposition and etch uniquely define the customer roadmap,” said Singh,“and we are the leading supplier in 3D-NAND deposition and etch.” Though each NAND manufacturer has different terminology for their unique 3D variant, from a manufacturing process integration perspective they all share similar challenges in the following simplified process sequences:

1)    Deposition of 32-64 pairs of blanket “mold stack” thin-films,

2)    Word-line hole etch through all layers and selective fill of NAND cell materials, and

3)    Formation of “staircase” contacts to each cell layer.

Each of these unique process modules is needed to form the 3D arrays of NVM cells.

For the “mold stack” deposition of blanket alternating layers, it is vital for the blanket PECVD to be defect-free since any defects are mirrored and magnified in upper-layers. All layers must also be stress-free since the stress in each deposited layer accumulates as strain in the underlying silicon wafer, and with over 32 layers the additive strain can easily warp wafers so much that lithographic overlay mismatch induces significant yield loss. Controlled-stress backside thin-film depositions can also be used to balance the stress of front-side films.

Hole Etch

“The difficult etch of the hole, the materials are different so the challenges is different,” commented Singh about the different types of 3D-NAND now being manufactured by leading fabs. “During this conference, one of our customer presented that they do not see the hole diameters shrinking, so at this point it appears to us that shrinking hole diameters will not happen until after the stacking in z-dimension reaches some limit.”

Tri-Layer Resist (TLR) stacks for the hole patterning allow for the amorphous carbon hardmask material to be tuned for maximum etch resistance without having to compromise the resolution of the photo-active layer needed for patterning. Carbon mask is over 3 microns thick and carbon-etching is usually responsive to temperature, so Lam’s latest wafer-chuck for etching features >100 temperature control zones. “This is an example of where Lam is using it’s processes expertise to optimize both the hardmask etch as well as the actual hole etch,” explained Singh.

Staircase Etch

The Figure shows a simplified cross-sectional schematic of how the unique “staircase” wordline contacts are cost-effectively manufactured. The established process of record (POR) for forming the “stairs” uses a single mask exposure of thick KrF photoresist—at 248nm wavelength—to etch 8 sets of stairs controlled by a precise resist trim. The trimming step controls the location of the steps such that they align with the contact mask, and so must be tightly controlled to minimize any misalignment yield loss.

A) Simplified cross-sectional schematic of the staircase etch for 3D-NAND contacts using thick photoresist, B) which allows for controlled resist trimming to expose the next “stair” such that C) successive trimming creates 8-16 steps from a single initial photomask exposure. (Source: Ed Korczynski)

Lam is working on ways to tighten the trimming etch uniformity such that 16 sets of stairs can be repeatably etched from a single KrF mask exposure. Halving the relative rate of vertical etch to lateral etch of the KrF resist allows for the same resist thickness to be used for double the number of etches, saving lithography cost. “We see an amazing future ahead because we are just at the beginning of this technology,” commented Singh.

—E.K.

Fab Facilities Data and Defectivity

Monday, August 1st, 2016

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By Ed Korczynski, Sr. Technical Editor

In-the-know attendees at SEMICON West at a Thursday morning working breakfast heard from executives representing the world’s leading memory fabs discuss manufacturing challenges at the 4th annual Entegris Yield Forum. Among the excellent presenters was Norm Armour, managing director worldwide facilities and corporate EHSS of Micron. Armour has been responsible for some of the most famous fabs in the world, including the Malta, New York logic fab of GlobalFoundries, and AMD’s Fab25 in Austin, Texas. He discussed how facilities systems effect yield and parametric control in the fab.

Just recently, his organization within Micron broke records working with M&W on the new flagship Fab 10X in Singapore—now running 3D-NAND—by going from ground-breaking to first-tool-in in less than 12 months, followed by over 400 tools installed in 3 months. “The devil is in the details across the board, especially for 20nm and below,” declared Armour. “Fabs are delicate ecosystems. I’ll give a few examples from a high-volume fab of things that you would never expect to see, of component-level failures that caused major yield crashes.”

Ultra-Pure Water (UPW)

Ultra-Pure Water (UPW) is critical for IC fab processes including cleaning, etching, CMP, and immersion lithography, and contamination specs are now at the part-per-billion (ppb) or part-per-trillion (ppt) levels. Use of online monitoring is mandatory to mitigate risk of contamination. International Technology Roadmap for Semiconductors (ITRS) guidelines for UPW quality (minimum acceptable standard) include the following critical parameters:

  • Resistivity @ 25C >18.0 Mohm-cm,
  • TOC <1.0 ppb,
  • Particles/ml < 0.3 @ 0.05 um, and
  • Bacteria by culture 1000 ml <1.

In one case associated with a gate cleaning tool, elevated levels of zinc were detected with lots that had passed through one particular tool for a variation on a classic SC1 wet clean. High-purity chemistries were eliminated as sources based on analytical testing, so the root-cause analysis shifted to to the UPW system as a possible source. Then statistical analysis could show a positive correlation between UPW supply lines equipped with pressure regulators and the zinc exposure. The pressure regulator vendor confirmed use of zinc-oxide and zinc-stearate as part of the assembly process of the pressure regulator. “It was really a curing agent for an elastomer diaphragm that caused the contamination of multiple lots,” confided Armour.

UPW pressure regulators are just one of many components used in facilities builds that can significantly degrade fab yield. It is critical to implement a rigorous component testing and qualification process prior to component installation and widespread use. “Don’t take anything for granted,” advised Armour. “Things like UPW regulators have a first-order impact upon yield and they need to be characterized carefully, especially during new fab construction and fit up.”

Photoresist filtration

Photoresist filtration has always been important to ensure high yield in manufacturing, but it has become ultra-critical for lithography at the 20nm node and below. Dependable filtration is particularly important because industry lacks in-line monitoring technology capable of detecting particles in the range below ~40nm.

Micron tried using filters with 50nm pore diameters for a 20nm node process…and saw excessive yield losses along with extreme yield variability. “We characterized pressure-drop as a function of flow-rate, and looked at various filter performances for both 20nm and 40nm particles,” explained Armour. “We implemented a new filter, and lo and behold saw a step function increase in our yields. Defect densities dropped dramatically.” Tracking the yields over time showed that the variability was significantly reduced around the higher yield-entitlement level.

Airborne Molecular Contamination (AMC)

Airborne Molecular Contamination (AMC) is ‘public enemy number one’ in 20nm-node and below fabs around the world. “In one case there were forrest fires in Sumatra and the smoke was going into the atmosphere and actually went into our air intakes in a high volume fab in Taiwan thousands of miles away, and we saw a spike in hydrogen-sulfide,” confided Armour. “It increased our copper CMP defects, due to copper migration. After we installed higher-quality AMC filters for the make-up air units we saw dramatic improvement in copper defects. So what is most important is that you have real-time on-line monitoring of AMC levels.”

Building collaborative relationships with vendors is critical for troubleshooting component issues and improving component quality. “Partnering with suppliers like Entegris is absolutely essential,” continued Armour. “On AMCs for example, we have had a very close partnership that developed out of a team working together at our Inotera fab in Taiwan. There are thousands of important technologies that we need to leverage now to guarantee high yields in leading-node fabs.” The Figure shows just some of the AMCs that must be monitored in real-time.

Big Data

The only way to manage all of this complexity is with “Big Data” and in addition to primary process parameter that must be tracked there are many essential facilities inputs to analytics:

  • Environmental Parameters – temperature, humidity, pressure, particle count, AMCs, etc.
  • Equipment Parameters – run state, motor current, vibration, valve position, etc.
  • Effluent Parameters – cooling water, vacuum, UPW, chemicals, slurries, gases, etc.

“Conventional wisdom is that process tools create 90% of your defect density loss, but that’s changing toward facilities now,” said Armour. “So why not apply the same methodologies within facilities that we do in the fab?” SPC is after-the-fact reactive, while APC is real-time fault detection on input variables, including such parameters as vibration or flow-rate of a pump.

“Never enough data,” enthused Armour. “In terms of monitoring input variables, we do this through the PLCs and basically use SCADA to do the fault-detection interdiction on the critical input variables. This has been proven to be highly effective, providing a lot of protection, and letting me sleep better at night.”

Micron also uses these data to provide site-to-site comparisons. “We basically drive our laggard sites to meet our world-class sites in terms of reducing variation on facility input variables,” explained Armour. “We’re improving our forecasting as a result of this capability, and ultimately protecting our fab yields. Again, the last thing a fab manager wants to see is facilities causing yield loss and variation.”

—E.K.

Solid State Watch: May 13-19, 2016

Monday, May 23rd, 2016
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Solid State Watch: March 20-26, 2015

Thursday, March 26th, 2015
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Research Alert: August 12, 2014

Tuesday, August 12th, 2014

SRC, UC Davis explore new materials and device structures to develop next-generation “Race Track Memory” technologies

University of California, Davis researchers sponsored by Semiconductor Research Corporation (SRC), a university-research consortium for semiconductors and related technologies, are exploring new materials and device structures to develop next-generation memory technologies.

The research promises to help data storage companies advance their technologies with predicted benefits including increased speed, lower costs, higher capacity, more reliability and improved energy efficiency compared to today’s magnetic hard disk drive and solid state random access memory (RAM) solutions.

Conducted by UC Davis’ Takamura Research Group that has extensive experience in the growth and characterization of complex oxide thin films, heterostructures and nanostructures, the research involves leveraging complex oxides to manipulate magnetic domain walls within the wires of semiconductor memory devices at nanoscale dimensions. This work utilized sophisticated facilities available through the network of Department of Energy-funded national laboratories at the Center for Nanophase Materials Sciences, Oak Ridge National Laboratory and the Advanced Light Source, Lawrence Berkeley National Laboratory.

“We were inspired by the ‘Race Track Memory’ developed at IBM and believe complex oxides have the potential to provide additional degrees of freedom that may enable more efficient and reliable manipulation of magnetic domain walls,” said Yayoi Takamura, Associate Professor, Department of Chemical Engineering and Materials Science, UC Davis.

Existing magnetic hard disk drive and solid state RAM solutions store data either based on the magnetic or electronic state of the storage medium. Hard disk drives provide a lower cost solution for ultra-dense storage, but are relatively slow and suffer reliability issues due to the movement of mechanical parts. Solid state solutions, such as Flash memory for long-term storage and DRAM for short-term storage, offer higher access speeds, but can store fewer bits per unit area and are significantly more costly per bit of data stored.

An alternative technology that may address both of these shortcomings is based on the manipulation of magnetic domain walls, regions that separate two magnetic regions. This technology, originally proposed by IBM researchers and named ‘Race Track Memory,’ is where the UC Davis work picked up.

Notre Dame paper offers insights into a new class of semiconducting materials

A new paper by University of Notre Dame researchers describes their investigations of the fundamental optical properties of a new class of semiconducting materials known as organic-inorganic “hybrid” perovskites.

The research was conducted at the Notre Dame Radiation Laboratory by Joseph Manser, a doctoral student in chemical and biomolecular engineering, under the direction of Prashant Kamat, Rev. John A. Zahm Professor of Science. The findings appear in a paper in the August 10 edition of the journal Nature Photonics.

The term “perovskites” refers to the structural order these materials adopt upon drying and assembling in the solid state.

“Hybrid perovskites have recently demonstrated exceptional performance in solid-state thin film solar cells, with light-to-electricity conversion efficiencies approaching nearly 20 percent,” Manser said. “Though currently only at the laboratory scale, this efficiency rivals that of commercial solar cells based on polycrystalline silicon. More importantly, these materials are extremely easy and cheap to process, with much of the device fabrication carried out using coating and or printing techniques that are amenable to mass production. This is in stark contrast to most commercial photovoltaic technologies that require extremely high purity materials, especially for silicon solar cells, and energy-intensive, high-temperature processing.”

Manser points out that although the performance of perovskite solar cells has risen dramatically in only a few short years, the scientific community does not yet fully know how these unique materials interact with light on a fundamental level.

Manser and Kamat used a powerful technique known as “transient absorption pump-probe spectroscopy” to examine the events that occur trillions of a second after light absorption in the hybrid methylammonium lead iodide, a relevant material for solar applications. They analyzed both the relaxation pathway and spectral broadening in photoexcited hybrid methylammonium lead iodide and found that the excited state is primarily composed of separate and distinct electrons and holes known as “free carriers.”

“The fact that these separated species are present intrinsically in photoexcited hybrid methylammonium lead iodide provides a vital insight into the basic operation of perovskite solar cells,” Manser said. “Since the electron and hole are equal and opposite in charge, they often exist in a bound or unseparated form known as an ‘exciton.’ Most next-generation’ photovoltaics based on low-temperature, solution-processable materials are unable to perform the function of separating these bound species without intimate contact with another material that can extract one of the charges. ”

This separation process siphons energy within the light absorbing layer and restricts the device architecture to one of highly interfacial surface area. As a result, the overall effectiveness of the solar cell is reduced.

Pairing old technologies with new for next-generation electronic devices

UCL scientists have discovered a new method to efficiently generate and control currents based on the magnetic nature of electrons in semiconducting materials, offering a radical way to develop a new generation of electronic devices.

One promising approach to developing new technologies is to exploit the electron’s tiny magnetic moment, or ‘spin’. Electrons have two properties – charge and spin – and although current technologies use charge, it is thought that spin-based technologies have the potential to outperform the ‘charge’-based technology of semiconductors for the storage and process of information.

In order to utilise electron spins for electronics, or ‘spintronics’, the method of electrically generating and detecting spins needs to be efficient so the devices can process the spin information with low-power consumption. One way to achieve this is by the spin-Hall effect, which is being researched by scientists who are keen to understand the mechanisms of the effect, but also which materials optimise its efficiency. If research into this effect is successful, it will open the door to new technologies.

The spin-Hall effect helps generate ‘spin currents’ which enable spin information transfer without the flow of electric charge currents. Unlike other concepts that harness electrons, spin current can transfer information without causing heat from the electric charge, which is a serious problem for current semiconductor devices. Effective use of spins generated by the spin-Hall effect can also revolutionise spin-based memory applications.

The study published in Nature Materials shows how applying an electric field in a common semiconductor material can dramatically increase the efficiency of the spin-Hall effect which is key for generating and detecting spin from an electrical input.

The scientists reported a 40-times-larger effect than previously achieved in semiconductor materials, with the largest value measured comparable to a record high value of the spin-Hall effect observed in heavy metals such as Platinum. This demonstrates that future spintronics might not need to rely on expensive, rare, heavy metals for efficiency, but relatively cheap materials can be used to process spin information with low-power consumption.

As there are limited amounts of natural resources in the earth and prices of materials are progressively going up, scientists are looking for more accessible materials with which to develop future sustainable technologies, potentially based on electron spin rather than charge. Added to this, the miniaturization approach of current semiconductor technology will see a point when the trend, predicted by Moore’s law, will come to an end because transistors are as small as atoms and cannot be shrunk any further. To address this, fundamentally new concepts for electronics will be needed to produce commercially viable alternatives which meet demands for ever-growing computing power.

3D memory for future nanoelectronic systems

Wednesday, June 18th, 2014

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By Ed Korczynski, Sr. Technical Editor

The future of 3D memory will be in application-specific packages and systems. That is how innovation continues when simple 2D scaling reaches atomic-limits, and deep work on applications is now part of what global research and development (R&D) consortium Imec does. Imec is now 30 years old, and the annual Imec Technology Forum held in the first week of June in Brussels, Belgium included fun birthday celebrations and very serious discussions of the detailed R&D needed to push nanoelectronics systems into health-care, energy, and communications markets.

3D memory will generally cost more than 2D memory, so generally a system must demand high speed or small size to mandate 3D. Communications devices and cloud servers need high speed memory. Mobile and portable personalized health monitors need low power memory. In most cases, the optimum solution does not necessarily need more bits, but perhaps faster bits or more reliable bits. This is why the Hybrid Memory Cube (HMC) provides >160Gb/sec data transfer with Through-Silicon Vias (TSV) through 3D stacked DRAM layers.

“We’re not adding 70-80% more bits like we used to per generation, or even the 40% recently,” explained Mark Durcan, chief executive officer of Micron Technology. “DRAM bits will only grow at the low to mid-20%.” With those numbers come hopes of more stability and less volatility in the DRAM business. Likewise, despite the bit growth rates of the recent past, NAND is moving to 30-40%  bit-increase per new ‘generation.’

“Moore’s Law is not over, it’s just slowing,” declared Durcan. “With NAND, we’re moving from planar to 3D, and the innovation is that there are different ways of doing 3D.” Figure 1 shows the six different options that Micron defines for 3D NAND. Micron plans for future success in the memory business to be not just about bit-growth, but about application-specific memory solutions.

Fig. 1: Different options for Vertical NAND (VNAND) Flash memory design, showing cell layouts and key specifications. (Source: Micron Technology)

E. S. Jung, executive vice president Samsung Electronics, presented an overview of how “Samsung’s Breaking the Limits of Semiconductor Technology for the Future” at the Imec forum. Samsung Semiconductor announced it’s first DRAM product in 1984, and has been improving it’s capabilities in design and manufacturing ever since. Samsung also sees the future of memory chips as part of application-specific systems, and suggests that all of the innovation in end-products we envision for the future cannot occur without semiconductor memory.

Samsung’s world leading 3D vertical-NAND (VNAND) chips are based on simultaneous innovation in three different aspects of materials and design:

1)    Material changed from floating-gate,

2)    Rotated structure from horizontal to vertical (and use Gate All Around), and

3)    Stacked layers.

To accomplish these results, partners were needed from OEM and specialty-materials suppliers during the R&D of the special new hard-mask process needed to be able to form 2.5B vias with extremely high aspect-ratios.

Rick Gottscho, executive vice president of the global products group Lam Research Corp., in an exclusive interview with SST/SemiMD, explained that with proper control of hardmask deposition and etch processes the inherent line-edge-roughness (LER) of photoresist (PR) can be reduced. This sort of integrated process module can be developed independently by an OEM like Lam Research, but proving it in a device structure with other complex materials interactions requires collaboration with other leading researchers, and so Lam Research is now part of a new ‘Supplier Hub’ relationship at Imec.

Luc Van den hove, president and chief executive officer of Imec, commented, “we have been working with equipment and materials suppliers form the beginning, but we’re upgrading into this new ‘Supplier Hub.’ In the past most of the development occurred at the suppliers’ facilities and then results moved to Imec. Last year we announced a new joint ‘patterning center’ with ASML, and they’re transferring about one hundred people from Leuven. Today we announced a major collaboration with Lam Research. This is not a new relationship, since we’ve been working with Lam for over 20 years, but we’re stepping it up to a new level.”

Commitment, competence, and compromise are all vital to functional collaboration according to Aart J. de Geus, chairman and co-chief executive officer of Synopsys. Since he has long lead a major electronic design automation (EDA) company, de Geus has seen electronics industry trends over the 30 years that Imec has been running. Today’s advanced systems designs require coordination among many different players within the electronics industry ecosystem (Figure 2), with EDA and manufacturing R&D holding the center of innovation.

Fig. 2: Semiconductor manufacturing and design drive technology innovation throughout the global electronics industry. (Source: Synopsys)

“The complexity of what is being built is so high that the guarantee that what has been built will work is a challenge,” cautioned de Geus. Complexity in systems is a multiplicative function of the number of components, not a simple summation. Consequently, design verification is the greatest challenge for complex System-on-Chips (SoC). Faster simulation has always been the way to speed up verification, and future hardware and software need co-optimization. “How do you debug this, because that is 70% of the design time today when working with SoCs containing re-used IP? This will be one of the limiters in terms of product schedules,” advised de Geus.

Whether HMC stacks of DRAM, VNAND, or newer memory technologies such as spintronics or Resistive RAM (RRAM), nanoscale electronic systems will use 3D memories to reduce volume and signal delays. “Today we’re investigating all of the technologies needed to advance IC manufacturing below 10nm,” said Van den hove. The future of 3D memories will be complex, but industry R&D collaboration is preparing the foundation to be able to build such complex structures.

DISCLAIMER:  Ed Korczynski has or had a consulting relationship with Lam Research.

Research Alert: Feb. 18, 2014

Tuesday, February 18th, 2014

Breakthrough development of flexible 1D-1R memory cell array

With the introduction of curved smartphones, flexible electronic goods are gradually moving to the center stages of various markets. Flexible display technology is the culmination of the latest, cutting-edge electric cell device technology. Developing such products, however, requires not only a curved display, but also operational precision of other parts, including the memory, in a flexible state.

Dr. Tae-Wook Kim at KIST announced their successful development of a 64-bit memory array using flexible and twistable carbon nano material and organo-polymer compound, which can accurately store and delete data.

The most common memory cell today uses a silicone (Si)-based hard, inorganic matter, however, in order to be flexible, the materials were fabricated with a carbon-based organic compound. The recently developed memory cell uses a technology, which arranges such organic material in a single configuration at room temperature and places the material on a desired spot on the substrate. This is the core technology in enlarging the storage capacity of memory, an unprecedented discovery until now. In particular, demonstrating this on a bendable substrate required highly sophisticated technology, which signified difficulties in fabrication. The research team developed a technology with the above characteristics to make the electric current flow in one direction so that the data could be rewritable even in a curved state.

Leeds researchers build world’s most powerful terahertz laser chip

University of Leeds researchers have taken the lead in the race to build the world’s most powerful terahertz laser chip.

A paper in the Institution of Engineering and Technology’s (IET) journal Electronics Letters reports that the Leeds team has exceeded a 1 Watt output power from a quantum cascade terahertz laser.

The new record more than doubles landmarks set by the Massachusetts Institute of Technology (MIT) and subsequently by a team from Vienna last year.

Terahertz waves, which lie in the part of the electromagnetic spectrum between infrared and microwaves, can penetrate materials that block visible light and have a wide range of possible uses including chemical analysis, security scanning, medical imaging, and telecommunications.

Widely publicised potential applications include monitoring pharmaceutical products, the remote sensing of chemical signatures of explosives in unopened envelopes, and the non-invasive detection of cancers in the human body.

However, one of the main challenges for scientists and engineers is making the lasers powerful and compact enough to be useful.

Professor Edmund Linfield, Professor of Terahertz Electronics in the University’s School of Electronic and Electrical Engineering, said: “Although it is possible to build large instruments that generate powerful beams of terahertz radiation, these instruments are only useful for a limited set of applications. We need terahertz lasers that not only offer high power but are also portable and low cost.”

The quantum cascade terahertz lasers being developed by Leeds are only a few square millimetres in size.

In October 2013, Vienna University of Technology announced that its researchers had smashed the world record output power for quantum cascade terahertz lasers previously held by Massachusetts Institute of Technology (MIT). The Austrian team reported an output of 0.47 Watt from a single laser facet, nearly double the output power reported by the MIT team. The Leeds group has now achieved an output of more than 1 Watt from a single laser facet.

Professor Linfield said: “The process of making these lasers is extraordinarily delicate. Layers of different semiconductors such as gallium arsenide are built up one atomic monolayer at a time. We control the thickness and composition of each individual layer very accurately and build up a semiconductor material of between typically 1,000 and 2,000 layers. The record power of our new laser is due to the expertise that we have developed at Leeds in fabricating these layered semiconductors, together with our ability to engineer these materials subsequently into suitable and powerful laser devices.”

Professor Giles Davies, Professor of Electronic and Photonic Engineering in the School of Electronic and Electrical Engineering, said: “The University of Leeds has been an international leader in terahertz engineering for many years. This work is a key step toward increasing the power of these lasers while keeping them compact and affordable enough to deliver the range of applications promised by terahertz technology.”

Quantum dots provide complete control of photons

A semiconductive materials research group led by Professor Per Olof Holtz is now presenting an alternative method where asymmetrical quantum dots of a nitride material with indium is formed at the top of microscopic six-sided pyramids. With these, they have succeeded in creating light with a high degree of linear polarization, on average 84%. The results are being published in the Nature periodical Light: Science & Applications.

“We’re demonstrating a new way to generate polarized light directly, with a predetermined polarization vector and with a degree of polarization substantially higher than with the methods previously launched,” Professor Holtz says.

In experiments, quantum dots were used that emit violet light with a wavelength of 415 nm, but the photons can in principle take on any colour at all within the visible spectrum through varying the amount of the metal indium.

“Our theoretical calculations point to the fact that an increased amount of indium in the quantum dots further improves the degree of polarization,” says reader Fredrik Karlsson, one of the authors of the article.

The micropyramid is constructed through crystalline growth, atom layer by atom layer, of the semiconductive material gallium nitride. A couple of nanothin layers where the metal indium is also included are laid on top of this. From the asymmetrical quantum dot thus formed at the top, light particles are emitted with a well-defined wavelength.

The results of the research are opening up possibilities, for example for more energy-effective polarized light-emitting diodes in the light source for LCD screens. As the quantum dots can also emit one photon at a time, this is very promising technology for quantum encryption, a growing technology for wiretap-proof communications.

Blog Review November 18 2013

Monday, November 18th, 2013

Dick James of Chipworks says that 28-nm samples they have seen from GLOBALFOUNDRIES and Samsung are remarkably similar, and ponders the possibility of Apple’s A7 chips being fabricated in New York in the not too distant future.

Recent progress in silicon photonics and optical interconnects is the focus of Pete Singer’s blog. Fujitsu and Intel recently demonstrated the world’s first Optical PCIe Express (OPCIe) based server, using Intel’s silicon photonics chip. Ludo Deferm of imec talks about what’s’ needed for intrachip optical communication.

Rich Wawrzyniak of Semico talks about what he learned from a discussion with Sundar Iyer, CEO of Memoir Systems, on the company’s new Pattern Aware Memory IP technology. Memoir has identified several different types of memory-processor operations and has created memories that perform these functions in the normal course of their operation within the system. In addition, this approach can save designers and device architects a considerable amount of die area, producing tangible power savings while increasing device performance.

Phil Garrou covers three new developments in the area of 3D integration this week. He looks at work from Leti/ST Microelectronics that explored the limits of conventional interconnects on RDL (vs damascene). They were able to achieve 8 µm line/spaces with high uniformity and reproducibility. He also reports on work from BESI and imec on thin wafer handling, and a new low temp via reveal process developed by SPTS.

Crossbar Unveils Resistive RAM with Simple, Three-Layer Structure

Sunday, September 1st, 2013

By Pete Singer

Crossbar, Inc., a start-up company, unveiled a new Resistive RAM (RRAM) technology that will be capable of storing up to one terabyte (TB) of data on a single 200mm2 chip. A working memory was produced array at a commercial fab, and Crossbar is entering the first phase of productization. “We have achieved all the major technical milestones that prove our RRAM technology is easy to manufacture and ready for commercialization,” said George Minassian, chief executive officer, Crossbar, Inc. The company is backed by Artiman Ventures, Kleiner Perkins Caufield & Byers and Northern Light Venture Capital.

The technology, which was conceived by Professor Wei Lu of the University of Michigan, is based on a simple three-layer structure of silver, amorphous silicon and silicon (FIGURE 1). The resistance switching mechanism is based on the formation of a filament in the switching material when a voltage is applied between the two electrodes. Minassian said the RRAM is very stable, capable of withstanding temperature swings up to 125°C, with up to 10,000 cycles, and a retention of 10 years. “The filaments are rock solid,” he said.

Crossbar has filed 100 unique patents, with 30 already issued, relating to the development, commercialization and manufacturing of RRAM technology.

After completing the technology transfer to Crossbar’s R&D fab and technology analysis and optimization, Crossbar has now successfully developed its demonstration product in a commercial fab. This working silicon is a fully integrated monolithic CMOS controller and memory array chip. The company is currently completing the characterization and optimization of this device and plans to bring its first product to market in the embedded SOC market.

Sherry Garber, Founding Partner, Convergent Semiconductors, said: “RRAM is widely considered the obvious leader in the battle for a next generation memory and Crossbar is the company most advanced to show working demo that proves the manufacturability of RRAM. This is a significant development in the industry, as it provides a clear path to commercialization of a new storage technology, capable of changing the future landscape of electronics innovation.”

FIGURE 1. The resistance switching mechanism of Crossbar’s technology is based on the formation of a filament in the silicon-based switching material when a voltage is applied between the two electrodes.

Crossbar technology can be stacked in 3D, delivering multiple terabytes of storage on a single chip. Its simplicity, stackability and CMOS compatibility enables logic and memory to be integrated onto a single chip at the latest technology node (FIGURE 2).

Crossbar’s technology will deliver 20x faster write performance; 20x lower power consumption; and 10x the endurance at half the die size, compared to today’s best-in-class NAND Flash memory. Minassian said the biggest advantage of the technology is its simplicity. “That allowed us in three years time to get from technology understanding, characterization, cell array and put a device together,” he said.

Minassian said RRAM compares favorably with NAND, which is getting more complex and expensive. “In 3D NAND, you put all of these thing layers of top of each other – 32 layers, or 64 or 128 in some cases – then you have to etch them, you have to slice them all at once and the equipment required for that accuracy and that geometry is very expensive. This is one of the reasons that 3D has been very difficult for NAND to be introduced.” With the Crossbar approach, “you’re always dealing with three layers. It’s much easier to stack these and it gives you a huge density advantage,” Minassian said.

“The switching media is highly resistive,” explains Minassian. “If you try to read the resistance between top and bottom electrode without doing anything, it’s a high resistance. That’s the off state. To turn on the device, we apply a positive voltage to the top electrode. That ionizes the metal on the top layer and puts the metal ions into the switching media. The metal ions form a filament that connect the top and bottom electrode. The moment they hit the bottom electrode, you have a short, which means that the top and bottom electrode are connected which means they have a low resistance.” The low resistance state is the on state. He said that although silver is not commonly used in front-end CMOS processing, the RRAM memory formation process is a back-end process. “You produce all your CMOS and then right before the device exits the fab, you put the silver on top,” he said. The silver is deposited, encapsulated, etched and then packaged. “That equipment is available, you just have to isolate it at the end,” Minassian said.

FIGURE 2. Crossbar’s simple and scalable memory cell structure enables a new class of 3D RRAM which can be incorporated into the back end of line of any standard CMOS manufacturing fab.

The approach is also CMOS compatible, with processes used to fabricate the memory layers all running at less than 400°C. “This allows you to not only be CMOS compatible, but it allows you to stack more and more of these memory layers on top of each other,” Minassian said. “You can put the logic, the controllers and microprocessors, next to the memory in the same die. That allows you to simplify packaging and increase performance.”

Another advantage compared to NAND is that the controllers used to address the cells can be less complicated. Minassian said that in conventional cells, 30 electrons are required to produce 1 Volt. “If you shrink that to a smaller node, the number of electrons is less. Fewer electrons are much harder to detect. You need a massive controller that does error recovery and complex coding so if the bits are changed, it can still provide you the right program to execute.” Also, because the Crossbar RRAM is capable of 10,000 write cycles, less complicated controllers are needed. Today’s NAND is capable of only 1000 write cycles. “If you write information 1000 times, that cell is destroyed. It will not contain or maintain the information. You have this complex controller that keeps track of how many cells have been written, how many times, to make sure all of them are aged equally,” Minassian said.

Non-volatile memory, expected to grow to become a $60 billion market in 2013, is the most common storage technology used for both code storage (NOR) and data storage (NAND) in a wide range of electronics applications. Crossbar plans to bring to market standalone chip solutions, optimized for both code and data storage, used in place of traditional NOR and NAND Flash memory. Crossbar also plans to license its technology to SOC developers for integration into next-generation systems-on-chips (SOC).

Michael Yang, Senior Principal Analyst, Memory and Storage, IHS, said: “Ninety percent of the data we store today was created in the past two years. The creation and instant access of data has become an integral part of the modern experience, continuing to drive dramatic growth for storage for the foreseeable future. However, the current storage medium, planar NAND, is seeing challenges as it reaches the lower lithographies, pushing against physical and engineering limits. The next generation non-volatile memory, such as Crossbar’s RRAM, would bypass those limits, and provide the performance and capacity necessary to become the replacement memory solution.”