By Mark LaPedus
The auction of ProMOS‘ 300mm fab ended in failure this week. There were no bidders for the Taiwan DRAM fab, as the price was considered too steep, according to reports. The bidding for the fab will re-open next month. At one time, GlobalFoundries, TSMC and UMC were interested in the fabrication facility. Now, Taiwan foundry vendor Vanguard is the leading contender for the facility.

GlobalFoundries is embarking on a long-term strategic initiative, called “Vision 2015,”which will include the expansion of its Singapore-based 300mm fab for advanced mixed-signal processes. However, the company reduced the site workforce by approximately 300 employees, or about 4% percent of its Singapore employee base, due to the softening of the current macro-economic environment.

The Semiconductor Industry Association (SIA) has elected GlobalFoundries CEO Ajit Manocha as its 2013 chairman and John Kelly III, IBM senior vice president and director of IBM Research, as its 2013 vice chairman.

Applied Materials plans to combine two business units, Energy and Environmental Solutions (EES) and Display, under one leader. Ali Salehpour, a former senior vice president at KLA-Tencor, will join Applied as group vice president and general manager of the EES and Display groups. As part of the changes, Mark Pinto, executive vice president and general manager of EES, and Tom Edman, group vice president and general manager of Display, announced their intention to leave Applied.

For the quarter, Mentor Graphics reported revenue of $268.8 million, non-GAAP earnings per share of $0.32, and GAAP earnings per share of $0.27. “Revenue and earnings were records for Q3. Mentor and the electronic design automation industry continue to benefit from the semiconductor industry’s transition to the next generations of technology,” said Walden Rhines, chairman and CEO of Mentor Graphics.

The Collaborative Alliance for Semiconductor Test (CAST), a SEMI special interest group, has elected new leadership. Elected by CAST was Chris Portelli Hale, manufacturing test director at STMicroelectronics, as CAST chair, and Octavio Martínez, senior director of engineering at Qualcomm, as vice chair.

Tokyo Electron Limited (TEL) has cancelled its joint solar venture contract with Sharp and dissolved the joint venture Tokyo Electron PV Ltd. set up by both companies. In February 2008, TEL and Sharp embarked on the development of plasma CVD systems for use in thin-film silicon solar photovoltaic cells. At present, Sharp appears to be in financial trouble. Meanwhile, TEL has also been on an acquisition spree. In March, TEL announced the acquisition of Oerlikon Solar. In May, TEL reached a definitive agreement to acquire NEXX Systems.  In October, TEL acquired FSI International. In November, TEL reached a definitive agreement to acquire Magnetic Solutions Ltd. MSL is engaged in the development, manufacture, and sale of magnetic annealing systems.

David Lam, founder of Lam Research in 1980, and currently chairman of both Multibeam and the David Lam Group, has been selected for induction into the distinguished Silicon Valley Engineering Hall of Fame. Other eminent technologists selected for induction include: Aart de Geus, chairman and co-CEO of Synopsys; Martin Hellman, professor emeritus of electrical engineering at Stanford University; and David Hodges, professor emeritus of the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley.

Here’s the current climate for VLSI Research’s so-called “Weather Report,” which gives a pulse on the IC industry: “The clouds are clearing, revealing a tall mountain to climb. Order activity jumped higher for the first time in nearly six months, led by foundries and logic IDMs. The uptick is seasonal and it’s coming off very low levels as chipmakers remain very cautious about prospects in 2013 due to macro and fiscal uncertainties. Moreover, order activity is down nearly 9 points from last year’s levels, which suggests that the seasonal increase in Q1 will be more subdued from last year. We expect Q1 sales to increase 10% sequentially.”

Despite soft macroeconomic conditions, the market for mobile communications equipment will grow by a robust 13 percent this year, propelled by climbing shipments of mobile handsets and tablets, according to iSuppli.

Samsung and Apple are forecast to dominate the smartphone market this year. In total, these two companies are expected to ship an estimated 353 million smartphones and hold a combined 47% share of the total smartphone market in 2012, according to IC Insights. Smartphone suppliers under pressure include Nokia, RIM, and HTC, each of which is expected to register steep double-digit year-over-year declines in smartphone unit sales this year.

Who’s winning the tablet wars? The answer: Apple, Amazon and Google. The loser? Microsoft. Apple is expected to ship 67.7 million iPads in 2012 and 83.5 million in 2013, according to FBR. The iPad mini is off to a slow start. And Samsung is trailing the pack with the Galaxy Tab. Samsung will ship 6 million Tabs in 2012 and 7.4 million in 2013, according to FBR. Craig Berger, an analyst with FBR, said: “We think Apple will manufacture at least 7.5 million iPad minis in 2012, and 18.5 million units in 2013. We now believe Amazon will manufacture about 10 million units (of the Kindle Fire HD) in 2012 and 15 million in 2013. We think the Google Nexus could move more than 6 million units in 2012 and about 10 million units in 2013. Contrary to what we see for the Kindle Fire and Google Nexus, we believe the first month’s sales of the MS Surface RT tablet have underwhelmed expectations. We estimate production of all Surface tablets, including the x86 models available in 1Q ’13, to be about 3 million units in 4Q ’12, with sales perhaps trending around 3-5 million units in all of 2013.”

By Mark LaPedus
In a blog, a former technologist from SEMI makes a strong case for 450mm fabs after dismissing the technology some years ago.

NASA faces some new and big challenges. There is wave of counterfeit parts hitting the space agency, a phenomenon that threatens the success of its missions, the safety of its personnel and the security of the country, according to iSuppli.

Three pure-play foundries, TSMC, GlobalFoundries and UMC, are expected to be in the top 20 rankings of leading semiconductor suppliers in 2012, according to IC Insights.

X-FAB Silicon Foundries announced its XT018 process, a trench dielectric isolated SOI foundry technology offering for 200V MOS capability at 180nm.

Soitec has more than doubled production of bonded silicon-on-sapphire (BSOS) substrates to meet increased demand from RF chipmaker Peregrine Semiconductor.

Soitec has signed a solar power purchase agreement in South Africa.

Mentor Graphics announced its new Tessent IJTAG solution, which allows designers to easily re-use test, monitoring and debugging logic embedded in existing IP blocks. In addition, ON Semiconductor has completed multiple tapeouts with Mentor’s Pyxis Custom IC Router.

C.J. Muse, an analyst with Barclays Capital, attended Lam’s analyst day. “One of the key points from the analyst day was Lam’s decision to focus on its core markets–etch, deposition, clean, and strip–as evidenced by its announcement to exit the PVD business and selling off the Peter Wolters business in 2013. We note that Novellus’s share in the PVD subsegment had steadily declined in recent years, reaching ~5-6% of the $1.6 billion market in 2011,” Muse said. “Lam had suggested that while the 2012 WFE is tracking weaker to ~$28-29 billion, the company anticipated the 2013 WFE market to recovery to $30B+, driven by a $1-$2 billion pick-up in memory, particularly NAND.”

Kulicke & Soffa Industries posted its results for its fourth quarter and fiscal year ended Sept. 29.

STATS ChipPAC has expanded its packaging options for advanced embedded Wafer Level Ball Grid Array (eWLB) technology.

Deca Technologies rolled out its M-Series CSP product line featuring Adaptive Patterning.

Alchimer, a provider of deposition technologies for advanced 3D packaging, through-silicon vias (TSVs) and other electronic applications, announced the appointments of Bruno Morel as CEO.

RF Micro Devices signed a definitive agreement to acquire Amalfi Semiconductor.

Wide-band-gap semiconductor materials such as gallium nitride (GaN) offer far higher performance than traditional silicon but cost significantly more. However, by 2020 GaN costs will drop enough for it to become competitive based on performance gains, according to Lux Research.

Worldwide tablet shipments totaled 27.8 million units in the third quarter of 2012, says IDC. Android shipments, led by Samsung and Amazon, surged during the quarter, at the expense of Apple, which saw its share slip notably during the quarter.

The “smart trend” has hit IT as an unstoppable force, as 821 million smart devices (smartphones and tablets) will be purchased worldwide in 2012 and pass the billion mark in 2013, according to Gartner.

More than half of all electronic OEMs worldwide plan to reduce the number of contract manufacturers they work with during the next year, according to iSuppli.

By Mark LaPedus
Intel reported quarterly revenue of $13.5 billion and net income of $3.0 billion. http://finance.yahoo.com/news/intel-reports-third-quarter-revenue-200100019.html C.J. Muse, an analyst with Barclays Capital, said: “Intel lowered its capex guidance to $11.3 billion for 2012 vs. our estimate of $11.8 billion. While we believe Intel will remain vigilant in the ramp of 14nm, as Intel looks to aggressively redirect space and equipment to 14nm (80-90% of equipment bought at 22nm is reusable at 14nm node), we see capex of ~$9 billion +/- $1 billion in 2013.”

Is AMD on the ropes again? AMD will cut its workforce by approximately 15%. It also announced revenue for the third quarter of 2012 of $1.27 billion and a loss of $157 million. “Management’s ongoing mis-execution in our opinion seems to be contributing to building too much inventory, firing top operational managers, channel misalignment (and) withdrawing from broad swaths of the market,” said Craig Berger, an analyst with FBR. Meanwhile, analyst, Hans Mosesmann of Raymond James, said: “The worrisome but not too surprising commentary by AMD management was that the PC market will take several quarters to recover. AMD now considers 85% of its current business ‘legacy’ PC, with the planned restructuring focused on attacking various adjacent high-volume markets.”

Seeking to accelerate the development of EUV lithography, ASML has entered into a definitive agreement to acquire Cymer for $2.6 billion. “Cymer’s light source is critical to EUV success and given recent slippage of key metrics, we think it makes sense for the technology to move in-house at ASML,” Muse said.

In response to its foundry rivals, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) has updated and accelerated its finFET roadmap.

GlobalFoundries could employ as many as 3,000 workers at its Malta plant, according to reports.

STMicroelectronics’ 28nm Fully Depleted Silicon-On-Insulator (FDSOI) process, which uses substrates from Soitec, is now available for prototyping to universities, research labs and design companies through the silicon brokerage services provided by CMP.

Soitec announced total consolidated sales of 130.2 million euros for the first half, down by 19.9% on a yearly basis.

European government representatives, consortia and suppliers discussed 450mm fabs at Semicon Europa in Dresden.

North America-based manufacturers of semiconductor equipment posted a book-to-bill ratio of 0.81 in September, compared to 0.84 in August, according to SEMI.

Mentor Graphics has rolled out a formal-based technology in the Questa Verification Platform.  In addition, Mentor announced new capabilities to complement TSMC’s 20nm manufacturing processes.  Meanwhile, SpringSoft and Mentor announced that the Laker-Calibre RealTime custom layout flow has been selected for the TSMC Custom Design Reference Flow. In a related announcement, TSMC has presented Mentor with two “Partner of the Year 2012” awards in various categories. And, Mentor announced the winners of its 24th annual PCB Technology Leadership Awards.

At the Storage Networking World (SNW) conference, there was no shortage of SSD presentations. But none of the keynoters who shared their data center experiences had deployed any SSDs in their systems. This seemed particularly odd to The SSD Guy.

Amazon is in talks to buy the mobile chip business of Texas Instruments. TI’s chips are used in Amazon’s Kindle Fire tablet.

FormFactor completed its acquisition of Astria Semiconductor Holdings and its subsidiary MicroProbe.

Lam Research achieved revenue of $906.9 million, up 22.3% from prior quarter, in first full quarter of consolidated results with Novellus.  “Based on continued push-outs of NAND spending, Lam guided to December quarter revenues of $820-880 million, well below consensus of $927 million,” said Barclay’s Muse. “While management had previously suggested that 2012 WFE was tracking to the low end of the $29-30 billion outlook, management took the opportunity to lower their 2012 WFE outlook to about $28-29 billion.”

Xilinx announced fiscal Q2 2013 sales of $543.9 million, down 7% sequentially and down 2% from the second quarter of the prior fiscal year.  Barclay’s Muse said: “Xilinx reported mixed September quarter results and then guided to worse December quarter, highlighting continued macro pressure for semis.”

Microchip Technology has lowered its forecast. “Our lower than anticipated net sales activity in the September quarter was driven primarily by macroeconomic and industry conditions,” said Steve Sanghi, Microchip’s president and CEO. “The overall global economic outlook continues to be poor and is adversely impacting our business as well as the rest of the semiconductor industry.”

Marvell expects net revenue for the third quarter of fiscal 2013 will be in the range of $765 million to $785 million, compared with prior outlook of between $800 million to $850 million. “The continued slowdown in the global economy during the third quarter is resulting in a weaker PC market than previously anticipated and thus lower demand from our storage HDD customers,” said Sehat Sutardja, Marvell’s chairman and CEO. FBR’s Berger said: “We think Marvell has a structural management problem that inhibits the firm from realizing real change, may discourage the development of formalized engineering processes, and keeps the firm on what seems to be a self-destructive path of no growth and limited traction in cellular. With the board unwilling to make real changes, business at Marvell could migrate from bad to worse over time.”

The NAND and NOR flash memory market landscape is shifting rapidly, with increasingly sophisticated mobile handsets playing a leading role in driving industry trends and determining which suppliers will be successful, according to IHS iSuppli.

By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss future manufacturing challenges with Carlos Mazure, chief technical officer at Soitec; Jeff Hebb, vice president of laser product marketing at Ultratech; Markus Wimplinger, corporate technology development and IP director at EV Group; and Girish Dixit, vice president of the customer integration center and process interactions at Lam Research. What follows are excerpts of that conversation.

SMD: Let’s look into the crystal ball and make some predictions. We’ve seen a considerable amount of consolidation in the semiconductor and IC equipment industries. Will the industry continue to consolidate?
Hebb: Every node gets more and more expensive. The industry will continue to consolidate as the nodes shrink. It is going to accelerate. At 14nm, you may see one of the major foundries drop out, or maybe even at 20nm. That’s a strong possibility. In the fabless-foundry world, only the guys with lots of money can afford to design at leading-edge nodes. Building these chip alliances has allowed some of these guys to stay in the game. On the equipment side, it’s the same thing. 450mm will only accelerate the consolidation. There are not going to be that many companies that will go to 450mm. We all know the list. On the equipment side, companies that are really small, or don’t have strong balance sheets, are going to have a tough time funding 450mm. Over time, a lot of the big guys will absorb a lot of the smaller guys—though lately, it’s been more like the big guys absorbing the big guys.
Wimplinger: We’re a mid-size company. Traditionally, we’ve always been early in technology development. That has served us very well in the past 30 years. So we don’t have any plans to be consolidated into another company. But it may be a slightly different story in pure front-end companies, where maybe consolidation is the only way to succeed.

SMD: Speaking of the next-generation wafer size, when will 450mm go into mass production?
Hebb: My wild guess for 450mm is 2018. It’s going to take awhile. The Albany consortium, the G450C, will be bringing in alpha tools next year—perhaps the back half of next year. But I think the industry is going to crawl while everyone gets ready and all the 450mm tools get ironed out. So 2018 is not a bad guess. One more quick comment on in-situ metrology and control for 450mm. That’s going to become even more critical at 450mm. Wafer scrap wasn’t tolerated at 300mm. As you can imagine, wafer scrap isn’t going to be tolerated at 450mm.
Wimplinger: For 450mm, we’ll see first production in 2016. For us, scaling our equipment to 450mm is under way. We’ve already announced the first systems available in 450mm. We are leveraging our learning from the 200mm and 300mm wafer progressions. From a technical side, we are not too concerned. But it’s an exercise that consumes R&D dollars. We need to focus our R&D dollars because we have a very wide portfolio of wafer sizes. We serve two-inch in compound semiconductor applications. We have a major share in the antenna circuitry for packaging in MEMS, which are still done at 200mm. And 300mm is not going away anytime soon.
Mazure: It depends on what applications you are looking at. Not all applications will roll out on 450mm. Memories and processors? Yes. But probably not RF and power management. Just to talk 450mm limits the focus. We forget the rest. Many companies are not looking at 450mm, or 14nm and 20nm.

SMD: What about stacked 3D chips using TSVs?
Wimplinger: The industry is convinced memory will move to 3D at least for some volumes fairly soon. There will be serious production probably in 2014. The transition to 450mm might be a year or two later. I am convinced the industry will do 3D on 450mm. From our perspective, that’s something a little bit overlooked at the moment in the 450mm discussion. The backend will play a role in 450mm.
Hebb: I agree. The backend packaging isn’t really being considered too much for 450mm. Everyone is focused on the front-end, not backend, for 450mm .

SMD: When will foundries move into finFET production?
Hebb: 20nm will come sometime in 2014. When will finFETs come at 14nm? I don’t see that happening before 2016.
Mazure: For finFETs in the foundries, I see risk production at the end or second half of 2015, and then volume production is in 2016. That has to happen before a foundry moves to 450mm.

SMD: Are there other issues with finFETs?
Dixit: The scaling path is very clear. You can say finFETs are the next step to scale a device. The challenge for the foundries is how many finFET wafers do they run in their fabs and at what nodes?
Mazure: A processor running at 14nm technology may be of no use if you do not have the Wide I/O or other types of memory that go along with it. So it’s not one part of the industry that must scale. Besides finFETs, everything has to move. Then, if you have the memory and application processor, but you cannot communicate in the system and your RF is not efficient, we still have a problem. Simply put, it’s not just one company pushing the transistor scaling. It doesn’t work that way anymore. The industry has changed in other ways. We are a systems-driven and a customer interface-driven industry. Software is the key.

SMD: When will the foundries offer SOI in volumes?
Mazure: Traditional SOI is partially depleted. But that’s a completely different technology than fully depleted. Fully depleted has an SOI structure, but it behaves like bulk. You don’t have partially depleted issues. The interesting thing is that a traditional bulk company like STMicroelectronics is moving towards fully depleted SOI. Now, STMicroelectronics is moving it into a foundry (under a deal with GlobalFoundries). So, it will become an open platform. Today, in a fabless-foundry scheme, there are no finFETs available. That will come.

By Mark LaPedus
Semiconductor Manufacturing & Design sat down with Carlos Mazure, chief technical officer at Soitec; Jeff Hebb, vice president of laser product marketing at Ultratech; Markus Wimplinger, corporate technology development and IP director at EV Group; and Girish Dixit, vice president of the customer integration center and process interactions at Lam Research. What follows are excerpts of that conversation.

SMD: Intel entered the finFET era at the 22nm node and is in production now. The foundries plan to do finFETs at 14nm. What are the challenges facing the foundries in finFETs?
Hebb: The company that has already succeeded in introducing finFETs tends to introduce things a couple of generations before anyone else. But for finFETs, it’s turning out to be quite a challenge for the foundries. The foundries will get there with enough work. The foundries will get to the point relatively soon, if they are not there already, where they have working transistors. But getting it into manufacturing with yield is a little bit unpredictable. The question is how fast will they be able to come up the yield curve? The yield curve between 28nm, 20nm and then 14nm could look drastically different. Everyone will get a finFET transistor working, but who is really going to make it yield and make it manufacturable? For the foundries, another major challenge is going to make finFETs in a cost-effective way. If you think about an applications processor from a foundry, the cost is anywhere between $10 and $30. If you’re selling a high-end microprocessor for a few hundred dollars, then you can do a lot of things in manufacturing you couldn’t in a foundry.
Dixit: FinFETs are the next step to scale a device. The benefits in terms of performance and power are all very obvious for finFETs. But I don’t know how easy it is to translate planar into finFETS at the foundry level. People are talking about how to control the variance of the fin itself. I don’t think it’s that easy to take planar and fit a fin on it. Trying to do multiple design types and doing it in a timely and cost-effective manner will also be challenging. And then you put the finFET into the design as part of the ecosystem. What do you do when you have all of these old standard cell libraries without having to make any changes from planar to a 3D transistor? You also have to make sure you get the right behavior models out of it. But the question is what are the demands from the systems-level ecosystem? How widely finFETs will get used is the other question?
Mazure: What’s driving this transition is the need to reduce leakage and power consumption. Intel, for one, has introduced the first finFET called Tri-Gate. Intel is a vertically integrated company. Design and manufacturing technology go hand-in-hand. You basically impose this in a bottoms-up fashion. This is the same type of approach in memories. Once you move outside this ecosystem, you have the fabless companies and the foundries. In that ecosystem, there are different design methodologies. You also have legacy IPs. Therefore, it’s not so simple. For time to market, the industry must look at how to reuse its design methodology without throwing everything out the window and developing everything from scratch. Power management also has a lot to do with design. Going forward, there is a need for finFETs. We will see the appearance of more and more fully depleted devices. But in finFETs, I also think there are bigger challenges for the foundries. Having a finFET is probably easy. You can develop ring oscillators and SRAM bits, but nobody buys that. Having an integrated process that yields is a different story. You need to do real circuits, applications processors and basebands. But let’s not forget, for many fabless companies, 28nm is going to be a long-lived node. Not everybody is going to immediately jump on the next node and move to the foundries with finFETs at 14nm.

SMD: Will the finFET architecture at 14nm look the same at 8nm? Or will you have to start from scratch at 8nm?
Hebb: You won’t start from scratch, but I think you’ll see different materials. You’ll start to see III V materials, maybe III V channels at 8nm. It’s the same way a planar transistor at 45nm is not going to be the same at 20nm. You will see new materials. You will probably see different strain engineering, as well.

SMD: Will we see the same or different lithography at those nodes?
Dixit: If you look at memory and advanced logic today, there is some level of double-patterning going on. Logic is maybe a little bit behind. Memory has been using double-patterning for a long time. For future nodes, people are now talking about triple-patterning and quadruple-patterning. Basically, this uses today’s illumination without changing to a radically different source. So, multi-patterning will be required for some critical steps. But the question is how do you partition those things?
Wimplinger: We have our eye on next-generation lithography. We have some activity in 450mm with our nanoimprint technology. But we are not really convinced nanoimprint will be the way to do patterning in manufacturing in the long run.
Mazure: The industry has a track record of pushing the limits in optical lithography. When I started my career, we were told the end of optical was one micron. We were told optical lithography could not print things smaller than that. For future nodes, I’m sure the lithography community will figure it out.

SMD: What role will SOI and bulk play in future designs?
Hebb: I think we might see a mix of solutions. Different companies have different levels of experience with SOI. Some companies have long, long histories with SOI. Some are extremely comfortable with it. Other companies have not really taken a serious look at SOI. Those companies would have a long learning curve with SOI. Those companies would likely go the bulk direction.
Dixit: It’s not going to be a one-solution-fits-all in terms of bulk or SOI. The foundries, IDMs and other players will look for solutions that are suited for their customers.
Mazure: The industry is going fully depleted. There are two ways of going fully depleted: planar and 3D. For planar, design porting is very easy. That can address huge volumes. That can address many applications. It’s very flexible, given that SOI is an evolution from 28nm bulk technology. For the brand new designs from scratch, some companies may decide to start fresh at 14nm technology with fully depleted SOI. But there are not too many companies that will need that type of technology today. Many companies are still designing in 65nm and 40nm. The question for leading-edge chipmakers is how long do they wait in 28nm before they need to swallow the pill? This, of course, is not a question for Intel. They have already made the transition to finFETs.

By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss future manufacturing challenges with Carlos Mazure, chief technical officer at Soitec; Jeff Hebb, vice president of laser product marketing at Ultratech; Markus Wimplinger, corporate technology development and IP director at EV Group; and Girish Dixit, vice president of the customer integration center and process interactions at Lam Research. What follows are excerpts of that conversation.

SMD: What are the big challenges facing the semiconductor and fab equipment industries today?
Hebb: One of the major challenges is process control. As the nodes shrink, and especially going to finFETs, the equipment must control the process with more uniformity, repeatability, and in a manufacturable way. Those challenges are not rising exponentially, but they are really getting tougher and tougher. We see requirements for in-situ metrology and direct control on whatever you are doing on the wafer. This is especially challenging for foundries, because they have so many mask sets. The issue of pattern loading also plays into this. You also have the challenge of within-die control uniformity. And then you have the challenge within the wafer and then wafer-to-wafer for many different mask sets. And as you go to 3D structures, this is going to become even tougher.
Dixit: Variation is a big factor in everything. Then, you couple that with what’s going on, and what could be projected, for lithography. The other part is materials. And then look at what went into the finFET. Trying to get these things together and do them in a fashion so that you are not worried about variation across the wafer is a challenge. When you compare gate oxide thicknesses 10 years ago to today, you are now talking about having variances of less than a third of that thickness across 300mm substrates. You are talking about very small numbers. That’s a big challenge. Then you start questioning how quickly can things shrink. Can chipmakers really stay on the physical feature size path? Can the industry move fast enough to the next node? And what will be required in next generation nodes?
Mazure: When you look at a tablet or smartphone, it’s not only the processor that has the latest feature size. The device also consists of memory, RF parts, controllers and image sensors. And then you add more and more functionality to a system. You basically don’t use it as a phone anymore. You use it in other ways like mobile computing. So for me, the challenges are how the ecosystem can contribute to reduce the overall power envelope. It’s all about reducing the power envelope without sacrificing performance. For the customer, the ease-of-use must not be impacted.
Wimplinger: The challenge for us is to understand how all of the technologies tie in together. On one hand, we see 3D happening. But it’s a little bit less clear what role 3D will play in the 450mm transition. Will it happen at the same time? That is, of course, is a question mark. We have to think about this, because we have to put the appropriate resources towards our R&D and equipment development.

SMD: Speaking of 450mm, what are the challenges in terms of moving to the next wafer size?
Hebb: In 450mm, you divide it into economic problems and technical problems. On the technical side, managing the uniformity across the entire wafer is going to be challenging. But the general problem for equipment suppliers is that 450mm obviously diverts R&D dollars. So now, you not only have to develop your equipment for new capabilities and materials, but you also have to develop your tools for the bigger wafer sizes. With all of this, you’re selling less equipment to fewer customers. Nonetheless, we have to get ready for 450mm. 450mm is not going to stop the good companies. Good equipment companies with strong balance sheets will do it and be successful at it.
Dixit: If you look back at the 200mm to 300mm transition, the industry started and stopped the process many times. I think the industry has learned from that. When I look at the big picture, I see some positive changes in the way people operate. The big question for the 450mm transition is how soon and when will it happen?
Wimplinger: For the processes we supply, we think our equipment is fairly scalable. Our concern is where to put those R&D dollars. There are other challenges with 450mm. Although Sematech is trying to put (a 450mm consortium) together, it’s not fully clear who will be playing which role. There are institutes in Europe that have been active like IMEC. There are some in Asia who want to play a role. But there are only so many resources available to work with everyone. The thing we learned is that we have to become more pro-active in the transition. If you’re a little ahead when you are really getting pushed by customers, it’s a little less painful.
Mazure: Our position is more like the IC companies. To make SOI, we need to buy the equipment. In that sense, we’re fully aligned with the equipment roadmap. We have already demonstrated the feasibility of scaling up to 450mm. But we shouldn’t forget to address the other wafer sizes. For example, leading edge in RF is still at 200mm. There is also a lot of power management at 200mm. In automotive, you don’t need 450mm. You are looking at 300mm and mainly 200mm.

SMD: To ensure that 450mm and EUV are on time, Intel, TSMC and Samsung recently invested in ASML. Are we seeing a new business model evolving in the equipment industry, where IC makers invest in fab tool vendors?
Mazure: Only the leading-edge chipmakers are pushing for 450mm. That reduces the market to just a few companies. And that puts incredible pressure on the equipment suppliers. So if leading-edge chipmakers want 450mm to happen at a certain timeline, they have to change the model.
Hebb: Intel’s move to work with ASML is a good sign. The chipmakers are recognizing that they need to kick in some funding. But that’s really the first sign we’ve seen. My gut feeling is that (the investments in ASML) might be a special case because of the cost of the lithography equipment. Leading-edge lithography is set apart just by the sheer capital costs of the equipment. So leading-edge chipmakers must fund some the equipment R&D to secure access to it in the future.

By Mark LaPedus
A nationwide survey, conducted online by Harris Interactive on behalf of Crucial.com, revealed that more than half (52%) of U.S. adults who own a computer have been unhappy with the performance of their computer in the past 6 months.

SEMI rolled out 450 Central, a web-based information service to help the semiconductor industry transition to 450mm-ready solutions.

Mentor Graphics posted strong results for the company’s fiscal second quarter ended July 31, 2012.

GlobalFoundries announced the addition of Bruce Kleinman as vice president of product marketing.

FormFactor has signed a merger agreement with Astria Semiconductor Holdings, the parent company of MicroProbe, Inc., a provider of probe cards. Under the terms, FormFactor will acquire MicroProbe for $100 million in cash and $16.8 million in stock. C.J. Muse, an analyst with Barclays, said: ”We view FormFactor’s acquisition of MicroProbe as largely mixed. From a positive perspective, MicroProbe makes FormFactor a real player in the faster-growing SOC probe card market and the price appears reasonable. From a negative perspective, we expect losses in memory to continue and expect few synergies in the deal.”

Mapper Lithography, a developer of maskless e-beams, has obtained a financing round of 80 million euros.

Lam Research announced that James Bagley, who has served as the company’s chairman of the board for the last 15 years, has decided to retire.

IBM rolled out the zEnterprise EC12, the company’s most powerful mainframe computer to date. zEC12 offers 25% more performance per core, more than 100 configurable cores and 50% more total capacity than its predecessor.

Swissbit—Europe’s largest independent producer of industrial DRAM modules and flash storage products—is expanding its production capabilities, moving into new product markets, and boosting its distribution channels.

Almost a year since the launch of ultrabooks, the market for these products has been a disappointment thus far. Vijay Rakesh, an analyst with Sterne Agee, said: “Overall, ultrabook ASPs remain high. We believe overall the high price points continue to be a challenge for the PC OEMs and also consumers.”

China will overtake the United States in smartphone shipments in 2012, according to IDC.

Driven by increased demand from developed regions for high-end models, smartphones are expected to rise to account for the majority of global cellphone shipments in 2013—two years earlier than previously predicted, according to IHS isuppli.

Media tablets powered by new Microsoft operating systems Windows 8 and Windows RT will have an impact on the overall market; just not this year, according to market intelligence firm ABI Research.

The April to June quarter of 2012 set a new record for media tablet shipments reaching nearly 25 million units, says ABI.

Six months after losing the top spot in the global hard disk drive (HDD) segment, Western Digital in the second quarter recovered its market lead from chief rival Seagate Technology, according to an IHS iSuppli.

In the second quarter of 2012, worldwide server shipments grew 1.4 percent over the second quarter of 2011, while revenue declined 2.9 percent year-on-year, according to Gartner.

By Mark LaPedus
The 14nm node represents an inflection point for leading-edge foundries.

The foundries hope to make a monumental shift from conventional planar transistors at 20nm to finFET structures at 14nm. And to accelerate their finFET efforts, leading-edge foundries are looking at hybrid integration schemes and “modular fin” strategies.

Using this approach, a foundry would devise a fin structure at the front-end with 14nm design rules. The fin structure itself is modular, meaning it can be plugged into a newly developed and corresponding 14nm back-end-of-line (BEOL) interconnect flow.

But by being modular, vendors also have the option to plug in the 14nm fin into an existing planar 20nm BEOL flow. This hybrid integration approach could enable a vendor to accelerate its finFET introduction date, but there are also some die-cost disadvantages.

“There are no challenges from a process point of view,” said Subramani Kengeri, head of advanced technology architecture at GlobalFoundries. “What you are doing is taking a fin module and making it compatible at 14nm and 20nm.”

By going the modular fin route, foundries hope to provide fast and flexible solutions for customers. “It has to be competitive,” he said. Foundries appear to be taking a “modular fin” approach for good reason: They must speed up their finFET efforts to play catch up with Intel and satisfy increasing customer demand for the technology.

Challenges mount at 14nm
The foundries face some challenges to integrate “modular fins,” not to mention bringing up finFET structures in the first place. At 14nm, there are other manufacturing challenges, such as etch, deposition, inspection and lithography. The net result is that there must be a closer collaboration between foundries and customers. “The key is to have a tighter integration between product design and manufacturing,” Kengeri said.

Clearly, the leader in finFETs is Intel Corp., which is already using the technology for its microprocessors at 22nm. At that node, Intel is also providing foundry services to a limited set of fabless chip makers.

Right now, the foundries are still ramping up their 28nm processes, with planar at 20nm and finFETs at 14nm in the works. At 14nm, the industry is not banking on extreme ultraviolet (EUV) lithography. The EUV power source is simply not ready.

Instead, the industry is gearing up for 193nm immersion and multi-patterning. “If EUV was ready today, people would use it,” said David Hemker, chief technology officer in the corporate technology development group at Lam Research. “The industry is confident using double pattering.”

Beside lithography, there is another pressing issue for finFETs: variability. Intel proved that a chipmaker could ramp up finFETs using bulk CMOS technology. Attempting to follow Intel’s successful formula, the foundries have decided to extend bulk CMOS into the finFET era.

But because of fin height variability, there are fears that the foundries could struggle making bulk finFETs. “People are just waking up to this,” said Gary Patton, vice president of the Semiconductor Research and Development Center at IBM. The foundries should take a harder look at silicon-on-insulator (SOI) technology, which can reduce fin height variability, Patton said. And because there are fewer process steps with SOI-based finFETs, the traditional cost penalty associated with SOI disappears, he added.

The finFET transition also will cause a spike for process-control tools. Given the soaring costs of IC designs, there is little margin for error. It will become more critical to spot killer defects much earlier in the process.

One of the emerging areas in process control involves non-visual defects. Non-visual defects do not scatter light and are not detectable by current optical or e-beam inspection tools. “Up to 30% of yield loss in today’s fabs are not traceable to physical defects,” said Robert Newcomb, executive vice president at Qcept Technologies, a metrology tool vendor.

Non-visual defects are cropping up in some new and unforeseen areas in finFET designs. In development work for one customer, for example, Qcept’s tools detected horizontal defect patterns in the outer 20nm to 30nm of the wafer in a finFET design.

Get out the scorecards
And if that isn’t enough, chipmakers will need a scorecard just to keep track of the foundries and their latest finFET roadmaps. The nodes at which vendors will introduce finFETs are a bit misleading and don’t necessarily tell which company is ahead in the race.

For example, United Microelectronics Corp. (UMC) is rolling out finFETs at 20nm. UMC is marrying a 14nm front-end fin with a 20nm backend. Rival Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) is talking about finFETs at the 16nm half-node. So far, Samsung is sticking to its plans to launch finFETs at 14nm.

GlobalFoundries, meanwhile, has devised a modular fin with 14nm front-end design rules, but it has not decided whether it will insert the structure to a 14nm or 20nm BEOL scheme. “We’ve been analyzing to see what is the right approach,” Kengeri said. “We may put it on 20nm. We may put it at 14nm. We may put it on both.”

In all cases, chipmakers still are able to devise new and innovative IC designs with finFETs. “To achieve this, there are many aspects of finFET technology,” he said. “Optimization and upfront planning are key. The ratio of contacted poly pitch, metal layers and fin pitch are critical. The choice of fin pitch will impact fin efficiency, resistance-capacitance, cost, process complexity, scalability and many other metrics. Therefore, it is important to architect the finFET process with a fin pitch optimal for both 20nm and 14nm and targeted for specific applications.”

Still, the modular fin strategy has some tradeoffs. The first option is to combine a 14nm front-end modular fin to a corresponding middle-of-the-line (MEOL) and BEOL flow at 14nm. The fin structure can be easily manufactured using 193nm immersion, multi-pattering and other steps.

The real challenge is to devise an entire new MEOL and BEOL infrastructure at 14nm, which could be an expensive proposition. Chip manufacturers could extend their existing physical vapor deposition (PVD) tools to devise the interconnect at 14nm. But for the capping layers, chipmakers may need to move to new deposition tools as well as materials like cobalt, said Sree Kesapragada, global product manager for metal deposition products at Applied Materials.

Until foundries bring up a new 14nm MEOL/BEOL flow, they may opt to go with the less expensive hybrid approach. This marries a 14nm fin with a 20nm planar MEOL/BEOL flow. The idea behind this approach is that foundries can leverage and use their existing and mature 20nm tools.

There are also some time-to-market and tool cost-of-ownership advantages with the hybrid approach. “There are some pros and cons,” Kengeri said. “You can bring up the technology faster.”

The disadvantage is that the die cost is roughly similar between a 20nm planar device and a hybrid 14nm/20nm finFET. “You don’t get the die cost advantage” of a homogenous 14nm finFET structure, he said. There also could be some integration challenges in terms of the different capacitances between the 14nm front-end fin and the 20nm planar BEOL. “It’s something you have to account for and model,” he said.

By Mark LaPedus
The shift towards the 28nm node and beyond has put the spotlight back on the interconnect in semiconductor manufacturing.

In chip scaling, the big problem in the interconnect is resistance-capacitance (RC). Another, and sometimes forgotten, issue is electromigration. “Electromigration gets worse in device scaling,” said Daniel Edelstein, an IBM Fellow and manager of BEOL technology strategy at IBM Corp. “Some of the issues on the table are becoming limiting problems.”

Electromigration, which can cause voids and failures in a device, refers to the displacement of the atoms as a result of current flowing through a conductor. To suppress electromigration in the interconnect part of the equation, chipmakers typically use a capping or etch stop layer of material on a dual-damascene structure.

But some warn the conventional capping layer of materials in advanced designs—silicon carbon nitride (SiCN) and a copper alloy—could run out of steam at 20nm and beyond, prompting the need for a new solution. “At 20nm, customers will have to bite the bullet,” said Sree Kesapragada, global product manager for metal deposition products at Applied Materials. “Copper does not adhere very well to the dielectric layer. Cobalt is needed for the nanoline.”

In fact, there are several new capping layer options for advanced designs. One solution is to somehow extend the current materials. Another option is Lam Research’s electroless deposition technology, which deposits cobalt-tungsten-phosphide (CoWP) or a related material. This is already in production in at least one foundry vendor at 32nm.

And a newer option is Applied Materials’ in-situ metal/dielectric tool technology for use in depositing cobalt and SiCH. Cobalt-related materials are said to boost electromigration lifetimes by up to hundredfold.

Electromigration in the interconnect
It’s still too early to tell which capping technology will prevail in the long run. The capping layer process takes place during the formation of the interconnect in the dual-damascene flow. The interconnects themselves are becoming more compact at each node, causing unwanted RC. To address the problem, the industry must make advances on two fronts: metallization and low-k dielectrics.

The dual-damascene flow includes the following steps: via and trench patterning, barrier layer and copper seed deposition, electroplating and chemical mechanical polishing. Using a deposition technique, the final step in the process is the addition of a capping layer. This is because the interface between the copper line and capping layer is susceptible to electromigration.

Prior to the 90nm node, IC makers generally used silicon nitride (SiN) as the capping layer material. At 130nm and 90nm, chip makers also moved to low-k materials. The trouble was that the dielectric constant of SiN was more than double that of low-k films, which impacted the overall effective k value of the stack.

This, in turn, prompted chipmakers to switch to SiCN materials for the capping layer as a means to reduce capacitance at or around 90nm. SiN has a dielectric constant of 7.0, while SiCN is around 5.0.

Subramani Kengeri, head of advanced technology architecture at GlobalFoundries, said electromigration became more of an issue for the interconnect at the 45nm and 40nm nodes. So to help suppress electromigration, many chipmakers deposited a tiny percentage of a material such as manganese in the copper seed layer using physical vapor deposition (PVD). Manganese or other types of alloys work in conjunction with SiCN. In effect, these types of alloys “find their way to the top and act like a capping layer,” said IBM’s Edelstein.

At 32nm and beyond, chipmakers would prefer to extend SiCN and the alloy approach without moving to new tool technologies and materials. The problem with this approach is that some of the alloys “diffuse and some of them don’t,” said Applied’s Kesapragada.

The next big material, cobalt, has been proposed because it adheres well to copper. In a structure, IC makers would still use SiCN as the outside metal capping layer. A thin layer of cobalt serves as the interface between the copper and SiCH. Cobalt helps to suppress electromigration, but it adds cost to the equation.

New solutions
Cobalt is getting some traction. For its 32nm processors, Advanced Micro Devices is using a CoWP capping layer, based on Lam Research’s electroless deposition tools. These tools reside within GlobalFoundries, which is making the processors on a foundry basis for AMD.

Electroless is a process of depositing a material with the aid of a chemical reducing agent. The origins of Lam’s electroless tools can be traced back to Blue29, a startup that developed this technology. One of Blue29’s original investors was KLA-Tencor.

In 2004, KLA-Tencor and Dainippon Screen Manufacturing Co. Ltd. formed a joint electroless tool venture and invested in Blue29. But in 2006, KLA-Tencor exited the venture, and subsequently, Lam Research acquired Blue29’s intellectual property.

Electroless deposition “is already running in production at 32nm,” said David Hemker, chief technology officer in the corporate technology development group at Lam Research. “The beauty of electroless is that it’s selective. It’s also more flexible.”

Electroless can deposit various materials, such as CoWP, nickel molybdenum phosphide (NoMP) and others. “Regarding the topic of electromigration, there are a lot of ways to address it,” Hemker said. “There are so many variants. It’s a trade-off between integration and performance.”

The electroless approach adds processing steps and increases wafer cost, according to a paper from IBM and Applied Materials at the recent International Interconnect Technology Conference (IITC) in San Jose, Calif. In the paper, the companies also described another capping layer option being developed at Applied Materials for use at 20nm and beyond.

In one possible approach, the capping layer could be handled by two separate machines. One tool provides the SiCN metal capping layer. A separate system deposits cobalt for the interface layer. The problem with this approach is that the structure could suffer from oxidation.

Applied proposes to combine the metal and the dielectric capping layer depositions in a single vacuum platform, according to the paper. The SiCN layer would be provided in one chamber, while the cobalt material would be deposited in a separate chamber.

In one experiment, patterned wafers were fabricated using 32nm CMOS test vehicles. This test was carried out in a copper structure with about 50nm wide lines and spaces as well as 1.5nm and 3nm cobalt films. This method had five to 10 times longer electromigration lifetimes, compared to a method without using cobalt. Module-level time-dependent dielectric breakdown (TDDB) testing was performed. It confirmed no line-to-line dielectric breakdown occurred from the in-situ capping process, according to the paper.

By David Lammers

Water is proving increasingly useful to the semiconductor industry. Just as immersion techniques came to the rescue of lithographers, ice could prove beneficial in removing small particles from wafers, speakers from Dai Nippon Screen (DNS) said at the Sematech Surface Preparation and Clean Conference (SPCC 2012) in Austin.

Ice is effective at dislodging small particles. (Source: DNS presentation at SPCC 2012)

Researchers at the central research laboratory of DNS (Kyoto, Japan) hypothesized that the expansive force which occurs when water freezes could nudge small particles stuck to a wafer’s surface. Water expands in volume by about 10 percent when it freezes, said Jim Snow, a chemist based at the DNS office in Dallas.

Early tests have shown that when water becomes ice it lifts particles adhering to a wafer surface. If water is frozen in a convex manner, i.e., from the inner part of the wafer out to the edge, there is no damage to the wafer. After the water is frozen with liquid nitrogen at minus 190° C, it is unfrozen with 80° C water. The result, said DNS CTO Soichi Nadahara, is an 80 percent particle removal efficiency (PRE), better than the company’s current state-of-the-art techniques.

While DNS has tested the ice cleaning method with 37nm poly lines and spaces, the test patterns were not very dense. “We believe this technique could be useful beyond 28nm and 20nm,” Snow said, adding that it is “a work in progress.”

Nadahara said “we are close to the beta or prototyping tool stage, and we will put it to the test somewhere at a customer site. We have been working on it internally for a couple of years.” The motivation, he said, is that ice seems more effective than other techniques at dislodging extremely small particles, with less damage than spray aerosols or megasonic techniques.

Cryogenic techniques have been used in wafer cleaning tools for some time. BOC earlier introduced its Eco Snow cleaning method, hitting the wafer with ice particles while rotating the wafer at different speeds.

FSI, for example, projects frozen nitrogen and argon at wafers at high velocity, with no side effects, said Jeff Butterbaugh, CTO at FSI International (Chaska, Minn.) DNS has used a two-fluid spray technique — most often nitrogen (N2) combined with water or SC1 chemistry for a 30 second period — using a tangential force in its Nanospray 2 product.

But as far as anyone could recall at the SPCC conference, the idea of freezing a wafer has not been tried before. Participants at the conference said many questions remain to be answered, including the impact on throughput, damage to sensitive structures, and the like.

One large wafer foundry is working with DNS on the tool, and participants at the conference that that foundry is most likely TSMC, which has pioneered single-wafer cleaning before. While working with SEZ (now part of Lam Research), TSMC engineers figured out that back end of the line (BEOL) cleaning with the ST250 chemistry at lower viscosity worked better in single-wafer chambers than in batch processing tools. TSMC’s move jump-started the move to single-wafer cleaning, and the major clean tool companies now offer tools with eight to 20 chambers.

Texas Instruments, which worked closely with TSMC and other foundries, had visibility into TSMC’s success with single-wafer cleaning, and began incorporating single-wafer cleaning tools into its DMOS 6 fab in Dallas at the 65nm generation, a participant at the SPCC conference said. Since then, single-wafer techniques have worked their way into the front-end of the line as well.

Nadahara said DNS estimates that single-wafer tools overtook sales of batch tools in 2008, accelerating as high-k/metal gate introduction began to pick up speed.

Ice seems to work better than dual-fluid cleaning techniques for the smallest particles. (Source: DNS presentation at SPCC 2012)