By Mark LaPedus
Over the years, suppliers of metrology equipment have managed to meet the requirements for conventional planar chips. But tool vendors now find themselves behind in the emerging 3D chip era, prompting the urgent need for a new class of 3D metrology gear.

3D is a catch-all phrase that includes a range of new architectures, such as finFET transistors, 3D NAND and stacked-die using through-silicon vias (TSVs). Although a few 3D-like devices have appeared in the market, many chipmakers are still developing these technologies and face several process control challenges.

“In our industry, a lot of segments are metrology-limited,” said Christopher Bencher, a member of the technical staff at Applied Materials. “Overlay metrology is the number one area where we are limited. There is also a challenge with 3D devices like finFETs and 3D NAND. You have to be able to characterize them in 3D.”

As with many fab tool markets, there is a disconnect between the rhetoric from chipmakers and equipment vendors. Process control tool vendors insist they are ready for the 3D era. In contrast, chipmakers say many of the existing metrology solutions are running out of steam.

For example, some 50% of the process steps in a fab are devoted to inspection and metrology alone. About 10% of those steps use the workhorse metrology tool in the fab—the critical-dimension scanning electron microscope (CD-SEM). With finFETs, the CD-SEM is being stretched to its limits. “Three quarters of the steps can be handled by a conventional CD-SEM,” said Eric Solecky, senior manufacturing engineer at IBM. “This percentage is growing. It’s that fraction for 3D information that we don’t have a solution today for an image-based tool.”

Near term, there are other challenges in process control. “The main gaps in general are next-generation defect inspection, next-generation charge particle imaging, and next-generation scatterometry profile metrology,” said Benjamin Bunday, senior technical staff member at Sematech. Longer term, the industry also lacks a process control solution for graphene, carbon nanotubes and directed self-assembly (DSA).

Metrology madness
Several tool types—AFM, CD-SEM and OCD—can handle most requirements for today’s planar chips. Atomic force microscopy (AFM) uses a tiny probe to enable measurements. The CD-SEM is used for top-down measurements. And used for CD and overlay, optical scatterometry (OCD) measures the changes in the intensity of light.

But the process control world changed in 2011, when Intel rolled out the industry’s first finFETs. Using a transmission electron microscope (TEM), Chipworks recently discovered that the traditional one-to-one ratio between structures and transistors doesn’t apply with Intel’s tri-gate technology. In fact, one transistor can have multiple fins—six or more—while one fin can have multiple transistors, according to Chipworks.

So for finFETs, a given metrology tool must measure and characterize the separate pieces in the structure, such as the gate, fin height, sidewall angle and others. Each of those parts also requires one or more separate measurements.

The question is which single metrology tool can handle all requirements for structures such as finFETs and 3D NAND? The answer: None of them. There is no silver bullet. “We are already in a deluge of data,” said Jason Osborne, senior systems design engineer at Bruker. “We’ve got many systems making multiple measurements on the same structures and not getting the entire answer off any one system.”

In one possible finFET metrology flow, the fin is measured by the CD-SEM or AFM, and then, the results are feed to the OCD tool. Another possible metrology flow involves the CD-SEM, OCD and a TEM. The TEM, a system that shoots a beam of electrons through a tiny specimen, is used to validate the OCD model. “What you are trying to do is make your scatterometry model more robust,” said John Allgair, senior member of the technical staff and Fab 8 patterning metrology manager at GlobalFoundries.

Intel, meanwhile, uses a combination of undisclosed tool technologies within its finFET process control flow. “We need all solutions,” said Adam Schafer, area manager of metrology and inspection at Intel. “We need to combine them.”

In process control, the biggest challenges for Intel can be summarized in three words—cost, noise and throughput. “Noise is one of our top problems. And it is really distinguishing the signal from the noise in any one of our techniques,” Schafer said.

Each tool type has its own set of issues. “If you are talking about CD-SEM, my CD measurement is traditionally top down. That’s not enough. I cannot control my processes with those CDs,” said Alok Vaid, senior member of the technical staff at GlobalFoundries. “Regarding OCD, it’s a solution, but it’s too complicated. So if you look at 14nm, 10nm and beyond, I don’t think the small dimensions are an issue for OCD. In fact, it can work in your favor. The problem is correlations.”

For AFM, the challenge is to measure finFETs in 10nm to 20nm spaces and characterize the profiles and shapes, he said. “We can’t leave optical tools such as ellipsometry out of the picture. Since everything is going 3D, now you want to measure those thicknesses and compositions on actual 3D structures,” he said.

The solutions
For some time, GlobalFoundries and others have been talking about the solution to the 3D problem—hybrid metrology. In this approach, separate tool technologies are used in a flow. The challenge is to put rival tool vendors in the same flow and tell the competitors to collaborate and share proprietary data with each other. “Let’s take an example. You have a CD-SEM supplier. You have an OCD supplier. And let’s say you want to overlap them and get my results. You can’t do that unless you get those guys to draw an algorithm together and get them to collaborate,” Vaid said.

While hybrid metrology is perhaps the wave of the future, tool vendors are also improving their respective technologies. For example, using Applied Materials’ CD-SEM, IBM conducted measurements in a theoretical gate-all-around finFET with silicon nanowires. In this experiment, “you see nice defined edges, even when you are beyond the resolution image,” said Ofer Adan, managing technology and marketing manager at Applied Materials. “So can we go beyond 14nm? What this work tells me is that a CD-SEM can go down to 6nm on a gate-all-around device.”

This is not to say the CD-SEM can handle all finFET requirements. “It cannot see whether or not there is an undercut. We need to work together with the OCD guys,” Adan said.

Overlay is another challenge and OCD is being stretched to the limits. KLA-Tencor recently unveiled a dimensional metrology system, which includes a new OCD technology based on a laser-driven source. “We think this is an inflection point for scatterometry,” said Andrei Shchegrov, director of advanced development at KLA-Tencor. “Our signal-to-noise gets a huge boost across a very wide range of wavelengths. We found the increased sensitivity due to the light source allows us to see things we couldn’t see before. It allows us to measure deep structures like high-aspect ratio 3D NAND flash.”

Despite the breakthroughs, the industry is still searching for new and better 3D metrology solutions. There are some promising candidates on the table. For example, a possible successor to the CD-SEM is helium-ion imaging. And X-ray scattering (CD-SAXS) could succeed OCD.

“The CD-SEM today, for the most demanding applications, cannot resolve 3D information,” said IBM’s Solecky. “So the question is, ‘Do you need 3D information on the smallest features?’ The answer is yes. Potentially, helium ion is the solution.”

Helium ion enables 3D images, but the technology also can damage a device. The industry is looking for ways to tweak the helium ion microscope, which would make it somewhat comparable to the CD-SEM. “Technically, this involves a lot of challenges to make (helium ion into) a CD-SEM kind of tool. Those are not unsolvable problems, but it requires a lot of investments,” said Bipin Singh, product manager for Zeiss, a supplier of helium ion scopes and other fab tools.

As a replacement for OCD, the industry is looking at CD-SAXS, an X-ray scattering technology based on a synchrotron radiation source. “If you want 3D structures, you can certainly do it with CD-SAXS,” said Joseph Kline, a materials engineer at NIST. “The main limiter for CD-SAXS is throughput. Most of the measurements with CD-SAXS are done with a synchrotron source. Clearly, we are not going to have something like this in the fab. We are trying to figure out how to get a new source and make it work.”

There are other major gaps in metrology. For example, the current buzz in lithography centers on DSA, but it’s unclear if the industry has a metrology solution. “Metrology needed for DSA is really not different than the metrology needed for the rest of the industry,” said Applied’s Bencher. “You need to measure the registration of the holes. Now, when you are defining all of your holes by a mask, things tend to shift systematically, at least within the mobile region of the wafer. So how do you obtain an overlay measurement when things on the local level are shifted randomly? That’s not clear. It requires a different way of thinking.”

By Mark LaPedus
Amid ongoing delays and setbacks, extreme ultraviolet (EUV) lithography and multi-beam e-beam have both missed the 10nm logic node. So for the present, chipmakers must take the brute force route at 10nm by using 193nm immersion with multiple patterning.

Now, it’s time to hit the reset button. For the 7nm node, chipmakers currently are lining up the lithographic competition. As before, with perhaps a slightly different twist, the candidates are EUV, multi-beam and the old standby, 193nm immersion with multiple patterning.

The same candidates also are competing for next-generation DRAM and NAND production. Nanoimprint is vying for a spot in NAND. But another option, directed self-assembly (DSA), could change the entire landscape if chipmakers can bring the technology from the lab to the fab.

Based on the delays with EUV, chipmakers could end up using 193nm with multiple patterning at 7nm. But they also are shuddering at the thought, as the costs and complexities for multiple patterning are enormous.

At 7nm, IC makers would prefer to use EUV or maskless for the critical or cut layers. But after a series of ongoing delays with these next-generation lithography (NGL) candidates, lithographers clearly are frustrated and beginning to run out of patience. “I am not happy with the progress of EUV,” said Burn Lin, vice president of research and development at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC). “I am also not happy with the progress of maskless, but it is making progress.”

Lin, considered the father of immersion lithography, is the industry’s biggest proponent for multi-beam e-beam. In addition, TSMC has installed an EUV scanner and recently invested in ASML to jumpstart technology. Intel and Samsung also have invested in ASML.

EUV or bust?
For now, chipmakers hope to put EUV in pilot production at the 10nm logic and next-generation memory nodes. At 7nm, EUV remains the leading NGL candidate, with maskless running a distant second. TSMC still has EUV and maskless running neck-and-neck, although both technologies could be used in production for different applications.

To date, the progress with EUV is mixed. ASML Holding’s production-worthy EUV scanner, the NXE:3300B, is ready to roll. The scanner has a numerical aperture (NA) of 0.33 and a resolution of 22nm (half-pitch). ASML plans to ship the first NXE:3300B in the second quarter of 2013, but the throughputs are far less than previously advertised.

The throughput issues are due to the source, which is being developed by Cymer. The development of the EUV source has been “more difficult than what we anticipated,” said David Brandt, senior director of EUV marketing and business development at Cymer, which recently was acquired by ASML.

Last year, Cymer promised to ship a 100 Watt source by the end of 2012. So far, in the lab, Cymer has demonstrated the ability to generate 40 Watts and 50 Watts of EUV power. A 55 Watt source translates to an EUV throughput of 43 wafers an hour.

Cymer’s EUV source is based on laser-produced plasma (LPP) technology. In LPP, plasma is generated by a laser pulse hitting a target. The source also makes use of a pre-pulse laser and a master-oscillator power amplifier (MOPA), which will help generate more EUV power.

By the end of 2013, Cymer hopes to ship an 80 Watt source with a MOPA upgrade, enabling an EUV throughput of 58 wafers per hour. By 2015, ASML hopes to ship an EUV scanner with a 250 Watt source, which translates to a throughput of 126 wafers an hour.

Two other vendors, Gigaphoton and Xtreme, are racing against Cymer to deliver a 250 Watt EUV source. So far, Gigaphoton has achieved an EUV light output equivalent to a maximum of 20 Watts, said Yuji Minegishi, manager of the sales division for the company.

By 2015 or so, the IC industry is expected to be at the 10nm node. EUV is a 13.5nm wavelength technology, meaning chipmakers must use multiple pattering with EUV. With self-aligned double patterning (SADP), ASML’s NXE:3300B has demonstrated resolutions down to 9nm.

But if EUV is used in conjunction with double patterning, the EUV scanner itself will require twice the source power than before—or about 500 Watts, contends TSMC’s Lin. However, to deal with the resists, Yan Borodovsky, a senior fellow and director of advanced lithography at Intel, recently said that EUV source power needs to be in the range of 1,000 Watts.

Another way to extend EUV is by moving to higher NAs. For example, with an NA of 0.45, an EUV scanner can print 9.5nm feature sizes, but the image contrast drops, according to Zeiss. To address that problem, the current 4X magnification scheme can be increased to 6X or 8X.

Current EUV scanners with 4X magnification support standard 6-inch photomasks. A 0.45 NA lens with 6X magnification may improve EUV resolutions, but in some cases, that solution may require the photomask industry to move to a new and larger 9-inch mask size. In other words, photomask tool makers must develop new equipment.

“I don’t think we should give up on 4X just yet,” said Harry Levinson, senior fellow and manager of strategic lithography technology at GlobalFoundries, at the recent SPIE conference. “We may be able to extend 4X a bit. Maybe for a later node, we can go for more of these radical changes, such as larger format masks and higher lens reductions.”

Still, Levinson urged the industry to explore the idea of moving toward 9-inch masks, a move that is less painful than some might think. To support 9-inch reticles, the optics and other critical parts of a photomask tool will not need to be re-engineered, but vendors will need to develop new handling systems, he said.

In another scenario, EUV with 8X magnification could support 6-inch masks, but scanning would be done in a smaller field size. “You put this all together and we get less than half the throughput at 8X than 4X,” he said. “This is not an attractive situation.”

Beam me up
Amazingly, multi-beam e-beam or maskless lithography has seen more delays than EUV. Summarizing the state of multi-beam, Serge Tedesco, lithography program manager at CEA-Leti, said: “It’s a shame. There is a lack of support from the industry, when you compare it to the EUV side. This is one of the reasons why the technology is not mature yet.”

In 2002, for example, Mapper Lithography claimed that within three years it would ship its 13,000-beam tool for the 45nm node. As it turned out, Mapper’s initial production tool, which only will consist of 1,300 beams, won’t ship until the end of 2013.

Two other vendors, KLA-Tencor and Multibeam, are separately developing multi-beam tools. In another major move, Golden Gate Capital, a venture capital firm, recently sold its e-beam company, Vistec, to two different companies.

In one transaction, Raith recently acquired Vistec’s Gaussian e-beam unit, called Vistec Lithography. Vistec Lithography continues to specialize in conventional direct-write applications in the aerospace and military arena.

In a separate move, the Heidenhain Group recently acquired Vistec’s variable shaped beam (VSB) e-beam unit. That operation, Vistec Electron Beam, sells a single-beam e-beam tool based on VSB technology. It also is working on a multi-beam tool based on a variant of VSB called multi-shape beam (MSB), said Ines Stolberg, manager of strategic marketing at Vistec Electron Beam.

Given that MSB is based on proven VSB technology, Vistec Electron Beam may have an advantage over rival multi-beam approaches, said Hans Pfeiffer, principal of HCP Consulting. “This has a greater chance for success,” Pfeiffer said.

Multi-beam’s future still remains unclear, as only two entities, CEA-Leti and TSMC, are basically propping up and supporting the entire industry. CEA-Leti recently launched the Imagine Program, a multinational consortium aimed to bring maskless into production.

TSMC is working with both KLA-Tencor and Mapper. For years, KLA-Tencor has been developing what it calls Reflective Electron Beam Lithography (REBL). REBL makes use of a six-wafer rotary stage and a linear column. The 75-100-KeV design also consists of a CMOS-based digital pattern generator module, a 4,096 x 247 pixel array unit that enables more than 1 million beams at full current.

When operating with the rotary stage, REBL has demonstrated the ability to print 120nm half-pitch resolutions, a modest effort at best. In a static mode, the tool demonstrated 28nm resolutions, said Thomas Gubiotti of KLA-Tencor. A high-throughput version of REBL is due out in 2015.

Rival Mapper is developing a multi-beam tool, which is supposed to consist of 13,260 beams with sub-25nm resolutions. However, the first production tool, dubbed the Matrix 1.1, will consist of only 1,300 beams and a throughput of 1 wafer an hour, according to CEA-Leti. In June, CEA-Leti is expected to receive one of the first Matrix 1.1 tools. First exposures for the Matrix 1.1 are slated for the fourth quarter of 2013.

By 2015 or 2016, the overall goal is to cluster 10 Matrix systems together, enabling an overall throughput of 100 wafers an hour. In terms of the cost-of-ownership (COO), the Matrix runs €1 million for a system with a throughput of 2 wafers per hours, €5 million for 10 wafers an hour, and $50 million euros for a 10-cluster unit.

By Mark LaPedus
The shift toward the 20nm node and beyond will require new and major breakthroughs in chip manufacturing.

Most of the attention centers around lithography, gate stacks, interconnects, strain engineering and design-for-manufacturing (DFM). Lost in the conversation are two other critical but overlooked pieces in the manufacturing puzzle—wafer inspection and metrology.

For years, inspection and metrology tool vendors have managed to stay one step ahead of the defect curve. But as chipmakers migrate toward finFETs, 2.5D/3D chips and other complex structures, process control will become even more challenging and costly.

In fact, three key process control tools, CD-SEMs, brightfield defect inspection and optical scatterometry, may soon run out of steam, prompting the need for a new class of 3D metrology gear. “When we get to the 14nm node, we may be able to get by with what we have,” said John Allgair, senior member of the technical staff and Fab 8 patterning metrology manager at GlobalFoundries. “As you get to 10nm, we might need a new technology.”

Next-generation 3D metrology tools exist to some degree, but the industry must make substantial investments to bring these technologies into production. And that’s precisely where the problem, and tension, exists between chipmakers and tool vendors. To develop new tools, equipment vendors want a bigger piece of the R&D pie and want customers to assume more of the risk.

“Different business models are definitely needed,” said Chris Talbot, senior director of strategic licensing at Applied Materials. “As the industry consolidates, with 450mm and EUV on the horizon, the amount of R&D that needs to be done not just in metrology and inspection, but right across the equipment industry, is enormous.”

One idea is to replicate ASML Holding’s recent and blockbuster business deal. Intel, Samsung and TSMC recently invested millions of dollars in ASML to speed up the development of extreme ultraviolet (EUV) lithography and 450mm tools. The three chipmakers also took minor stakes in ASML.

“The investments made by Intel and others in ASML are huge to solve an enormous problem,” Talbot said. “This is maybe one of the things we need to look at for other segments of the industry.”

Wanted: New business models
It’s unlikely that the inspection/metrology industry, or other fab tool sectors, will garner the same level of funding as the ASML deal. Lithography is considered the key manufacturing technology in IC scaling, and it will require a substantial investment to propel the development of EUV and 450mm lithography tools.

In the process control sector, the industry is providing substantial funding to KLA-Tencor, Zeiss and others for the development of EUV mask inspection tools. But beyond EUV, the industry may need to rethink the R&D funding model.

For years, chipmakers, consortia, venture capitalists and even governments have provided various levels of funding to equipment vendors for the development of new fab tools. Generally, the fab tool vendors themselves have assumed a larger percentage of the R&D bill and assumed more of the risk.

Today, however, tool vendors can no longer afford to develop a system on a whim and foot the R&D bill. The development costs, and the risks, are too high. After all, only a handful of chipmakers buy advanced tools today.

As before, there are no guarantees that a proposed tool will move into production. At times, equipment makers also fail to deliver the promised goods. But the real problem surfaces when a chipmaker demands a new system for a future node. An equipment maker complies and develops the system.

Then, in some cases, the IC maker decides not to insert the proposed tool. Instead, the company ends up extending the current technology. For this reason and others, the equipment maker ends up holding the bag. “If you look at the last 10 years, there are very few examples where a technology that we talked about was actually converted into a tool that we could put in our fabs,” acknowledged Alok Vaid, senior member of the technical staff at GlobalFoundries.

So, the time is ripe for a new R&D and risk-sharing model, although don’t look for an immediate change. “The industry has invested in time, resources and materials in process control,” said GlobalFoundries’ Allgair. “You’ve seen some investments through research consortiums. But we’re probably reaching the point where it needs to extend a little bit further than that. We should try to explore some different funding models.”

Given the enormous risks involved in tool development, chipmakers also must open the lines of communication and do a better job in conveying the exact types of technologies needed for a given node, he added.

Wanted: New metrology tools
Chipmakers are finally addressing the problems with the current R&D funding model, as some of today’s process control tools may soon hit the scaling wall. Fortunately, there are some promising next-generation candidates on the table. For example, a possible successor to the CD-SEM is helium-ion imaging; meanwhile, multi-beam e-beam inspection could displace brightfield inspection. And X-ray scattering (CD-SAXS) could succeed optical scatterometry.

In one area, Applied and KLA-Tencor are among the major suppliers of optical-based brightfield inspection tools. Used to find defects during transistor fabrication, brightfield is a technique that collects light reflected from a defect. In turn, the defect appears dark against a white background. Brightfield is often used in conjunction with single-beam e-beam inspection, which detects even smaller defects.

As chips move to finer feature sizes, brightfield may have trouble seeing smaller defects. “It’s believed that 20nm is a critical particle size in which scattering falls off,” said Benjamin Bunday, senior technical staff member at Sematech. “E-beam inspection can see 5nm particles. But, of course, the throughput is too slow.”

Still, the death of optical and single-beam e-beam inspection is greatly exaggerated, said Mingwei Li, director of product marketing at KLA-Tencor. “Even with today’s wavelengths in optical inspection, we are detecting defects in the range of 10nm,” Li said. “We are not very far off with the ITRS roadmap, which specifies 5nm defects. We also think e-beam has a place.”

One possible successor to brightfield is multi-beam e-beam inspection technology. Multiple beams can boost inspection throughputs, but the technology is difficult to develop and control.

One startup, Multibeam, is developing a 100-column e-beam inspection system. Multibeam’s technology will not replace today’s optical and single-beam e-beam inspection, but rather it is a complementary approach, said David Lam, a venture capitalist and chairman of Multibeam. “We’re focusing on detecting small physical defects that are almost indistinguishable to noise,” Lam said.

Perhaps the biggest challenge for startups like Multibeam is clear—getting funding. “It is indeed very difficult to get funding,” Lam said. “Semiconductor equipment, in particular, is considered passé. It’s something that’s takes too much money. You can’t go IPO. It’s a very unattractive investment for investors.”

Multibeam is not looking for a handout, but the startup needs some backing to advance its tool. “I don’t think it will take $3 billion or $4 billion in funding like EUV. I’d say tens of millions of dollars,” he added.

Besides a new inspection technology, the IC industry is also looking for a next-generation scatterometry tool. Scatterometry analyzes changes in the intensity of light in a device, but the shift towards finFETs presents a challenge for the technology.

As a replacement, the industry is looking at CD-SAXS, a technique that uses a shorter wavelength to measure structures. The downfall with CD-SAXS is that it makes use of a synchrotron radiation source. “CD-SAXs is too slow,” said GlobalFoundries’ Allgair. “We need a new high-brightness source and faster measurement times.”

Another tool under stress is the scanning electron microscope (CD-SEM), which measures critical dimensions in chip structures. “The CD-SEM today, for the most demanding applications, cannot resolve 3D information,” said Eric Solecky, senior manufacturing engineer at IBM.

There is one solution on the table. In 2006, Carl Zeiss acquired Alis, a supplier of helium ion microscopy. The technology was supposed to provide better resolutions than CD-SEMs. “We thought we would go to the semiconductor market and solve all of their problems,” said Bipin Singh, product manager for Zeiss. “It turns out the traditional CD-SEM was good enough. The list price for a helium ion microscope was $2.1 million. The industry wasn’t willing to bear the costs.”

Last year, Zeiss decided to focus its helium ion microscopes for nanotechnology fabrication. But as the IC industry moves towards finFETs, some are once again looking at helium ion as a possible replacement for CD-SEMs.

Applied, Hitachi and other CD-SEM suppliers are not throwing in the towel just yet. “The case for helium ion is a bit fuzzy,” said Applied’s Talbot. “Conventional CD-SEMs are getting older, but they are still doing the job and are extendable.”

By Mark LaPedus
Gartner has revealed its top predictions for IT and strategic technology. Among them: By 2014, three of the top five mobile handset vendors will be Chinese; by 2015, big data demand will reach 4.4 million jobs globally, but only one-third of those jobs will be filled; and by 2016, wearable smart electronics in shoes, tattoos and accessories will emerge as a $10 billion industry.

With about 21 months remaining until publicly traded U.S. component manufacturers must disclose their usage of conflict minerals to the government, the electronics industry appears to be unprepared, according to iSuppli. Conflict minerals are defined as those mined in locales of armed conflict and human rights abuses. These minerals, such as tin, tantalum, tungsten and gold, are used in a wide range of components across the electronics supply chain.

According to IDC, end users’ concerns over foreign governments’ access to cloud data, particularly data stored in the U.S., are misplaced. “Scare stories over the Patriot Act abound, but they are fallacious,” said David Bradshaw, IDC research manager for European public cloud services, on IDC’s site. “The Patriot Act is nothing special, indeed data stored in the U.S. is generally better protected than in most European countries, in particular the U.K.”

Hans Mosesmann, an analyst with Raymond James, said: ”While the Street seems to view AMD as imminently going out-of-business we would caution investors otherwise. AMD’s strategy announcement next week (October 29th) will likely be the unveiling of an ARM 64-bit strategic collaboration. With SeaMicro’s world-class fabric, AMD’s strategic positioning becomes quite powerful. We also remind investors that AMD knows the server market quite well, it has an x86 license and it just hired Apple’s processor architect.”

STMicroelectronics reported its third quarter results. The company also cut jobs and reduced its capital expenditures to about $500 million this year. During the quarter, ST-Ericsson’s NovaThor L8540 LTE ModAp platform and the FD-SOI variant of this application processor product were taped out and sample wafer fabrication started. Samples of both products are expected to be available during Q4. STMicroelectronics will fab the chips. ST-Ericsson is a 50-50 joint venture between Ericsson and STMicroelectronics.

During a conference call to discuss its results, executives from STMicroelectronics remained bullish about its efforts with FD-SOI.

TSMC reported mixed results in the quarter. http://www.tsmc.com/english/default.htm “TSMC reported 3Q results and guided 2013 CapEx to $8.0 billion to $8.5 billion, versus $8 billion in 2012, below our estimate of $9 billion. We believe this is consistent with a weakening macro backdrop, coupled with expectation for Apple business to truly ramp in 2014, as opposed to 2013,” said C.J. Muse, an analyst with Barclays Capital. TSMC is expected to make applications processors at the 20nm node on a foundry basis for Apple.

TSMC has purchased 14 hectares of land near Hsinchu, Taiwan. TSMC plans to build an R&D facility for 450mm wafers, as well as 7nm process development, according to TSMC Chairman Morris Chang on Seeking Alpha. Chang also discussed TSMC’s outlook, CapEx, and other topics.

In partnership with the Semiconductor Research Corp. (SRC), ATIC will support 14 research initiatives over the coming year spanning Khalifa University, UAE University, American University of Sharjah, Masdar Institute and New York University Abu Dhabi. ATIC owns a majority stake in GlobalFoundries.

Mentor Graphics has released a new product in the HyperLy-nx suite. h In addition, Kalray has completed its new 160 million gate, 3 billion transistor multi-purpose processor array IC using a Mentor’s functional verification, physical design and verification, and design-for-test flow.

AMD announced its collaboration with Microsoft for more than 125 Windows 8-based PC designs from OEMs, including ASUS, Dell, Fujitsu, HP, Lenovo, Samsung, Sony, Toshiba and more.

During a recent press event at the company’s new headquarters in San Jose, Calif., Maxim discussed integration and other trends in analog. The company also revealed a 90nm process technology and discussed a new class of power system-on-a-chip (SOC) products. And the company revealed its directions, including a strong push in the mobility segment.

Most mobile SoC GPUs were shipped by Qualcomm in the first half, according to Jon Peddie Research.

Texas Instruments announced third-quarter revenue of $3.39 billion and net income of $784 million. “For 4Q ‘12, TI guided revenues to fall 6% to 13%. Annual Capex guidance was cut by $200 million to $500 million, as TI dials back additional capital spending, commensurate with the environment,” said Craig Berger, an analyst with FBR.

Broadcom said revenue for the third quarter of 2012 was $2.13 billion. This represents an increase of 8.0% compared with the $1.97 billion reported for the second quarter of 2012 and an increase of 8.7% compared with the $1.96 billion reported for the third quarter of 2011. “Broadcom reported robust 3Q ‘12 results and gave 4Q ‘12 guidance near Street estimates, better than most peers,” Berger said.

KLA-Tencor reported mixed results. “KLA-Tencor’s results for the first quarter of fiscal year 2013 reflect today’s challenging demand environment for the wafer fab equipment industry,” said Rick Wallace, president and CEO.

It was a tough quarter for ATE giant Teradyne. The company reported Q3 revenues of $463 million, up 35% from the same period in 2011. But Q4 orders are down 61% from this quarter  quarter and Q4 revenue is forecast at between $235 million and $260 million.

By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss the current and future photomask manufacturing challenges with Franklin Kalk, executive vice president and chief technology officer at Toppan Photomasks, one of the world’s largest merchant mask makers.

SMD: The outlook for the photomask industry is for 2% growth in 2012. Do you agree with that?
Kalk: That’s probably about right. If you look back 10 to 20 years, the mask business did not follow the semiconductor business. The cycles did not exactly coincide. Typically, the mask business has seen more tempered cycles. In the past, the phases actually lagged the semiconductor industry. But as the supply chain tightened from the mid-1990s into the mid-2000s, the cycles coincided. So now, when semiconductors are up, masks are up. Right now, in semiconductors, things are a bit soft. In masks, you can say the same thing. Right now, I would not call it great, but it’s not horrible.

SMD: What are the trends for photomasks at the new nodes?
Kalk: In the mature nodes, you see a lot of activity. As you get to 130nm, there is still a lot of activity. In 90nm, there is a strong dip. There are not that many masks built at 90nm. At 65nm, it picks back up again; 45nm and 40nm are still ramping. 32nm and 28nm are just really starting to take off. Intel is manufacturing at 22nm. We are starting to see increased activity at 20nm. 14nm is really in development.

SMD: What are the trends in mask costs?
Kalk: There is a lot of misinformation about mask costs out there. If you take any node, the mask sets will start out at a very high price. But within a year or two, the price will drop to maybe one-half the introductory price. That’s because of yield learning and we start getting better utilization of our tool kit. And then there’s competition. So the prices will drop from completion.

SMD: How do the merchant mask makers prepare for a new node?
Kalk: We have to get our process ready about 18 months in advance of the wafer fab beginning its production ramp. We need a fixed process, meaning the OPC signature is set and the CD signature on the mask is set. During that 18-month period, we spend a lot of time doing optimization of defect quality and maybe improving the CDU. That hasn’t been done for 14nm. That kind of tells you 14nm is a couple of years out, for us anyway.

SMD: What is the demand mix for photomasks today?
Kalk: Historically, design activity in logic has been huge. Memory design activity has been relatively small. If you look at the total number of masks being produced for memory and logic, there is no comparison. In consumer applications, how many chips go into a cell phone? Only so many. The number we throw around is maybe 500 masks used to make an iPhone. But the number of types of chips is really not that big.

SMD: What are the lithography trends from a mask maker point of view?
Kalk: We have a history in this industry of pulling in design rules and pushing out technologies. For example, people talked about having 193nm lithography in 1999 and 0.18-micron technology in 2001. But in fact, what happened was the exact opposite. 0.18-micron was pulled into 1999 or so. And 193nm was pushed out into the early 2000s. 193nm didn’t come in until maybe 90nm. In other words, we push out these new technologies, because they are riskier and they tend to cost more to insert. Now, people are seeing continued delays in EUV. That’s a natural for us in the mask industry.

SMD: How do you envision complementary lithography playing a role in the mask business?
Kalk: Double-patterning is already in use. It will go to triple- or quadruple-patterning. I’ve seen numbers go higher than that. Certainly, 14nm will be multi-patterning. 10nm in all likelihood will be multi-patterning as the first solution. Even when EUV comes in, it will be in a multi-patterning environment. Let’s imagine the 10nm node. If you’re patterning with just 193nm, maybe you have a grating layer and several cut layers. The challenge of doing all of the cuts on a single mask is just too great at that node with 193nm. But if you do it with a single EUV mask, we may be looking at then replacing say two or three, or maybe more, 193nm immersion cut layers with a single EUV layer. But the original grating layer could be a 193nm layer.

SMD: What about multi-patterning?
Kalk: A lot of people talk about how multi-patterning is great for the mask maker, because there are more masks. But it’s not all that simple. You have materials, multiple writing steps and more time involved in the various processes. And it’s not very easy to make two masks cost the same as one mask.

SMD: What about mask inspection?
Kalk: Inspection has always been a high-cost module. That will probably remain the highest cost module.

SMD: Any progress with the resists?
Kalk: When you think of resolution, line-edge roughness, and resist speed, it’s gets really interesting. Today, our resists are at 15 to 20 microcoulomb-per-square-cm sensitivity. But if we’re going to meet the demand statement at 10nm, we’re probably going to need 70 to 100 microcoulomb-per-square-cm. So we’re going to need five times the dose, but maintain the current write times. We’re going to be hard pressed to do that unless a fairly radical change is made to the writing time.

SMD: What are your thoughts on EUV?
Kalk: Every disruptive technology has extreme advocates and extreme detractors. I’m neither. I’m a pragmatist. If EUV succeeds, I want to sell EUV masks. If it doesn’t, I’ll sell whatever is in its place. It’s going to come down to cost. I think the technical hurdles are considerable, but I think they can be overcome. It is going to come down to whether it is cheaper than the alternatives. Right now, the only alternative that is well developed is immersion and multi-patterning. Is EUV delayed past 10nm? I suppose I could see that happening. I guess it depends on the source development. That’s the driving force in EUV right now. It used to be the EUV mask was the big deal. Everyone worried about mask defectivity. But once the EUV source issues boiled to the top, everyone seems to have forgotten that we still have a mask to build.

SMD: What are the trends for EUV inspection tools? And will they go in the mask shop or elsewhere?
Kalk: You will need inspection, repair, clean and verification AIMS tools. Where do those go? Do they go in the wafer fab? For EUV, probably. Unless you have a mask fab that’s pretty close in proximity, it may be prudent to put a fair complement of tools in the wafer fab. The AIMS tool should be ready when high-volume EUV manufacturing is ready. The cleaning tool will be there. The repair tool will be there. For actinic inspection, it depends on how long EUV itself is delayed. Two or three years ago, we were thinking the EUV inspection tool would not be ready. But if EUV continues to see some delays, the inspection tool could be ready then. KLA-Tencor is predicting something like 2016 for the first tools.

SMD: To ensure that 450mm and EUV are on time, Intel, TSMC and Samsung recently invested in ASML. Are we seeing a new business model evolving in the equipment industry, where IC makers invest in fab tool vendors?
Kalk: I wouldn’t be surprised to see more of this in the near future. It’s not unheard of. Three years ago, both Dai Nippon Printing and Toppan Printing invested in (e-beam vendor) NuFlare. We each own about 8%-plus of NuFlare. Let’s say you have a 450mm fab at 10nm. For 450mm, you still need to have 193nm, 248nm, and a little bit of 365nm and maybe EUV. ASML has 193nm and 248nm platforms on 300mm, but they don’t have anything on 450mm. If they have to have three wavelengths on 450mm, they have to take everything and convert it to 450mm. It’s not just one machine, but it’s a whole family of equipment. It’s not trivial. It’s really difficult.

SMD: Any thoughts on directed self-assembly (DSA)?
Kalk: I think it has great potential. But if you look at where all of the papers are coming from, they are still out of universities and research labs like IBM. That’s great, but it shows you the state of the work. At some point, it has to transition into the commercial companies. You see a little bit out of TEL. The class of materials available is still relatively limited. It’s straightforward in that technology to make it one-dimensional. But in term of doing the cuts, this is more difficult. What’s interesting to me is if you look at multiple patterning, the grating layer is not the challenging layer. It’s the cut layers that are challenging. The hard stuff for DSA is the same as it is for standard 193nm immersion. Making the grating layer with 193nm is pretty well understood and doable. You can use spacer technology or spacer-spacer and get down to 10nm lines and spaces pretty easily. Is DSA solving a problem that has already been solved or not? If it can be done cheaper, then okay. Until it solves the randomness issue and cut layer, DSA will face the same problem everything else has.

By Mark LaPedus
The shift towards the 28nm node and beyond has put the spotlight back on the interconnect in semiconductor manufacturing.

In chip scaling, the big problem in the interconnect is resistance-capacitance (RC). Another, and sometimes forgotten, issue is electromigration. “Electromigration gets worse in device scaling,” said Daniel Edelstein, an IBM Fellow and manager of BEOL technology strategy at IBM Corp. “Some of the issues on the table are becoming limiting problems.”

Electromigration, which can cause voids and failures in a device, refers to the displacement of the atoms as a result of current flowing through a conductor. To suppress electromigration in the interconnect part of the equation, chipmakers typically use a capping or etch stop layer of material on a dual-damascene structure.

But some warn the conventional capping layer of materials in advanced designs—silicon carbon nitride (SiCN) and a copper alloy—could run out of steam at 20nm and beyond, prompting the need for a new solution. “At 20nm, customers will have to bite the bullet,” said Sree Kesapragada, global product manager for metal deposition products at Applied Materials. “Copper does not adhere very well to the dielectric layer. Cobalt is needed for the nanoline.”

In fact, there are several new capping layer options for advanced designs. One solution is to somehow extend the current materials. Another option is Lam Research’s electroless deposition technology, which deposits cobalt-tungsten-phosphide (CoWP) or a related material. This is already in production in at least one foundry vendor at 32nm.

And a newer option is Applied Materials’ in-situ metal/dielectric tool technology for use in depositing cobalt and SiCH. Cobalt-related materials are said to boost electromigration lifetimes by up to hundredfold.

Electromigration in the interconnect
It’s still too early to tell which capping technology will prevail in the long run. The capping layer process takes place during the formation of the interconnect in the dual-damascene flow. The interconnects themselves are becoming more compact at each node, causing unwanted RC. To address the problem, the industry must make advances on two fronts: metallization and low-k dielectrics.

The dual-damascene flow includes the following steps: via and trench patterning, barrier layer and copper seed deposition, electroplating and chemical mechanical polishing. Using a deposition technique, the final step in the process is the addition of a capping layer. This is because the interface between the copper line and capping layer is susceptible to electromigration.

Prior to the 90nm node, IC makers generally used silicon nitride (SiN) as the capping layer material. At 130nm and 90nm, chip makers also moved to low-k materials. The trouble was that the dielectric constant of SiN was more than double that of low-k films, which impacted the overall effective k value of the stack.

This, in turn, prompted chipmakers to switch to SiCN materials for the capping layer as a means to reduce capacitance at or around 90nm. SiN has a dielectric constant of 7.0, while SiCN is around 5.0.

Subramani Kengeri, head of advanced technology architecture at GlobalFoundries, said electromigration became more of an issue for the interconnect at the 45nm and 40nm nodes. So to help suppress electromigration, many chipmakers deposited a tiny percentage of a material such as manganese in the copper seed layer using physical vapor deposition (PVD). Manganese or other types of alloys work in conjunction with SiCN. In effect, these types of alloys “find their way to the top and act like a capping layer,” said IBM’s Edelstein.

At 32nm and beyond, chipmakers would prefer to extend SiCN and the alloy approach without moving to new tool technologies and materials. The problem with this approach is that some of the alloys “diffuse and some of them don’t,” said Applied’s Kesapragada.

The next big material, cobalt, has been proposed because it adheres well to copper. In a structure, IC makers would still use SiCN as the outside metal capping layer. A thin layer of cobalt serves as the interface between the copper and SiCH. Cobalt helps to suppress electromigration, but it adds cost to the equation.

New solutions
Cobalt is getting some traction. For its 32nm processors, Advanced Micro Devices is using a CoWP capping layer, based on Lam Research’s electroless deposition tools. These tools reside within GlobalFoundries, which is making the processors on a foundry basis for AMD.

Electroless is a process of depositing a material with the aid of a chemical reducing agent. The origins of Lam’s electroless tools can be traced back to Blue29, a startup that developed this technology. One of Blue29’s original investors was KLA-Tencor.

In 2004, KLA-Tencor and Dainippon Screen Manufacturing Co. Ltd. formed a joint electroless tool venture and invested in Blue29. But in 2006, KLA-Tencor exited the venture, and subsequently, Lam Research acquired Blue29’s intellectual property.

Electroless deposition “is already running in production at 32nm,” said David Hemker, chief technology officer in the corporate technology development group at Lam Research. “The beauty of electroless is that it’s selective. It’s also more flexible.”

Electroless can deposit various materials, such as CoWP, nickel molybdenum phosphide (NoMP) and others. “Regarding the topic of electromigration, there are a lot of ways to address it,” Hemker said. “There are so many variants. It’s a trade-off between integration and performance.”

The electroless approach adds processing steps and increases wafer cost, according to a paper from IBM and Applied Materials at the recent International Interconnect Technology Conference (IITC) in San Jose, Calif. In the paper, the companies also described another capping layer option being developed at Applied Materials for use at 20nm and beyond.

In one possible approach, the capping layer could be handled by two separate machines. One tool provides the SiCN metal capping layer. A separate system deposits cobalt for the interface layer. The problem with this approach is that the structure could suffer from oxidation.

Applied proposes to combine the metal and the dielectric capping layer depositions in a single vacuum platform, according to the paper. The SiCN layer would be provided in one chamber, while the cobalt material would be deposited in a separate chamber.

In one experiment, patterned wafers were fabricated using 32nm CMOS test vehicles. This test was carried out in a copper structure with about 50nm wide lines and spaces as well as 1.5nm and 3nm cobalt films. This method had five to 10 times longer electromigration lifetimes, compared to a method without using cobalt. Module-level time-dependent dielectric breakdown (TDDB) testing was performed. It confirmed no line-to-line dielectric breakdown occurred from the in-situ capping process, according to the paper.

By David Lammers

KLA-Tencor introduced a clustered defect inspection/metrology/review system, called CIRCL, which performs inspection and metrology on both the front and back sides of the wafer, incorporating wafer edge inspection as well.

Designed for operation in lithography, outgoing quality control (OQC), and other process modules, CIRCL monitors the front side, back side, and edges of multiple wafers in parallel. Prashant Aji, senior director of product marketing at the company’s Swift division, said the CIRCL tool “does with parallel processing what had previously been running serially.”

Circl offers parallel, rather than serial, operations. (Source: KLA-Tencor)

Seven wafers can be inside the tool at any one time, with four undergoing various forms of inspection, resulting in an estimated 25 percent throughput improvement over today’s serial inspection tools. Fabs also save on space by having one cluster tool in place, and can configure the modules for the needs of a particular logic or memory process.

After lithographic patterning and development, CIRCL inspects for macro defect types on the front side of the wafer, including particles, defocus defects spanning several die, and full-wafer defects such as missing resist. CIRCL can handle 155 wafers per hour of front side inspection. Aji said fabs often will team one CIRCL tool with three scanners, checking eight wafer samples in a 25-wafer lot, for example.

The Circl tool provides faster root cause analysis. (Source: KLA-Tencor)

CIRCL offers a 2X improvement in macro defect inspection capabilities, with a 5-µm detection capability compared with the 10-µm limit on the company’s LDS 3300 inspection tool. As the tool zooms in to hotspots for micro inspection, the capability improves to one-half the design rule, he added.

CIRCL provides full coverage of the edge, including the bevel and backside, Aji said. It performs detection and binning of the edge defects, which can migrate to the die area and cause yield loss, and handles edge bead removal (EBR) metrology. Edge profile measurements identify excursions that can result in water bead leakage or film delamination during immersion lithography.

Back side inspection is becoming more important as design rules continue to shrink. A small defect on the backside of the wafer can create an out-of-focus image on the front side, particularly with the depth of focus seen at deep submicron linewidths.

“With EUV lithography, more backside inspection will be necessary. EUV is done in vacuum, and without a pellicle, so backside defects from the chuck can become more important,” Aji said.

CIRCL uses directed sampling, in which data from one surface is used during inspection of the wafer’s other surfaces. KLA-Tencor supports automated high-resolution optical defect review and automated defect classification, “helping engineers identify the defect source quickly.”

The total available market for macro inspection tools is $100-120 million, a TAM that is growing as semiconductor vendors incorporate more immersion lithography steps and the number of critical layers increases, he said.

Oreste Donzella, general manager of the SWIFT division at KLA-Tencor, said the clustered architecture offers “an ability to leverage several defect, inspection, metrology and review technologies in concert, to help our customers recognize and resolve excursions as they strike.”

By Marc D. Levenson

Does the transition to 450mm wafers offer the ultimate opportunity to switch to maskless lithography (ML2)? That was the suggestion made by Burn Lin, senior director of micropatterning at TSMC in his keynote for the SPIE Alternative Lithography Conference in San Jose Feb. 14. The 450mm transition would appear to require expensive development of a variety of patterning tools and resists if a conventional mix-and-match strategy were employed. Since multi-electron beam lithography can be used to write any layer, one 450mm e-beam direct-write tool could pattern them all, and for 30% lower cost at any production volume. Only one machine would have to be engineered and only a few resists formulated.

The architecture of Lin’s tool would be similar to a multi-column version of KLA-Tencor’s ReBL system, with several wafers on a rotating stage and up to 36 columns, each supporting one million independent beams. Direct write with continuous stage motion on all levels would allow devices to break out of the standard 26 x 33mm field, with consequent efficiency improvements. The issue, as always in electron beam lithography, would be throughput. Lin claimed that could be addressed by scaling the number of columns and stages.  Mass production would reduce tool cost to $500,000 per wafer per hour. Lin claimed that by the time 450mm came along, the CD would be 10nm or below, making his suggested ML2 architecture the least challenging and most economical of the available options.

Other advocates of ML2 and alternative lithographies seemed less visionary. The KLA-Tencor presentations on ReBL emphasized the steps needed to re-target the DARPA-funded 45nm program towards commercial viability at 16nm or so in 2015. Regina Freed described how returning to linear stage motion reduced risk and complexity with the lower stage velocity needed for 1nm CDU and overlay at 16nm. There still could be 36 columns and the throughput target  would be 100 wph.

Mark McCord of KLA-Tencor described the hardware evolution towards high-volume manufacturing (HVM). Going to linear stages simplified the data channel, allowing re-use of data, but still required a 6 Gb/s channel  for each column. The key element of the reflective million pixel design is the Digital Pixel Generator (DPG), which consists of a 248×4096 CMOS shift register underlying a 1.6mm MEMS electron lens array. McCord showed that the first CMOS chips are now working, producing a checkerboard pattern that was focused onto the wafer plane and scrolled at stage speed to facilitate time domain integration (TDI) of the exposure. At designed demagnification, the pixels would be 6nm and edges would be placed to <1nm by using 31 different dose levels. If all goes well, a TDI-exposed wafer would appear soon, and the end of 2012 would see a 100kV 100X demagnification machine with 4 wafers and four 4^th generation columns working simultaneously to yield 4-8 wafers/hour using 30mC/cm² resist.

E- Beam Initiative

At the annual E-Beam Initiative lunch Managing Director Aki Fujimura noted that his organization is an educational platform for all electron-beam applications with 42 member companies, and open to all. In 2012, he predicted that the design for e-beam program (DFeB) would demonstrate mask-CD uniformity improvement on the first full-chip model based mask data preparation (MB-MDP) example. Ryan Pearman of D2S described how MB-MDF facilitated the use of overlapping circular shots to draw curved and diagonal mask features with better edge definition and uniformity. Both shot count and edge placement errors are reduced when circles replace rectangles stitched together at corners, according to Pearman.

Mike Smayling of Tela Technologies described how e-beam lithography could be used for the tiny and difficult “cut” operations in proposed 11nm complimentary lithography. In this system, proposed by Yan Borodowski of Intel and already being used by that company, all circuit features begin as linear and uniform line-and-space gratings. The gratings are then cut into useful circuit elements by subsequent exposures. The problem has been that up to 5 additional optical exposures would be needed to make all necessary circuit geometries because of the fundamental ~80nm limit on the minimum resolved pitch of each optical exposure.

Complementary Lithography process with 193nm immersion lithography. Different colors denote each of the 4 cut-mask exposures. (Courtesy Intel)

Smayling pointed out that an e-beam system could write all of the cuts at once, using Tela’s patented system, which would be much faster than writing the entire pattern. No e-beam system has yet been optimized for this specialized application, but he showed an example of an 11nm grating with cuts made using a Vistec electron lithography system at Cea-Leti .

Later in the conference, Kenji Abe described more   esthetic 22nm and 11nm line-and-cut results achieved on a multi-column cell projection prototype by a team from eBI member Advantest and TEL. In the first stage, the line grating was written by TEL’s self aligned double or quadruple patterning process. Then one beam of the Advantest MCC-POC EdBW tool cut line ends with 5nm overlay accuracy using either a positive or negative tone process. Development etching and subsequent processing resulted in controllable line end spacings down to 13nm. Abe pointed out that such a tool could cut the gate and M1 patterns anticipated for the 11nm node. Other papers from Advantest recommended design and resist innovations that would facilitate EbDW with character projection. The goal is 100 WPH at the 14nm node in a 150 beam, 10 cluster system with 100B shots/wafer, and 75mC/cm² resist. The drastic shot reduction required may first prove feasible in complementary lithography.

By Mark LaPedus, SemiMD senior editor

Next-generation maskless lithography — or multi-beam e-beam — is a great concept. But over the years, the progress for multi-beam has been slow and the technology is still not in production despite years of R&D.

Now, even though the multi-beam e-beam vendors are behind the curve, the new champions of the technology — DNP, Intel, Photronics and TSMC — have raised the bar on suppliers. The question is clear: Can vendors finally deliver?

It could be a make-or-break period for multi-beam vendors. For some time, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) has wanted maskless as part of its overall lithography strategy. At last week’s SPIE Advanced Lithography event in San Jose, Calif., TSMC surprised the industry and proposed the idea of having maskless for use in processing all critical layers in devices.

Maskless lithography has been around for decades. The idea behind the technology is to use a conventional, single-beam e-beam to write patterns directly on a wafer, thereby avoiding the need for the costly photomask. The problem is that direct-write e-beam is slow and expensive. So, various vendors, including IMS Nanofabrication AG, KLA-Tencor Corp., Mapper Lithography BV and others, are separately developing systems with multiple beams to boost overall throughput.

In a different application, Dai Nippon Printing Co. Ltd. (DNP), Intel Corp. and Photronics Inc. want a faster mask writer for the production of photomasks. Intel and Photronics have recently invested in IMS, which is developing a multi-beam tool for mask production. DNP has joined the effort.

Today’s photomask makers use traditional single-beam e-beams to pattern the reticle. But like direct-write applications, e-beams are slow. Still, multi-beam e-beam technology is unproven and suffers from throughput and cost issues. Because of the throughput issues, the technology “takes the industry off Moore’s Law,” said G. Dan Hutcheson, president of VLSI Research Inc.

The multi-beam vendors originally hoped to find a home at the 32nm and 22nm nodes, but they have missed that window. Now, vendors are talking about rolling out their first production tools for the 16nm node in 2015 or 2016.

New life for e-beam?

But given the problems and delays with extreme ultraviolet (EUV) lithography — and the costs of multi-patterning — multi-beam is worth exploring. Maskless lithography makes sense for prototyping or small-lot production, where it could potentially eliminate “50 percent of the masks in the world,” said Moshe Preil, manager of emerging lithography and tools at GlobalFoundries Inc.

What’s more, there is a pressing need for faster e-beams for photomask production. Since the 130nm node, the write step using an e-beam for the production of photomasks has fallen by a factor of eight, said Christopher Progler, vice president and chief technology officer at Photronics, a photomask maker, during a keynote at SPIE.

“We need a TwinScan-like productivity boost,” Progler said. He was referring to ASML Holding NV’s TwinScan scanner architecture, which uses a twin-stage scheme to double the overall throughput.

Today, there are two basic approaches to handle the reticle writing step using conventional single-beam tools. Using one e-beam tool, mask makers can write the critical layers on a photomask in sequential steps. Or, a mask maker can process the reticle using two or more e-beams simultaneously.

There is a third approach, which is being explored by DNP, Intel and Photronics. Austria-based IMS has been developing a so-called electron multi-beam Mask Exposure Tool (eMET) for the fabrication of leading-edge masks and templates. The company has completed a concept 50keV eMET. Through a programmable aperture plate, the eMET would provide 264,144 programmable beams with 20nm and 10nm beam sizes.

“It’s still in the proof-of-concept stage,” Progler said, but “this would fundamentally change the way masks are made.”

IMS’ alpha tool is due out in 2014, which could produce one mask in 15 hours, according to IMS during a presentation at SPIE. A beta tool is due out in 2015, which could produce one mask in 10 hours, according to the firm. The high-volume manufacturing system is due out in 2016, which could produce a mask in less than 10 hours.

In comparison, the average write time per mask layer is around 3.3 hours right now, a decrease from those in 2010, according to a survey from Sematech. But the average maximum write time per layer for a more complex mask is 33.2 hours right now, up 15 percent over 2010, according to the survey.

TSMC wants maskless

In another application, TSMC has been pushing hard for maskless lithography. As for multi-beam e-beam, high-volume manufacturing for the critical layers is targeted for 14nm and 10nm production. “The time is ripe for massively parallel e-beam systems,” said Burn Lin, vice president of the nano-patterning division at TSMC.

TSMC wants maskless to the point that Lin said the company is willing to pay $500,000 per wafer an hour. The end goal is to have a multi-beam system that handles 100 wafers an hour, which equates to a $50 million tool. That’s far below the price tag for extreme ultraviolet (EUV) lithography, as an EUV tool from ASML Holding NV reportedly runs $125 million each.

Lin said TSMC is considering inserting maskless lithography exclusively when it moves to 450mm wafers. Maskless would not only handle the critical layers, but also the non-critical layers for chips in 450mm fabs, Lin said. This would save time and money, because chip makers would only have to develop “one system for all resolutions,” he said.

Some believe this is a noble but far-fetched strategy. It is unlikely that TSMC would toss out its investments in optical tools if or when it moves to 450mm wafers or more advanced 300mm substrates.

The silicon foundry giant said it is evaluating multi-beam tools from three vendors: IMS, Mapper and KLA-Tencor. In 2010, TSMC installed Mapper’s “pre-alpha” maskless tool within its Fab 12 in Taiwan. In 2012, Mapper will complete its Matrix pre-production platform, which will initially have a throughput of 1 wafer per hour.

For some time, Mapper has been developing a production tool with some 13,000 beams. In theory, TSMC would like to cluster 10 of these production tools together for an overall throughput of 100 wafers an hour. But as before, Mapper has made little progress. The current tool from Mapper still only consists of 1 to 10 beams, according to TSMC. This leaves some to wonder if the company can really scale its technology to 13,000 beams.

TSMC is warming up to a tool from KLA-Tencor Corp. TSMC has not procured a tool, but KLA-Tencor has made “progress” in maskless, said Regina Freed, process development marketing manager for the REBL program. KLA-Tencor’s maskless tool is dubbed Reflective Electron Beam Lithography (REBL). Originally, the program was funded by the company and Darpa. In total, the entities have invested some $100 million in REBL.

The tool itself originally made use of a rotary stage and 36 separate e-beam columns. KLA-Tencor has changed the design and moved towards a linear column to the boost overall throughput, Freed said. The 50-100KeV design would eventually provide some 1 million beamlets.

During a presentation at SPIE, Freed envisioned three applications for REBL: processing all critical layers, prototyping and small lot production, and line cuts in complementary lithography applications. KLA-Tencor’s pre-alpha tool is due out in 2013, which would consist of a 4-to-6 column system for 45nm to 16nm patterning. Throughput would be around 5 wafers an hour, she said. The high-volume manufacturing system is due out in 2015, which could have an overall throughput of 100 wafers an hour.

By Mark LaPedus, SemiMD senior editor

The IC industry needs to think differently about lithography, according to a panel at the SPIE Advanced Lithography conference in San Jose, Calif.

Current optical lithography is moving towards the dreaded double-pattering era, thereby boosting chip-manufacturing costs. The leading next-generation lithography (NGL) — extreme ultraviolet (EUV) — is late due to the delays with the adequate power sources. And the cost-of-ownership for EUV is soaring out of control. An EUV tool is expected to run $125 million — each.

During the panel, lithography experts said that the market is ripe for an alternative NGL solution. Panelists represented the various alternative NGL technologies, such as direct self-assembly (DSA), maskless and nanoimprint.

Moshe Preil, manager of emerging lithography and tools at GlobalFoundries Inc., painted a sober picture in the current lithography landscape. None of the alternative NGLs “will be ready for the 20nm and neither will EUV,” Preil declared during the panel at SPIE.

Preil said that the industry is now looking for EUV at 14nm, but the other NGLs will still be on the launching pad. “I don’t think DSA or e-beam will be ready even if EUV is late,” Preil said, who represented the DSA viewpoint during the panel. In fact, GlobalFoundries is working on DSA, he said.

If or when the various NGLs appear for production fabs, the eventual winner in the NGL race will be the technology “that can make chips economically,” said Chris Bevis, principal investigator for KLA-Tencor Corp.’s REBL Electronic Beam Lithography unit. The inspection giant is developing a maskless system, dubbed Reflective Electron Beam Lithography (REBL).

Each NGL technology has its challenges, but clearly, “we are going in the wrong direction” with multi-patterning, Bevis said during the panel. Despite developing a maskless solution, the representative from KLA-Tencor believes that EUV could be a viable NGL. In fact, EUV and maskless could ultimately “co-exist” in a fab, he said. “EUV has made tremendous progress. It is ahead of e-beam. No doubt.”

Maskless suffers from slow throughput and other issues. Still, the technology could become a viable solution for prototyping and high-volume manufacturing, he said.

Adding to the argument from the maskless community, Burn Lin, vice president of the nano-patterning division at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), reiterated his radical and controversial stance.

Lin said TSMC is considering inserting maskless lithography exclusively when it moves to 450mm wafers. Maskless would not only handle the critical layers, but also the non-critical layers for chips in 450mm fabs, Lin said. This would save time and money, because chip makers would only have to develop “one system for all resolutions,” he said.

TSMC and others are also looking at EUV. But there are ongoing delays with the EUV power sources, causing angst in the industry. “I’m waiting for a light source,” said Tatsuhiko Higashiki, senior manager for the Advanced Lithography Process Technology Department at Toshiba Corp.

During the panel, Higashiki was touting nano-imprint lithography as a viable solution. Several years ago, Toshiba took delivery of a nano-imprint tool from Molecular Imprints Inc. (MII). Toshiba is  using nano-imprint for R&D in the NAND flash arena.

The trouble with nano-imprint is throughput and defectivity. The Toshiba representative said nano-imprint is making solid progress. For example, “the cost of ownership will be at the levels of 193nm immersion,” added S. V. Sreenivasan, chief technology officer at MII.

The darling in the NGL race is DSA. DSA is an alternative patterning technology that enables frequency multiplication through the use of block copolymers. When used in conjunction with an appropriate pre-pattern that directs the orientation for patterning, DSA can reduce the pitch of the final printed structure.

DSA is expected to hit the market at the 10nm node, said Ben Rathsack, member of the technical staff at Tokyo Electron Ltd. (TEL). “Defects are the obvious gaps. That’s the No. 1 goal we need to answer,” he said.

GlobalFoundries’ Preil agreed. “We’ve clearly demoed for lines and space for 10nm,” he said. “We will have processes ready for DSA at 10nm.”

The real challenge for DSA ”is to get it into the design flow early,” he said, adding the technology needs better overlay.

GlobalFoundries is also looking at EUV as its first choice in the NGL race. “Will DSA kill EUV? No. But it should kill 6x X-ray,” he said, referring to the industry push to develop 6.7nm EUV.

GlobalFoundries is talking to various consortia about maskless. Maskless makes sense in various applications, such as prototyping and complementary lithography. Prototyping in maskless application could potentially eliminate “50 percent of the masks in the world,” he said, but the technology boils down to “cost.”