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Posts Tagged ‘KLA-Tencor’

Lam Research, KLA-Tencor to Combine in $10.6 Billion Deal

Wednesday, October 21st, 2015

By Jeff Dorsch, Contributing Editor

Lam Research has agreed to acquire KLA-Tencor for $10.6 billion in cash and stock. The two giant suppliers of semiconductor capital equipment expect to close the transaction in mid-2016, subject to regulatory and shareholder approval.

The mammoth deal was announced on the same day as Western Digital saying it will purchase SanDisk for about $19 billion in cash and stock, continuing the yearlong trend of consolidation and megamergers in the semiconductor industry, and now in IC equipment, as well.

The news of the proposed tie-up between Lam and KLA-Tencor was greeted enthusiastically by industry analysts and perhaps less so at 3050 Bowers Avenue in Santa Clara, California – the headquarters of Applied Materials.

Srini Sundararajan, an analyst with Summit Research Partners, wrote of the blockbuster deal, “This is just what the doctor ordered. It removes excessive dependence of LRCX on memory and excessive dependence of KLAC on foundry/logic.  We expect minimal opposition to this deal from the various jurisdictions, rather easily handled.  Second, this deal is quite negative for Applied Materials (AMAT) and Hermes Microvision and perhaps for ASML also.  In the case of AMAT, their process diagnostics and control division being based in Israel does not allow of meshing of capabilities, and product synergies really don’t exist.  In the case of Hermes Microvision, since etch is the pre-dominant user of e-beam inspection due to testing of contacts, a combination of KLAC and LRCX with both e-beam and etch capabilities can be lethal.”

Both companies have experience in large mergers, with Lam acquiring Novellus Systems in 2012. KLA Instruments merged with Tencor Instruments in 1997. And both companies are generally active in strategic acquisitions.

The megadeal values KLA-Tencor common stock at roughly $67.02 per share, a premium of about 24 percent to KLAC’s closing price of $53.86 on Tuesday (October 20).

With the closing of the deal, KLA-Tencor shareholders will own around 32 percent of the combined company, which will be called Lam Research Corporation. Martin Anstice, president and chief executive officer of Lam Research, will serve as the combined company’s CEO. Lam Chairman Steve Newberry will continue in that post. Upon closing, two members of the KLA-Tencor board of directors will join the Lam board.

Lam Research also reported net income of $288.7 million on revenue of $1.6 billion for the quarter ended September 27, compared with net income of $141.1 million on revenue of $1.15 billion for the same quarter a year ago.

KLA-Tencor reported results for its fiscal first quarter ended September 30, with net income of $104.9 million on revenue of $642.64 million. That compared with year-ago net income of $72.23 million on revenue of $642.9 million.

Optimal+ Turns 10, Wins Accolades For Its Work

Friday, July 17th, 2015


By Jeff Dorsch, Contributing Editor

Optimal+ has been in business since 2005. The Israel-based company, which has offices around the world, has something else to celebrate this year: Frost & Sullivan gave Optimal+ its 2015 Global Semiconductor Test Visionary Innovation Leadership Award.

“Frost & Sullivan firmly believes that Optimal+ is the epitome of visionary innovation as it relates to Big Data analytics for the semiconductor industry,” the management consulting and market research firm said. It cited Optimal+’s ability to offer customers a high return on investment, along with improvements in quality and yield, among other attributes.

Optimal+ last year changed its name from OptimalTest, saying it had expanded beyond semiconductor test operations to supply chain management and visibility, product planning, and Big Data analytics.

“The name Optimal+ is more representative of our business and focus moving forward,” founder and CEO Dan Glotter said in a statement.

Kenneth Levy, the chairman emeritus of KLA-Tencor and founder of KLA Instruments, serves as chairman of the Optimal+ board. The company’s investors include Aviv Ventures, Carmel Ventures, Evergreen Venture Partners, and Pitango Venture Capital.

Optimal+ has Advanced Micro Devices and Broadcom among its customers, and it has worked with a wide variety of fabless semiconductor companies, integrated device manufacturers, and outsourced semiconductor assembly and test firms.

“Everything we do is predicated on ROI,” says David Park, the company’s vice president of worldwide marketing. Optimal+ has processed and approved more than 20 billion chips in its decade-long history, and it says its software and services are checking out 15 billion chips a year now.

Park says the company can deliver up to 2 percent greater yield and up to 3 percent improvement in product yield recovery based solely on test, while also increasing operational efficiency and productivity improvements by up to 20 percent. Optimal+ is additionally all about test-time reduction, he adds.

Optimal+ last month rolled out Release 6.0 of its Semiconductor Operations Platform with a new feature, Extreme Analytics and Characterization, or EXACT. It also announced the selection of the HP Vertica Analytics Platform to help its customers with business intelligence and analytics.

For Optimal+, the company’s product and services portfolio is all about providing “Manufacturing Intelligence,” Park notes.

SPIE Photomask Technology Wrap-up

Tuesday, September 23rd, 2014

Extreme-ultraviolet lithography was a leading topic at the SPIE Photomask Technology conference and exhibition, held September 16-17-18 in Monterey, Calif., yet it wasn’t the only topic discussed and examined. Mask patterning, materials and process, metrology, and simulation, optical proximity correction (OPC), and mask data preparation were extensively covered in conference sessions and poster presentations.

Even with the wide variety of topics on offer at the Monterey Conference Center, many discussions circled back to EUV lithography. After years of its being hailed as the “magic bullet” in semiconductor manufacturing, industry executives and engineers are concerned that the technology will have a limited window of usefulness. Its continued delays have led some to write it off for the 10-nanometer and 7-nanometer process nodes.

EUV photomasks were the subject of three conference sessions and the focus of seven posters. There were four posters devoted to photomask inspection, an area of increasing concern as detecting and locating defects in a mask gets more difficult with existing technology.

The conference opened Tuesday, Sept. 16, with the keynote presentation by Martin van den Brink, the president and chief technology officer of ASML Holding. His talk, titled “Many Ways to Shrink: The Right Moves to 10 Nanometer and Beyond,” was clearly meant to provide some reassurance to the attendees that progress is being made with EUV.

He reported his company’s “30 percent improvement in overlay and focus” with its EUV systems in development. ASML has shipped six EUV systems to companies participating in the technology’s development (presumably including Intel, Samsung Electronics, and Taiwan Semiconductor Manufacturing, which have made equity investments in ASML), and it has five more being integrated at present, van den Brink said.

The light source being developed by ASML’s Cymer subsidiary has achieved an output of 77 watts, he said, and the company expects to raise that to 81 watts by the end of 2014. The key figure, however, remains 100 watts, which would enable the volume production of 1,000 wafers per day. No timeline on that goal was offered.

The ASML executive predicted that chips with 10nm features would mostly be fabricated with immersion lithography systems, with EUV handling the most critical layers. For 7nm chips, immersion lithography systems will need 34 steps to complete the patterning of the chip design, van den Brink said. At that process node, EUV will need only nine lithography steps to get the job done, he added.

Among other advances, EUV will require actinic mask inspection tools, according to van den Brink. Other speakers at the conference stressed this future requirement, while emphasizing that it is several years away in implementation.

Mask making is moving from detecting microscopic defects to an era of mesoscopic defects, according to Yalin Xiong of KLA-Tencor. Speaking during the “Mask Complexity: How to Solve the Issues?” panel discussion on Thursday, Sept. 18, Xiong said actinic mask inspection will be “available only later, and it’s going to be costly.” He predicted actinic tools will emerge by 2017 or 2018. “We think the right solution is the actinic solution,” Xiong concluded.

Peter Buck of Mentor Graphics, another panelist at the Sept. 18 session, said it was necessary to embrace mask complexity in the years to come. “Directed self-assembly has the same constraints as EUV and DUV (deep-ultraviolet),” he observed.

People in the semiconductor industry place high values on “good,” “fast,” and “cheap,” Buck noted. With the advent of EUV lithography and its accompanying challenges, one of those attributes will have to give way, he said, indicating cheapness was the likely victim.

Mask proximity correction (MPC) and Manhattanization will take on increasing importance, Buck predicted. “MPC methods can satisfy these complexities,” he said.

For all the concern about EUV and the ongoing work with that technology, the panelists looked ahead to the time when electron-beam lithography systems with multiple beams will become the litho workhorses of the future.

Mask-writing times were an issue touched upon by several panelists. Shusuke Yoshitake of NuFlare Technology reported hearing about a photomask design that took 60 hours to write. An extreme example, to be sure, but next-generation multi-beam mask writers will help on that front, he said.

Daniel Chalom of IMS Nanofabrication said that with 20nm chips, the current challenge is reduce mask-writing times to less than 15 hours.

In short, presenters at the SPIE conference were optimistic and positive about facing the many challenges in photomask design, manufacturing, inspection, metrology, and use. They are confident that the technical hurdles can be overcome in time, as they have in the past.

SPIE panel tackles mask complexity issues

Friday, September 19th, 2014

Photomasks that take two-and-a-half days to write. Mask data preparation that enters into Big Data territory. And what happens when extreme-ultraviolet lithography really, truly arrives?

These were among the issues addressed by eight panelists in a Thursday session at the SPIE Photomask Technology conference in Monterey, Calif. Participants in the “Mask Complexity: How to Solve the Issues?” panel discussion came from multiple segments of the photomask food chain, although only one, moderator Naoya Hayashi of Dai Nippon Printing, represented a company that actually makes masks.

The panelists were generally optimistic on prospects for resolving the various issues in question. Dong-Hoon Chung of Samsung Electronics said solutions to the thorny challenges in designing, preparing, and manufacturing masks were “not impossible.”

Bala Thumma of Synopsys said he was “going to take the optimistic view” regarding mask-making challenges. “Scaling is going to continue,” he added.

“We are not at the breaking point yet,” Thumma said. “Far from it!” Electronic design automation companies like Synopsys will continue to improve their software tools, he asserted. Mask manufacturers will also benefit from “strong partnerships” with vendors of semiconductor manufacturing equipment, and “strong support from semiconductor companies,” he said.

“There is a lot of complexity,” he acknowledged. Still, going by past experience, “this group of people has been able to work together and solve these issues,” Thumma concluded.

To resolve the issue of burgeoning data volumes in mask design and manufacture, Suichiro Ohara of Nippon Control System (NCS) proposed the solution of a unified data format – specifically MALY and OASIS.MASK software. Shusuke Yoshitake of NuFlare Technology later said, “OASIS is gaining, but GDSII still predominates.”

Several panelists took the long-term view and looked beyond the coming era of EUV lithography to when multiple-beam mask writers and actinic inspection of masks will be required. EUV and actinic technology, it was generally agreed, will arrive at the 7-nanometer process node, possibly in 2017 or 2018. Multi-beam mask writers are also several years away, it was said.

As the floor was opened to questions and comments, consultant Ken Rygler noted that commercial mask makers have “very low margins” and asked, “How does the mask maker pay for the inspection tools, the EDA, materials?” Yalin Xiong of KLA-Tencor said the mask business is in “a tough time economically.” He added, “We have to look at where the high-end business is going. Captive [mask shops] should step up.”

Process Watch: Sampling matters

Monday, September 15th, 2014

By David W. Price and Douglas G. Sutherland

Author’s Note: Sampling Matters is the second in a series of 10 installments that explores the fundamental truths about process control—defect inspection and metrology—for the semiconductor industry. Each article introduces one of the 10 fundamental truths and highlights their implications.

In the previous installment we discussed the importance of a process control strategy being capable (i.e. able to identify the problems that are limiting a factory’s baseline yield). After a capable strategy is in place, a factory can turn to optimizing the strategy to make it cost-effective—ensuring that the factory achieves maximum return on their investment. In most cases, this optimization is made through the introduction of sampling.

In general, process control sampling takes into account:

  • the number of measurement sites per wafer for metrology (or wafer area for defect inspection)
  • the number of wafers per lot that are measured
  • the percentage of measured lots

In this article, it is assumed that the first two sampling components— sites per wafer and wafers per lot, are part of your capability strategy (addressed in the previous article), and that the word sampling refers simply to the percentage of the measured lots.

Sampling is a unique concept to process control—you can’t sub-sample wafers to be etched, for example. The degree to which a factory will sample is based on the probability, projected from historical data, that an excursion will occur and the potential impact of that excursion. Determining an optimum sampling strategy comes down to weighing the cost of process control against the benefit of capturing the defect or other excursion in a timely manner.

The second fundamental truth of process control for the semiconductor IC industry is:

It is always more cost-effective to over-inspect than to under-inspect

For simplicity, let’s assume that the probability that the process control tool will detect the excursion is fixed. That means that we’re neglecting the fact that some types of excursions are easier to detect than others. We will cover this topic in a later series installment.

The economic impact of this excursion is a function of the number of exposed lots per excursion, the number of excursions per year, the yield loss per excursion, and the cost of the twenty-five wafers in the exposed lots. These quantities can be estimated and plotted as a function of the sampling rate (Figure 1a). Thus, lower sampling leads to more yield loss when an excursion occurs simply because there are more lots between inspections. The excursion cost is reciprocal of the sampling rate—very high at low sampling and decreasing at 1/x as the sampling rate, x, increases.

Figure 1a

The capital cost of sampling is a function of the process control tool price, the resources used to operate it and the tool’s throughput and sensitivity. These quantities are estimated and plotted as a function of a sampling rate in Figure 1b. The capital costs increase linearly with the sampling rate because more tool capacity is required as the sampling rate increases.

Figure 1b

The total cost is the sum of the excursion and the capital cost, and the shape of the resulting curve is depicted in Figure 1c. A minimum in this curve indicates an optimum sampling rate—the point of lowest total cost. When there is no minimum, the optimum sampling rate is 100 percent, a scenario that frequently occurs for metrology.

Figure 1c

At the optimum sampling rate, any reduction in sampling would result in more yield loss than capital savings, and any increase in sampling would result in more capital cost than the prevented yield loss (see Figure 1c). While the overall shape of the curve is governed mainly by the lot sampling rate, with other input assumptions shifting the minimum left or right, the curve consistently delivers the message that under-sampling is riskier (i.e. more costly) than over-sampling. Measuring too few sites per wafers, wafers per lot, or lots per run is a high-cost way of running a manufacturing line.

In this model, the optimum sampling rate is proportional to the square root of the excursion cost and inversely proportional to the square root of the capital cost. In other words, a stable process does not need to be measured as frequently as a process having frequent excursions, but the relationship is not linear. If you were to decrease the excursion frequency by a factor of four, then you would be able to cut the sampling rate by a factor of two, to retain the minimum total cost.

Because of the mathematical nature of this curve, the total cost to the right of the optimum (higher sampling) is always less risker than being off by the same amount to the left of the optimum (lower sampling). In other words:

Total cost (xo + Dx) < Total cost (xoDx)

where xo is the sampling rate with the lowest total cost.

There are other reasons to err on the side of over-sampling. Data is usually cheaper than the experienced engineering expertise required to draw conclusions. In a time-to-market based environment, such as the semiconductor industry, you cannot allow your decision makers to be data-starved; the data needs to be readily available to drive appropriate corrective actions. Indeed, of all the activities required for baseline yield learning–engineering talent, inspection data, processed wafers—the cost of the inspection is the least expensive.

About the authors:

Dr. David W. Price and Dr. Douglas Sutherland are senior director and principal scientist, respectively, at KLA-Tencor Corp. Over the last 10 years, Dr. Price and Dr. Sutherland have worked directly with more than 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements. For further exploration of how sampling theory can be used to optimize inspection or metrology process control for your specific situation, please contact the authors of this article.

The Week in Review: August 29, 2014

Friday, August 29th, 2014

Intel Corporation announced two new technologies for Intel Custom Foundry customers that need cost-effective advanced packaging and test technologies.

Fairchild Semiconductor, a supplier of high performance power and mobile products, today announced it will eliminate its internal five-inch and significantly reduce six-inch wafer fabrication lines, resulting in the closure of its manufacturing and assembly facilities in West Jordan, Utah and Penang, Malaysia, as well as the remaining five-inch wafer fabrication lines in Bucheon, South Korea.

KLA-Tencor Corporation released two metrology tools and an upgraded data analysis system that can reduce overlay error by 25% when using multi-patterning in leading-edge IC fabs. By taking additional data and using feed-forward control loops, the integrated solution dynamically adjusts the exposures in lithographic steppers to improve both overlay and critical dimension (CD) results in high-volume manufacturing (HVM).

United Microelectronics Corporation (UMC) and Fujitsu Semiconductor Limited announced an agreement for UMC to become a minority shareholder of a newly formed subsidiary of Fujitsu Semiconductor that will include its 300mm wafer manufacturing facility located in Kuwana, Mie, Japan.

Scientists have developed what they believe is the thinnest-possible semiconductor, a new class of nanoscale materials made in sheets only three atoms thick.

SEMI announced the keynotes for the 2nd Vietnam Semiconductor Strategy Summit (September 16-17), an executive conference focused on Vietnam’’s growing role in the global semiconductor industry.

Solid State Watch: August 22-28, 2014

Friday, August 29th, 2014
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Overlay Metrology Suite for Multiple Patterning

Tuesday, August 26th, 2014

By Ed Korczynski, Sr. Technical Editor

Today, KLA-Tencor Corporation (NASDAQ: KLAC) released two metrology tools and an upgraded data analysis system that can reduce overlay error by 25% when using multi-patterning in leading-edge IC fabs. By taking additional data and using feed-forward control loops, the integrated solution dynamically adjusts the exposures in lithographic steppers to improve both overlay and critical dimension (CD) results in high-volume manufacturing (HVM). The suite of tools has passed beta-site evaluations with fab customers.

“Feed-forward has been used at gate CD to control variations, mostly controlling the Z-dimension of deposition and etch. But this is using feed-forward to control the 2D aspect of overlay.” explained Ady Levy, KLA-Tencor fellow, in an exclusive interview with Solid State Technology and SemiMD. “With the absence of traditional lithography scaling, customers are developing 3D structures that are using other parts of the fab.”

Figure 1 shows an analysis of the origin of patterning errors for Litho-Etch-Litho-Etch (LELE) double-patterning, indicating that traditional lithography processes account for just ~40% of the errors. Most multi-patterning errors originate with the deposition and etching and chemical-mechanical planarization (CMP) of films, inducing wafer-shape variations and thickness non-uniformities.

Fig. 1

The company’s WaferSight™ Patterned Wafer Geometry (PWG) measurement tool is an extension of the WaferSight line to measure bow and warp and other surface non-uniformities on unpatterned wafers, with the added ability to measure both sides to provide data on thickness variations. By incorporating industry-unique vertical wafer hold to minimize gravitational distortion and a sampling density of 3.5 million data points per wafer, the new tool produces highly accurate wafer shape data. “By feeding forward this information we can then correct the exposure on the scanner and correct for the induced overlay error due to stress from a prior process step,” elaborated Levy.

Brunner et al. (Optical Microlithography XXVII, Proc. of SPIE, Vol. 9052, 90520U, 2014) from IBM recently showed the quantified benefits of using PWG feed-forward (PWG-FF) information in stepper exposures to correct for across-wafer stress variation. Stress Monitor Wafers showed overlay errors dominated by wafer distortion effects, with six-times greater distribution of errors compared to distortion-free wafers. Table 1 compares standard linear alignment with High Order Wafer Alignment (HOWA) and with PWG-FF alignment, the latter provides the best results without requiring the slower processing of HOWA.

Proprietary model-based metrology allows the LMS IPRO6 to accurately measure reticle registration for on-device pattern features, as well as standard registration marks for significantly higher sampling. With faster measurement time than its predecessor, the LMS IPRO6 supports measuring the increased number of reticles associated with innovative multi-patterning techniques. The LMS IPRO6 enables generation of pattern-dependent registration error data that improves feedback to the e-beam mask writer, and can be fed forward to the fab’s lithography module for feature-optimized scanner corrections that improve wafer-level patterning.

The K-T Analyzer 9.0 is the latest version of the company’s platform that enables advanced, run-time data analysis for a wide range of metrology system types. Though the company fields a wide portfolio of products, KLA-Tencor doesn’t provide all inspection and metrology tools needed to control a commercial HVM fab line, and so the company provides software loaders to allow data from other tools to be integrated. The data analysis platform upgrade includes in-line methods for calculating scanner corrections per exposure on an on-product, lot-by-lot basis that maintains high accuracy without requiring full wafer measurement data—a production-capable control technique that can reduce pattern overlay error. In addition, the platform includes new scanner fleet management, scanner data analysis, and scanner alignment optimization capabilities.

All of this allows commercial HVM fabs to push the limits of patterning resolution for complex next-generation logic ICs. “Within the lithography module, our Archer™ 500 overlay and SpectraShape™ 9000 CD advanced metrology systems identify and monitor patterning errors,” said Ahmad Khan, group vice president of KLA-Tencor’s Parametric Solutions Group. “Extending beyond the lithography cell, our new WaferSight PWG and LMS IPRO6 systems isolate additional process- or reticle-related sources of patterning errors. These fab-wide, comprehensive measurements, supported by K-T Analyzer 9.0’s flexible data analysis, expand the process window and enable improved production patterning control for our customers’ leading-edge devices.”


The Week in Review: May 23, 2014

Friday, May 23rd, 2014

Worldwide silicon wafer area shipments increased during the first quarter 2014 when compared to fourth quarter 2013 area shipments according to the SEMI Silicon Manufacturers Group (SMG) in its quarterly analysis of the silicon wafer industry. Total silicon wafer area shipments were 2,364 million square inches during the most recent quarter, a 7.1 percent increase from the 2,208 million square inches shipped during the previous quarter. New quarterly total area shipments are 11.1 percent higher than first quarter 2013 shipments.

North America-based manufacturers of semiconductor equipment posted $1.44 billion in orders worldwide in April 2014 (three-month average basis) and a book-to-bill ratio of 1.03, according to the April EMDS Book-to-Bill Report published today by SEMI.   A book-to-bill of 1.03 means that $103 worth of orders were received for every $100 of product billed for the month.

KLA-Tencor Corporation announced the Teron SL650, a new reticle quality control solution for IC fabs that supports 20nm design nodes and beyond. With 193nm illumination and multiple STARlight optical technologies, the Teron SL650 provides the sensitivity and flexibility required to assess incoming reticle quality, monitor reticle degradation and detect yield- critical reticle defects, such as haze growth or contamination in patterned and open areas. In addition, the Teron SL650’s industry-leading production throughput supports the fast cycle times required to qualify the increased number of reticles associated with advanced multi- patterning techniques.

Mentor Graphics Corp. announced that it has acquired Nimbic, Inc., a provider of Maxwell-accurate, 3D full-wave electromagnetic (EM) simulation solutions. Nimbic’s high-performance high-end simulation capability and ability to accurately calculate complex electromagnetic fields will expand and strengthen Mentor’s chip-package-board simulation portfolio.

ON Semiconductor has introduced a new family of six N-channel MOSFETS that have been designed and optimized to deliver efficiency.

Brewer Science, Inc., a supplier of thin-wafer handling technology, materials, and equipment to the microelectronics industry, today unveiled the Brewer Science Apogee bonder for temporary wafer bonding applications. This marks an industry milestone in leveraging Brewer Science’s unique ability to combine processing equipment, high-temperature temporary adhesives, and process integration into a seamless thin-wafer handling solution.

Blog review January 13, 2014

Monday, January 13th, 2014

Why is Silicon Valley the world center for innovation? How does innovation continue to thrive there? How do you create and maintain an innovative culture? These and other thought-provoking questions were the topics of discussion on a recent episode of Inside Silicon Valley, a public affairs program. Eric Witherspoon of Applied Materials blogs about these questions and various answers.

Adele Hars blogs that 2014 is going to be a terrific year for the greater SOI community, with 28nm FD-SOI ramping in volume and 14nm debuting, plus RF-SOI continuing its stellar rise. In this post she takes a look back at some of the SOI-related highlights from 2013.

Phil Garrou provides details on the most notable packaging papers presented at the 2013 IWLPC Conference held in San Jose CA this past fall, including those from Rudolph, Nanium and Deca. He also comments on the rumors that ASML has delayed its 450mm EUV efforts.

Pete Singer blogs from this week’s ISS. Keynote Rick Wallace, president and CEO of KLA-Tencor said the semiconductor industry could be approaching a “Concorde moment” where economic factors overtake technical capabiltiies. Wallace also sees a need to boost innovation, and suggests the way to best do that is encourage young people to get excited about the “magic behind the gadget.”

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