A company’s intellectual property (IP) is fundamental to its ability to innovate, develop new technologies and methods, and move forward in a competitive industry. SEMI is acutely aware that what distinguishes its key industries from many others is the relatively high percent of revenue that is reinvested into R&D.

On average, semiconductor equipment and materials companies invest 10-15 percent of their revenues back into R&D each year, with 2011’s R&D investment translating to $9-14 billion. Both semiconductor equipment and materials companies have unique challenges associated with their IP, but realizing a return on their R&D investment is still essential.

The SEMI IP survey was sent to a global group of SEMI members and almost half responded. Over 60 percent of companies reported that IP challenges have translated into an adverse impact on their companies. Three-fourths of the companies responding had pursued legal action against IP violators. In terms of the types of violations experienced, several areas were repeatedly mentioned; patent infringement and counterfeiting were the recurring themes, with some regions more problematic than others. The survey also asked whether the situation in each region was improving, worsening, or staying the same.

This survey information helps SEMI continue benchmarking the global evolution of IP as a key concern, and helps us prioritize our work and actions with governments and partners around the world—helping to raise the bar and level the playing field.

To download this white paper, click here.

By Ed Sperling
Semiconductor Manufacturing & Design sat down to discuss the transition to IP subsystems with Kevin Meyer, vice president of design enablement strategy and alliances at GlobalFoundries; Steve Roddy, vice president of marketing at Tensilica; Mike Gianfagna, vice president of marketing at Atrenta; and Adam Kablanian, CEO of Memoir Systems. What follows are excerpts of that conversation, which took place before a live audience at the Semico Impact Conference.

SMD: Do subsystems limit the number of players that can compete in the market by raising the cost of entry?
Kablanian: Absolutely. The integrated device manufacturers and large chipmakers have been able to do this integration for years. It includes everyone from software to architect to RTL designer, physical library providers to the fab. They have the whole vertical know-how. For a small company to do this is almost impossible. Naturally it will limit the number of companies doing this, and it will force consolidation among a few players.
Gianfagna: You’ll have to have more investment and more vertical knowledge, and that in general will result in a better deliverable. I don’t think it will limit innovation, though. The market resists being homogenized. Differentiation will continue at a higher level of abstraction.

SMD: Software is a subsystem, right?
Gianfagna: It is.
Roddy: There was a time when you could count 500-plus IP providers. But if there are 3,000 to 5,000 design starts, you can’t have 500 IP providers. They’re all going to wind up with five customers. That doesn’t work. But there can be 30 to 50 IP providers.

SMD: Both of the big foundries have done testing of IP. Will that continue with subsystems?
Meyer: You have to look at that by technology node. The closer you are to the bleeding edge of technology the more expensive that investment is. There you’re going to limit the number of partners. You have to do that because you need solutions as early as possible for existence proof of that technology node. We work very hard on that, and we do that with guys who know what they’re doing and who are capable of providing a level of support at that design level. It’s not just throwing it over the wall and getting IP. The IC integrator has to be involved to do that successfully. But as we start moving away from the bleeding edge, we want to work with innovative companies doing things like power management at 1.3 micron or even 65nm. With embedded and non-volatile we look to work with those companies.
Kablanian: There is room for the foundries to adopt new IP and take some risks. That has not been done.
Meyer: A lot of what we’re doing is anticipating yields. A lot of our focus is on working with companies like Cadence and Synopsys and Mentor on yield enhancement, and we’re working with system providers to understand how that IP will work in silicon. We think our customers get a lot more of an advantage working in those areas, like DFM, as opposed to the system-level aspect. That’s why you can come in with a customer who really understands the value of what you’re doing.

SMD: One of the great advantages of stacking die is that you don’t necessarily need to worry about developing IP at the latest process node. What does that mean for subsystems?
Roddy: If it becomes widespread then the economics of the value chain will change. That’s a dramatically different business model because the IP provider essentially is a contractual silicon provider. They might sell you a 50-cent sliver of silicon that you’re integrating, which is dramatically different business structure. The analog IP provider works to validate with the global partner. You could be sitting back at quarter micron for your analog and your memory might be at 14nm.
Gianfagna: There is certainly more predictability.
Roddy: It adds much more opportunity for the analog part, which has less flexibility because they have so many process-specific attributes. If you get it right, then there will be an emphasis on keeping it in that process.
Gianfagna: If you get it right for subsystems, you can make the same argument.
Roddy: You can still validate a piece of silicon with the proper interface. That may be the next evolution.

SMD: Subsystems aren’t a new concept. It’s been done at the board level for decades. But have we gotten to the point where designers are willing to let others create and verify these subsystems?
Gianfagna: It’s no longer a question of who designs the best circuit. It’s who integrates it the best.
Roddy: There are a handful of companies that still do their own libraries, but the vast majority do not. The vast majority doing SoC design are no longer providing all of the pieces, but they are working with vendors to optimize blocks wherever they can.

By Ed Sperling
Semiconductor Manufacturing & Design sat down to discuss the transition to IP subsystems with Kevin Meyer, vice president of design enablement strategy and alliances at GlobalFoundries; Steve Roddy, vice president of marketing at Tensilica; Mike Gianfagna, vice president of marketing at Atrenta; and Adam Kablanian, CEO of Memoir Systems. What follows are excerpts of that conversation, which took place before a live audience at the Semico Impact Conference.

SMD: If we have two good memory subsystems and they no longer work when they’re put together, who’s responsible and how do we sort that out?
Gianfagna: The one who fixes it is always the system designer. But who’s responsible is a good question. Is it because the spec was wrong? Is it because the design was wrong? It could be the IP vendor, the subsystem vendor or the system designer. Natural selection will eventually weed out the problem, but at the end of the day is the system vendor who has take responsibility. They’re the general contractor. They have the responsibility of making sure everything works, which is a daunting task at this level of complexity. Even though things may comply with standards, that may not mean the same thing to everyone.
Roddy: The are two pieces to this. The first is that the subsystem has to be a naturally occurring subsystem. You can’t take two things that don’t normally go together because no one will know how to put them together. Expertise in one area isn’t the same in another. The second is that you see system designers doing an immensely larger amount of system simulation. If they can do it early enough they can determine if these things will work together with the system resources like bandwidth and memory. Planning ahead is the key to avoiding problems.
Kablanian: The best thing is to avoid having two similar subsystems on the same chip. You need to understand how to test a memory, for example, how to integrate it into a common test methodology, and how to debug it. If you have two similar subsystems, it’s almost impossible to figure this stuff out.
Gianfagna: But if you buy two subsystems from the same vendor, will they work together? I would hope so.

SMD: Where does the foundry sit in all of this?
Meyer: If it comes down to a design issue, there’s not much we can do. What we can do is enable design components ahead of the integration into the system level. For instance, if it’s a third-party IP partner, we work with them as we go through the process of silicon validation. Increasingly, for more advanced technologies we’re actually building in a second spin. We try to get out early in the process, work with our IP suppliers to get on early shuttles so we get back results early. We have a learning step through that to make the process more robust. We’ll do what we can relative to silicon validation with third-party IP. When we have a large customer that does its own IP, we have a team in design enablement that does co-optimization with them. That team actually works with our customers early. We often run their test chips as part of that process, as well, for their libraries, memory and IP. But we also have a team that goes in and does early co-optimization and gives them our input as to anticipated silicon effects. Whatever the problem is, we’ll get involved as much as we can, because until it gets into production everything we do is an investment to save time. We’re highly motivated to get all parties into production.

SMD: When you look at IP it’s a black box. Subsystems are bigger black boxes. Is it harder to verify and integrate them?
Roddy: If the vendor has done their work to validate the box, whether it has one element or four, it should be largely immaterial to the integrator. The inflection point is when you start stacking software on top of the multiple elements and it goes out and addresses other resources and you’re bus traffic-dependent. You have to factor in the expected system behavior, including latencies and interactions between multiple blocks and the system. What are the potential problems from the graphics subsystem fighting with the video subsystem? That’s where we get into system modeling and analysis. If the vendor assumed a certain set of conditions that your SoC doesn’t adhere to, then all the characterization goes out the window.
Kablanian: Testing the silicon is not sufficient because many of the IPs people use are configurable. What works in one case may not work in another. The crux of this is a verification methodology, and companies that figure that out will be successful with this strategy.
Gianfagna: There’s a topic we’re touching on here that is very important, which is what it means to deliver a certain level of quality. There are not a lot of standards there. This is a big problem. There is no vocabulary we can use that is consistent between IP vendors. You need machine-generated metrics, which is something the IP community won’t like. But we don’t even have a common language that says this IP is of a certain level of quality and it has passed these tests.
Meyer: Ultimately, if it doesn’t work then GlobalFoundries is involved. We’re doing all we can. Obviously we have partners at the very leading edge working on this, including verification of their IP. When we start looking at 28 gigabit-per-second SerDes, that’s a whole subsystem. We are not the systems experts, but we put into place a very good support structure for them. Now, when you start to move away from the bleeding edge, clearly the challenges are not as great. We’re working with customers on all types of IP, but for each different application and each technology node we are working with customers and IP partners to make sure their IP is as risk-free as possible.

SMD: Even in the most advanced devices we’ve seen major errors crop up in subsystems. There is no way to test all of this complexity. Are subsystems really a step forward in reducing complexity or are they just adding new wrinkles to it?
Roddy: I don’t think subsystems change the overall equation. There are too many pieces. In the fully synchronous synthesizable areas the processors interact with the software so it becomes an issue of software correctness. The good news is that you do have software, so it can be fixed. If you can do an analysis and make sure the parts that consume data flowing through the device are properly calibrated and you model all the use cases, then you can fix the software to address everything else. It’s all about appropriate system-level design. It isn’t any different today than 15 years ago when we worked on IP blocks instead of subsystems. It still gets treated like a block.
Gianfagna: There needs to be a methodology. You have to run tests on those blocks before you create masks. But if the quality of the incoming data is vetted you’re going to have fewer problems later on for everyone in the supply chain. From the front of the supply chain to the back, everyone has to step up.
Roddy: We look at a core as being a subsystem. It’s a complex set of registers, data paddles and so forth. That’s an integral part of an SoC. Typically you bring up a technology node with very regular structures. We’ve integrated an A9 core and integrated it into our test chip strategy. It gives us a different understanding of the technology problem, which is great for isolating defects. But you also now have to consider proximity effects, so we now use the A9 as part of our test strategy for bringing up our process technology. We started looking at these problems from the yield side. Once we see them work, we start increasing the frequency. We are trying to support the subsystems down to our test strategy.