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IP interoperability in SoCs: Mix and match doesn’t always work

Wednesday, March 26th, 2014

By Matt Hogan, product marketing manager for Calibre Design Solutions at Mentor Graphics.

Design re-spins, shorter time to market schedules, and the continued productivity pressures on engineers within the integrated circuit (IC) design community have all contributed to the widespread re-use of intellectual property (IP), which is seen as a quick way to incorporate proven technology in a new design. The thing is, more often than not, a design re-spin isn’t just a simple re-spin with a tweak here and a tweak there. The new design will probably have to comply with modified specifications that inevitably raise the bar for performance and power usage, and it will probably contain new IP that must be integrated. At the same time, the design team will be told to leverage as much of the silicon-proven IP already in production as possible. The verification from the previous design must be re-done, using as many automated tools and processes as possible to minimize timelines. With multiple power domains, complex power management schemes, and high signal counts, reliability concerns for today’s low power designs are at the forefront of priorities.

In 2011, the ESD Association published a technical report on ESD Electronic Design Automation Checks (ESD TR18.0-01-11) that outlined a number of recommended reliability checks. Not content to stop there, they continued work on a revised version of this report (publication forthcoming). Contained within this report are a number of recommended cell-level electrostatic discharge (ESD) checks. Rule 6.1.1 is titled, “Verify that Correct Version of the Device/Design Kit/Cell/Library is being used when using Standard Library Cells or Parameterized Cells (PCELLs)”. The focus of this check from the ESD community is to ensure that the cell has been “screened” to ensure it is acceptable for use within the design.

While the ESD focus for checking cell names is valid, there are broader reasons to validate the interoperability of cells being used together within the same design. Most of these focus on controlling and understanding the isolation of power and signals within the design. Imagine, if you will, a SERDES buffer contained in one cell, while supporting circuitry is contained in other cells. If an optimization is made to the SERDES buffer that also requires tweaks to the circuitry in the other cells, we now have a situation where the versions of all of these cells are now interdependent. How do we capture this interdependence in the design? More importantly, how do we control the situation so that other designers using these cells use the correct versions?

Figure 1. Re-spins of production designs may implement new cell versions that affect interoperability.

Figure 1 shows a case where five blocks were used successfully in a previous design. The version numbers of these blocks are proven to be compatible with each other. However, since the production of that design, the libraries containing these cells have been revised, and newer versions of these cells are now available. Unfortunately, simply accepting the latest versions from the design library may not yield optimum results. The new design on the right uses the latest versions of these cells, but who has validated that these new versions are compatible with each other, and with the older versions of the unchanged cells?

Internal design rule manuals provide a central location to store a vast array of different design rules. It would not be too much of a leap to include version numbers of cells and interoperability information. Alas, updating the design rule manual is a manual process, subject to the usual human error and forgetfulness. In addition, even if provided, the information could be easily overlooked, particularly for designs with large numbers of IPs and a significant number of dependent cells. Should you accept the latest version of a cell? Some very desirable optimizations may be implemented with new cell versions, but so, too, may be a dependence on a library cell of which you’re completely unaware.

Design flows, IP library conventions, even project requirements, all point to the need for a flexible solution. IP interoperability is an important but often overlooked aspect of SoC design that can be validated early and often in the design and chip assembly stages of the design. Many CAD groups write their own scripts to try to validate these conditions, but development and maintenance of custom code is time-consuming and costly. An automated method that can evaluate the cells in a design (including version numbers) in conjunction with any interoperability rules that may exist and report conflicts back to the user would seem an obvious choice. Tools such as Calibre® PERC™ are giving designers the power to quickly and effectively validate this reliability aspect of their designs early in the design flow. Final verification of cross-domain issues and other reliability issues can be found with final sign-off decks.

Early identification of potential interoperability issues in your designs helps keep your projects on track in a repeatable and controlled manner. Being aware of the issues is the first step. Adding automated interoperability verification to your design flow to uncover dependencies and resolve interoperability conflicts helps you keep designs on schedule while ensuring the designs take advantage of optimizations that can improve design performance and reliability.


Matthew Hogan is a Product Marketing Manager for Calibre Design Solutions at Mentor Graphics, with over 15 years of design and field experience. He is actively working with customers who have an interest in Calibre PERC. Matthew is an active member of the ESD Association—involved with the EDA working group, the Symposium technical program committee, and the IEW management committee. Matthew is also a Senior Member of IEEE, and a member of ACM. He holds a B. Eng. from the Royal Melbourne Institute of Technology, and an MBA from Marylhurst University. Matthew can be reached at

Big sell: IP Trends and Strategies

Monday, March 10th, 2014

By Sara Ver-Bruggen, SemiMD Editor

Experts at the table: Continued strong growth for semiconductor intellectual property (IP) through 2017 has been forecast by Semico Research. Semiconductor Manufacturing & Design invited Steve Roddy, Product Line Group Director, IP Group at Cadence, Bob Smith, Senior Vice President of Marketing and Business Development at Uniquify and Grant Pierce, CEO at Sonics to discuss how the IP landscape is changing and provide some perspectives, as the industry moves to new device architectures.

SemiMD: How are existing SIP strategies adapting for the transition to 20 nm generation of system- on-chips (SoCs)?

Roddy: The move to 22/16 nm process nodes has accelerated the trend towards the adoption of commercial Interface and physical IP. The massive learning curve in dealing with new transistor structures (FinFET, fully depleted SOI, high-k) raised the price of building in-house physical IP for internal consumption, thus compelling yet another wave of larger semiconductor IDMs and fabless semi vendors to leverage external IP for a greater share of their overall portfolio of physical IP needs.

Pierce: With 20 nm processes, the number of SIP cores and the size of memory accessed by those cores is seeing double digit growth. This growth translates into tremendous complexity that requires a solution for abstracting away the sheer volume of data generated by chip designs. The 20 nm processes will drive the need for SoC subsystems that abstract away the detailed interaction of step-by-step processing. For example, raising the abstraction of a video stream up to the level of a video subsystem; the collection of the various pieces of video processing into a single unit.
In this scenario, the big challenge becomes integration of subsystem units to create the final SoC. Meeting this challenge places a premium value on SIP that facilitates the efficient management of memory bandwidth to feed the growing number of SoC subsystems in the designs. Furthermore, 20 nm SoC designs will also place higher value on SIP that helps manage and control power in the context of applications running across these subsystems.

Smith: We are seeing many of the larger systems companies bypassing 20 nm entirely and moving from 28nm process technologies to the upcoming generation of 16 nm/14 nm FinFET technologies. FinFET offers the benefits of much lower power at equivalent performance or much higher performance at similar power to existing technologies. While 20 nm offers some gains, there are compelling competitive reasons to move quickly beyond 28/20 nm.
The demand for FinFET processes will naturally push the demand for the critical SIP blocks needed to support SoC designs at this node. SIP providers will need to migrate SIP blocks to the new technology and, for the most critical, will need to prove them out in silicon. The foundries will need to encourage this activity as SIP will typically make up more than 60-70% of the designs that will be slated for the new FinFET processes.

SemiMD: Within the semiconductor intellectual property (SIP) SoC subsystems market, which subsystem categories are likely to see most growth and how is the market evolving in the near term?

Pierce: Internet of Things (IoT) is causing an explosion in the number of sensors per device that are collecting huge amounts of data to be used locally or in the cloud. However, many of these sensors will need to operate at very low power levels, off of tiny batteries or scavenged energy. Sensor subsystems will need to carefully integrate the required processing and memory resources without support from the host processor. Some of the most interesting and challenging sensor subsystems will be imaging-related, where the processing loads can be highly dynamic, but the power requirements can be particularly challenging. Additionally, MEMS subsystems will grow in importance because this technology will often be used for power harvesting in IoT endpoint devices.

Smith: High-speed interfaces will see the most growth. DDR is at the top with DDR typically being the highest performance interface in the system and also the most critical. The DDR interface is at the heart of system operation and, if it does not operate reliably, the system won’t function. Other high-speed interfaces especially for video will also see tremendous growth, particularly in the mobile area.

Roddy: The emergence of a ‘subsystems’ IP market is to date over-hyped. That’s not to say that customers of IP are content with the status quo of 2008 where many IP blocks were purchased in isolation from a multitude of vendors. Customers do want a large portfolio of IP blocks that they can quickly stitch together, with known interoperability, provided with useful and usable verification IP. For that reason, we’ve seen a consolidation in the semiconductor IP business within the past five years, accelerating even further in 2012 and 2013. Larger providers such as Cadence can deliver a broad portfolio of IP while ensuring consistency, common support infrastructure, consistent best-in-class verification, and lowered transaction costs. But what customers don’t want is a pre-baked black-box that locks down system design issues that are best answered by the SOC designer in the context of the specific chip architecture. For that reason we expect to see slow growth in the class of ready-made, fully-integrated subsystems where the cost of development for the IP vendor far outweighs the added value delivered.

SemiMD: How will third party SIP outsourcing models become more important as the industry embarks 20 nm generation SoCs and what are IP vendors doing to enable the industry’s transition to the 20 nm generation of SoCs?

Roddy: As the costs of physical IP development scale up with the increasing costs of advance process node design, more consumers of IP are increasing the percentage of IP they outsource. Buyers of IP will always analyze the make versus buy equation by weighing several factors, including the degree of differentiation that a particular piece of IP can bring to their chips. Fully commoditized IP is easy to decide to outsource. Highly proprietary IP stays in house. But the lines are never black and white – there are always shades of grey. The IP vendors that can provide rapid means to customize pre-existing IP blocks are the vendors that will capture those incrementally outsourced blocks. The Cadence IP Factory concept of using automation to assemble and configure IP cores is one way that IP vendors can offer a blend of off-the-shelf cost savings with an appropriate touch of value added differentiation.

Pierce: From a business perspective, SIP outsourcing is inevitable for all functions that are not proprietary to the end system or SoC. It will not be feasible to develop and maintain all the expertise necessary to design and build a 20 nm device. The demand to abstract up to a subsystem solution will drive a consolidation of SIP suppliers under a common method of integration, for example a platform-based approach built around on-chip networks. Platform integration will be a key requirement for SIP suppliers.

Smith: SIP vendors are looking to the foundries and/or large systems companies to become partners in the development of the critical IP blocks needed to support the move to FinFET.

SemiMD: Are there examples of the ‘perfect’ SIP strategy in the industry, in terms of leveraging internal and third party SIP?

Smith: Yes. Even the largest semiconductor companies go outside for certain SIP blocks. It is virtually impossible for any individual company to have the resources (both human and capital) to develop and support the wide variety of SIP needed in today’s most complex SoC designs.

Pierce: The perfect SIP strategy in the industry is one that readily enables use of any SIP in any chip at any time. Pliability of architecture over a broad range of applications is a winning strategy. Agile integration of SIP cores and subsystems will become a critical strategic advantage. No one company exemplifies perfect SIP strategy today, but the rewards will be great for those companies that get closest to perfection first.

Roddy: There is no one-size-fits-all IP strategy that is perfect for all SOC design teams. The teams have to carefully consider their unique business proposition before embarking on an IP procurement strategy. For example, the tier 1 market leader in a given segment is striving to define and exploit new markets. That Tier 1 vendor will need to push new standards; add new value-add software features; and innovate in hardware, software and business models. For the Tier 1, building key value-add IP in-house, or partnering with an IP vendor that can rapidly customize standards-based IP is the way to go. On the other end of the spectrum, the ‘fast follower’ company looking to exploit a rapidly expanding market will be best served by outsourcing as close to 100% as possible of the needed IP. For this type of company, speed is of the essence and critical is the need to partner with IP vendors with the broadest possible portfolio to get a chip done fast and done right.

SemiMD: What challenges and also what opportunities is China’s growing SIP subsystems market presenting for the semiconductor industry?

Roddy: China is one of the most dynamic markets today for semiconductor IP. The overall Chinese semiconductor market is growing rapidly and a growing number of Chinese system OEMs are increasing investment levels, including taking on SOC design challenges previously left to the semiconductor vendors. By partnering with the key foundries to enable a portfolio of IP in specific process technology nodes for mutual customers, the leading IP providers such as Cadence are setting the buffet table at which the Chinese SOC design teams will fill their plates with interoperable, compatible, tested and verified physical IP blocks that will ensure fast time to market success.

Pierce: China is a fast growing market for SIP solutions in general. It is also a market that highly values the time-to-market benefit that SIP delivers as the majority of China’s products are consumer-oriented with short design cycles. SIP subsystems will be the most palatable for consumption by the China market. However, because China has adopted a number of regional standards, there will be substantial pressure on subsystem providers to optimize for local standards.

Smith: We see tremendous opportunities in terms of new business for SIP from both established companies and many entrepreneurial startups. Challenges include pricing pressure and the concern over IP leakage or copying. While this has become less of an issue over the years, it is still a concern. The good news is that the market in China is very aggressive and willing to take risks to get ahead.

From SEMICON West 2013: Luc Van den hove of imec

Tuesday, July 30th, 2013
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2012 IP Challenges For The Semiconductor Industry

Thursday, August 16th, 2012

A company’s intellectual property (IP) is fundamental to its ability to innovate, develop new technologies and methods, and move forward in a competitive industry. SEMI is acutely aware that what distinguishes its key industries from many others is the relatively high percent of revenue that is reinvested into R&D.

On average, semiconductor equipment and materials companies invest 10-15 percent of their revenues back into R&D each year, with 2011’s R&D investment translating to $9-14 billion. Both semiconductor equipment and materials companies have unique challenges associated with their IP, but realizing a return on their R&D investment is still essential.

The SEMI IP survey was sent to a global group of SEMI members and almost half responded. Over 60 percent of companies reported that IP challenges have translated into an adverse impact on their companies. Three-fourths of the companies responding had pursued legal action against IP violators. In terms of the types of violations experienced, several areas were repeatedly mentioned; patent infringement and counterfeiting were the recurring themes, with some regions more problematic than others. The survey also asked whether the situation in each region was improving, worsening, or staying the same.

This survey information helps SEMI continue benchmarking the global evolution of IP as a key concern, and helps us prioritize our work and actions with governments and partners around the world—helping to raise the bar and level the playing field.

To download this white paper, click here.

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