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Posts Tagged ‘International Electron Devices Meeting’

Companies Ready Cobalt for MOL, Gate Fill

Thursday, December 21st, 2017

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By Dave Lammers

Cobalt for middle-of-the-line and trench contacts emerged at the International Electron Devices Meeting, as Intel, GlobalFoundries, and Applied Materials discussed how to best take advantage of cobalt’s properties.

For its forthcoming 10nm logic process, Intel Corp. used cobalt for several of the lower metal levels, including a cobalt fill at the trench contacts and cobalt M0 and M1 wiring levels. The result was much-improved resistivity and reliability, compared with the traditional metallization at those levels.

Cobalt was used for the local interconnects of the Intel 10nm process, improving line resistance by 60 percent. (Source: Intel)

Chris Auth, director of logic technology at Intel’s Portland Technology Center, said the contacted line resistance “provides a good indicator of the benefits of cobalt versus tungsten,” with a 60 percent reduction in line resistance and a 1.5X reduction in contact resistance.

While cobalt was used for the local interconnects, the upper 10 metal layers were copper, with a cobalt cap used for layers M2-M5 to provide a 50X improvement in electro-migration. Intel continued to use tungsten for the gate fill.

John Pellerin, a vice president at GlobalFoundries who directs global research and development, said GlobalFoundries decided that for its 7nm logic technology, ramping in mid-2018, it would replace tungsten with cobalt at the trench contact level, which is considered the first level of the middle-of-the-line (MOL).

“We are evaluating it for implementation into the next level of contact above that. Cobalt trench level contacts are process of record (POR) for the 7nm technology,” Pellerin said in an interview at the 2017 IEDM, held Dec. 2-6 in San Francisco.

High performance logic often involves four-fin logic cells to drive the maximum amount of current from the largest transistor width. “You have to get that current out of the transistor. That is where the MOL comes into play. Junction and MOL resistance optimization is key to taking advantage of a four-fin footprint, and it takes a multi-front optimization to take advantage of that equation.

Pellerin said the biggest challenge with tungsten trench contacts is that the CVD process tends to leave a seam void. “We are always fighting seam voids. With cobalt deposition we get an intrinsic resistance improvement, and don’t get seam voids by pushing tungsten down in there,” Pellerin said.

Tighter Metal Pitches

Scotten Jones, president of consultancy IC Knowledge (Boston), said semiconductor vendors will introduce cobalt when it makes sense. Because it is a new material, requiring considerable costs prior to insertion, companies will use it when they need it.

“Global has trench contacts, while Intel uses cobalt at three levels. But the reason is that Intel has a 36nm minimum metal pitch with its 10nm process, while Global is at 40nm with its 7nm process. It is only at the point where the line gets narrow enough that cobalt starts to make sense.”

Applied Cobalt Solutions

As cobalt begins to replace tungsten at the smaller-dimension interconnect layers, Applied Materials is readying process flows and E-beam inspection solutions optimized for cobalt.

Namsung Kim, senior director of engineering management at Applied Materials, said cobalt has a bulk resistivity that is similar to tungsten, but the barrier thickness required for tungsten at leading-edge transistors is swinging the advantage to cobalt as dimensions shrink.

Line resistance probability plot of cobalt versus tungsten at 12nm critical dimensions. (Source: Applied Materials)

“Compared with tungsten, cobalt has a very thin barrier thickness, so you can fill up with more material. At our Maydan Technology Center, we’ve developed a reflow process for cobalt that is unique,” Kim said. The cobalt reflow process uses an annealing step to create larger cobalt grain sizes, reducing the resistance. And because there is no source of fluorine in the cobalt deposition steps, a thin barrier layer can suffice.

At IEDM, Naomi Yoshida, a distinguished member of the technical staff at Applied, presented a paper describing Applied’s research using cobalt to fill a 5nm-logic-generation replacement metal gate (RMG). The fill is deposited above the high-k dielectric and work function metals, and at the 5nm node and beyond there is precious little room for the gap fill metal.

Yoshida said modern transistors use multiple layers of work-function metals to control threshold voltages, with high-performance logic requiring low Vt’s and IoT devices requiring relatively high Vt’s. After the different work function layers are deposited, the fill material is deposited.

At the 5nm node, Applied Materials estimates that the contacted poly pitch (CPP) will shrink to about 42nm, while the gate length (Lg) will be less than 12nm. “There is very limited space for the fill materials, so customers need a more conductive metal in a limited space. That is the major challenge,” Yoshida said in an interview at the IEDM.

Work Function Maintained

Naomi Yoshida: room for gate fill disappearing

The Applied R&D work showed that if the barrier layer for a tungsten fill is reduced too much, to a 2nm or 3nm TiN layer for example, the effective work function (eWF) degrades by as much as 500mV eWF and the total gate conductance suffers. With the CVD process used to deposit a tungsten RMG fill, there was “significant fluorine diffusion” into the work function metal layer in the case of a 2nm TiN barrier.

By contrast, the cobalt fill maintained the NMOS band-edge eWF with the same 2nm TiN barrier.

Gradually, cobalt will be adopted more widely for the contacts, interconnects, and RMG gate fill steps. “It is time to think about how to achieve more conductance in the gate material. Previously, people said there was a negligible contribution from the gate material, but now with the smaller gates at 5nm, gate fill metal makes a huge contribution to resistance, and barrier thickness reduction is important as well,” Yoshida said.

E-beam Inspection

Nicolas Breil: E-beam void inspection useful for cobalt contacts

Applied Materials also has developed an e-beam inspection solution, ProVision, first introduced in mid-2016, and has optimized it for inspecting cobalt voids. Nicolas Breil, a director in the company’s contact module division, said semiconductor R&D organizations are busy developing cobalt contact solutions, optimizing the deposition, CMP, and other steps. “For such a dense and critical level as the contact, it always needs very careful engineering. They key is to get results as fast as possible, but being fast can be very expensive.”

Amir Wachs, business development manager at Applied’s process diagnostics and control business unit in Rehovat, Israel, said the ProVision e-beam inspection system has a resolution of 1nm, at 10,000-20,000 locations per hour, taking a few hundred measurements on each field of view.

“Voids form when there are adhesion issues between the cobalt and TiN. One of the key issues is the correct engineering of the Ti nitride and PVD cobalt and CVD cobalt. To detect embedded voids requires a TEM inspection, but then customers get very limited statistics. There might be a billion contacts per chip, and with conventional TEM you might get to inspect two.”

The ProVision system speeds up the feedback loop between inspection and co-optimization. “Customers can assess the validity of the optimization. With other inspection methods, co-optimization might take five days to three weeks. With this type of analysis, using ProVision, customers can do tests early in the flow and validate their co-optimization within a few hours,” Wachs said.

Logic Densities Advance at IEDM 2017

Monday, December 18th, 2017

By Dave Lammers

The 63rd International Electron Devices Meeting brought an optimistic slant to transistor density scaling. While some critics have declared the death of Moore’s Law, there was little evidence of that — on the density front at least — at the IEDM, held Dec. 2-6 in San Francisco.

And an Intel engineering manager gave a presentation at IEDM that took a somewhat optimistic view of EUV lithography readiness, auguring further patterning improvements, starting with contacts and vias.

GlobalFoundries, which is skipping the 10nm node, presented its 7nm logic technology, expects to move into manufacturing in mid-2018. John Pellerin, vice president of global R&D, said the foundry has worked closely with its two lead customers, AMD and IBM, to define a high-performance-computing 7nm logic technology that achieves a 2.8X improvement of routed logic density compared with its 14nm technology.

Pellerin said the current 7nm process of record (POR) delivers “the right mix of performance, power, and area (PPA),” adding that GlobalFoundries plans to bring in EUV patterning at an undefined later point in the 7+ generation for further improvements.

Contact Over Active Gate

Chris Auth, director of advanced transistor development at Intel Corp., described a 10nm logic technology that sharply increased the transistor density compared with the 14nm generation, partly due to a contact-over-active-gate (COAG) architecture. The 10nm ring oscillator performance was improved by 20 percent compared with the comparable 14nm test vehicle.

Chris Auth, who presented Intel’s 10nm technology paper at IEDM, was surrounded by questioners following the presentation.

Auth said the COAG approach was a key contributor to Intel’s ability to increase its transistor density by 2.7 times over the company’s previous generation, to 100 million transistors per square millimeter of silicon. While the traditional approach puts the contact via over the isolation area, COAG places the contact via directly over the gate. Auth said the approach does require a second etch stop layer and other process complexities, but contributes “a sizable 10 percent reduction in area.” Elimination of the dummy gate for cell boundary isolation, and the use of cobalt at three layers (see related story), also contributed.

While there has been much hand wringing in the industry over the costs involved with multi-level patterning, Auth didn’t appear phased by it. Intel used a self-aligned quad patterning (SAQP) scheme to create fins with a tight pitch. The SAQP approach required two sacrificial layers, with lithography defining the first large pattern and four additional steps to remove the spacers and create the final lines and spaces.

The Intel 10nm fins are 46nm in height.

The SAQP approach starts by exposing a 130nm line, depositing the two spacers, halving the pattern to 68nm, and again to 34nm. “It is a grating and cut process similar to what we showed at 22nm, except it is SAQP instead of SADP,” using patterning to form a grating of fins, and cutting the ends of the fins with a cut mask.

“There were no additional lithography steps required. The result was fins that are tighter, straighter, and taller, with better drive current and matching” than Intel’s 14nm-generation fins, he said. Intel continued to use self-aligned double patterning (SADP) for M 2-5, and for gate patterning.

GlobalFoundries — which has been in production for 18 months with the 14nm process used by AMD, IBM, and others — plans to ramp its 7nm logic generation starting in mid-2018. The 7nm high-density SRAM cell measures .0269 um2, slightly smaller than TSMC’s published 7nm cell, while Intel reported a .0312 um2 cell size for its 10nm process.

Intel argues that the traditional way of calculating density improvements needs to be replaced with a metric that combines NAND and scan flip-flop densities. (Source: Intel)

GlobalFoundries chief technology officer Gary Patton said, “all of us are in the same zip code” when it comes to SRAM density. What is increasingly important is how the standard cells are designed to minimize the track height and thereby deliver the best logic cell technology to designers, Patton said.

EUV Availability Needs Improvements

Britt Turkot, senior principal engineer at Intel, discussed the readiness of EUV lithography at an IEDM session, giving a cautiously bullish report. With any multi-patterning solution for leading-edge silicon, including etch and CMP steps, placement error is the biggest challenge. With quad patterning, Turkot said multiple masks are involved, creating “compounded alignment errors.”

EUV has its own challenges, including significant secondary ions from the EUV photons. The key challenge for much of the decade, source power, seems to be partially resolved. “We are confident that the 250 Watts of source power needed for volume manufacturing will be ready once the field tools are upgraded,” she said.

Pellicles may be another challenge, with ASML expected to have a polysilicon-based pellicle ready in time for EUV production. However, she said a polysilicon membrane “does give quite a hit to the transmissivity” of the mask. “The transmissivity impact is quite significant,” she acknowledged during the Q&A period following her talk.

Intel has succeeded in repairing some mask defects, Turkot said, and implements pattern shifting so that other defects do not impinge on the patterned wafer.

Asked by a member of the audience about EUV availability or up-time, Turkot said “one day, availability can be great,” and less than good on other days, with “long unscheduled downs.” Intel is predicting 88 percent availability next year, she said in response to a question.

Pellicle Needed for Wiring Layers

Scotten Jones, president of semiconductor cost consultancy IC Knowledge (Boston), said companies may be able to get by without a pellicle for EUV patterning of contacts and via layers late next year. However, a pellicle will be needed for patterning the lower-level wiring layers, absorbing 10-15 percent of the photons and impacting EUV patterning throughput accordingly.

“Companies can do the contacts and vias without a pellicle, but doing the metal layers will required a pellicle and that means that a ton of work still needs to be done. And then at 5nm, the dose you need for the resist goes up dramatically,” Jones said, adding that while it will take some time for ASML to roll out the 250 W source, “they should be able to do it.”

GlobalFoundries will take possession of its second EUV scanner in December 2017, while Intel is believed to own four EUV systems.

Pellerin said GlobalFoundries defined the ground rules for its 7nm process so that the foundry can do a phased implementation of EUV without causing its customers “design discontinuity, bringing a benefit to design costs.”

John Pellerin, v.p. of R&D, said GlobalFoundries plans a phased implementation of EUV without “design discontinuity.”

The foundry will first do the hole levels and then move into the tight-pitch metal levels as mask defectivity improves. “The mask ecosystem needs to evolve,” Pellerin said.

Cost-per-Function on Track

In a keynote speech at IEDM, Lisa Su, the CEO of Advanced Micro Devices, said over the last 10 years the semiconductor industry has succeeded in doubling transistor density every 2-2.4 years. But she said the performance gains have been much smaller. “We are making progress, but it is taking a tremendous amount of work,” said Su, who received a best paper award at the IEDM 25 years earlier.

About 40 percent of the CPU performance improvement now comes from pure process technology, Su said, while the remainder comes from better microarchitectures, power management, and integration of system components such as an on-chip memory controller. While instructions per cycle are increasing at a 7 percent annual clip, Su said “the tricks have run out.”

Overall, the leading semiconductor companies seem to continue to make progress on transistor density. And costs per transistor may also be on track. Kaizad Mistry, co-director of logic technology development at Intel, contends that with its Intel’s 10nm process Intel’s per-transistor costs are actually better than the historical  curve.

Jones said the IC Knowledge cost analysis of TSMC’s processes indicates TSMC also is hewing to historical improvements on the per-transistor cost front. However, the foundries are catching up to Intel.

Intel Cadence Lagging

“What really strikes me is that Intel brought out its 45nm process in 2007, 32nm in 2009, and 22nm in 2011, but then it took three years to do 14nm. We are about to be in the year 2018, and Intel still doesn’t have its 10nm process done. It is a very nice process, but it is not out yet, and TSMC’s 7nm process is ramping right now. By the time Intel gets to 7nm, the foundries may be at 3nm. GlobalFoundries skipped a generation but is ramping its 7nm next year. All will have processes competitive to Intel at the same time, or even earlier,” Jones said.

While foundries such as GlobalFoundries, Samsung, and TSMC may be able to quickly offer advanced logic platforms, the wider semiconductor industry faces design cost challenges, Jones said. “Yes, the cost-per-transistor is going down, and that’s nice, but the cost of a design with finFETs is in the 100-million-dollar range. Intel can do it, but many smaller companies can’t afford to design with FinFETs.”

That is why both GlobalFoundries and Samsung are offering FD-SOI based platforms that use planar transistors, reducing design costs.

“The Internet of Things market is going to be nine million things, at relatively low volumes. IoT companies are finding it hard to justify the cost of a FinFET design, but with the cheaper design costs, SOI gives them an economical path,” Jones said.