By Mark LaPedus
The European Commission this week announced a collection of five major projects to boost Europe’s manufacturing competitiveness in electronics. The “pilot lines” include a previously announced, fully depleted silicon-on-insulator (FDSOI) project. Other projects involve 450mm, GaN, MEMS and power electronics. In fact, Soitec will lead one consortium, dubbed the French AGATE pilot line. The aim of this proposal is to show that gallium-nitride (GaN) technology can be manufactured in a standard process line, with adapted equipment at a cost-competitive level on 150mm wafers, while keeping open the route to 200mm substrates. GaN is an emerging technology for LEDs, RF and other applications.

Minera El Tesoro (MET), part of one of the largest mining groups in Chile, has built the first pilot plant in South America with Soitec’s Solar technology, installing four of its concentrator photovoltaic (CPV) systems.

At the Cowen & Co. technology event, Bob Halliday, CFO of Applied Materials, addressed the state of the semiconductor and equipment industries. He also outlined Applied’s prospects for the year.

The World Semiconductor Council wants to expand the scope of the Information Technology Agreement (ITA), a key trade pact that provides for duty-free treatment of certain information technology products, including semiconductors. The list of covered products has not been updated since ITA’s inception in 1996. The WSC cited two such semiconductor products that should be covered by an expanded ITA—multi-component integrated circuits and multi-chip packages (MCP). Inclusion of these devices in an expanded ITA would result in estimated global tariff savings of between $94 million and $188 million annually. In a statement, Ajit Manocha, SIA chairman and CEO of GlobalFoundries, said: “The consensus reached in the 2013 WSC Joint statement represents a significant step toward enacting sound policies that will open markets, increase consumers’ ability to benefit from semiconductor technology advances, maintain market-based competition, and protect the environment.”

At the 50th Design Automation Conference (DAC) in Austin, Texas, GlobalFoundries will unveil a comprehensive set of certified design flows to support its advanced processes. It will also unveil a set of certified design flows to support 2.5D IC product development.

Mentor Graphics has collaborated with GlobalFoundries to deliver 20nm design kits for the Olympus-SoC netlist-to-GDS platform.  In addition, Mentor Graphics announced that its Calibre physical verification platform has achieved version 0.1 of design reference manual (DRM) and SPICE model tool certification for TSMC’s finFET process. And, Mentor Graphics announced the application of its Capital software suite to the development of CaetanoBus’ flagship C5 coach.

Andras Poppe of Mentor Graphics and the Budapest University of Technology has been recognized by the JEDEC international standards organization for his contributions to the JESD51-5x series of thermal testing standards for LEDs.

Cadence announced that several of its system-on-chip development tools have achieved version 0.1 of design rule manual (DRM) and SPICE model tool certification for TSMC’s 16nm finFET process.  In addition, PMC has adopted Cadence’s physical verification system as signoff technology for its global design centers.

The Silicon Integration Initiative (Si2) has acquired the Compact Model Council (CMC). The CMC develops and standardizes compact models of electronic devices used within commercial circuit simulators across the electronics industry, including virtually all SPICE-class simulation.

PMC-Sierra has entered into a definitive agreement to acquire Integrated Device Technology’s enterprise flash controller business and certain PCI Express (PCIe) switch assets for $100 million.

Using IC Insights’ current worldwide GDP forecast of 3.0%, the most likely range for IC market growth in 2013 is still 3-7%.

In February, Semiconductor Intelligence forecasted 7.5% growth in the semiconductor market in 2013 and 12% growth in 2014. Although 1Q 2013 was weaker than expected, the general trends driving moderate growth are still in place. Still, the research firm has lowered its IC forecast for 2013 to 6%. It is still holding the 2014 forecast at 12% based on continued improvement in the global economy.

By Mark LaPedus
For years, Brazil has been trying to get a semiconductor industry off the ground. A government-backed entity called Ceitec operates a small-scale fab in Brazil. There are also several IC design centers in that nation. Last November, SIX Semiconductors emerged and announced plans to build a fab in Brazil. The venture includes a partnership between IBM and SIX Soluções Inteligentes, a technology company of EBX Group, and others. The group will invest R$1 billion, or US$513 million, to a fab in Ribeirão Neves. Recently, the group was on a job-recruiting mission in the United States. In total, there are 300 job positions available at SIX Semiconductors in Brazil.

Starboard Value LP, together with its affiliates, currently owns 7.4% of the outstanding common shares of chip-packaging IP provider Tessera. The investment firm wants to shake up the board and oust the CEO. This follows allegations that Tessera’s CEO may have been engaged in inappropriate behavior.

Front-end fab equipment spending is expected to be flat in 2013, remaining around $31.7 billion, according to SEMI. Front-end fab equipment spending is projected to hit $39.3 billion in 2014, a 24% increase, according to SEMI.

Semiconductor industry growth drivers and European market strategies were featured topics at the recent SEMI Industry Strategy Symposium (ISS) Europe 2013. In one area of growth, NXP believes that by 2022, about 20% to 25% of global passenger vehicles will be connected to intelligent traffic management infrastructure and/or in-vehicle networks.

The flexible and printed electronics community reports encouraging progress in the materials and process ecosystem needed for commercial production, according to SEMI.

RDA Microelectronics has begun volume shipments of its GPS LNAs for use in Samsung’s 3G handsets. Developed on silicon-on-insulator (SOI) CMOS process technology, RDA’s GPS LNA is a high-gain, small-size amplifier ideally suited for GPS, Galileo and GLONASS applications in 2G and 3G handsets.

RF chipmaker Skyworks Solutions said that its SOI switching technology is now being utilized by European, Japanese, Korean and North American car manufacturers for advanced infotainment systems.

Peregrine Semiconductor will collaborate with Murata on a multisource arrangement for RF switches and other components based on Peregrine’s UltraCMOS technology. UltraCMOS is based on a variant of SOI.

Cadence introduced design and verification IP supporting the new Mobile PCI Express (M-PCIe) specification.

Mentor Graphics announced several new capabilities for its Flowmaster simulation software solution for thermo-fluid systems. Mentor also intends to pay an annual cash dividend of $0.18 per share on its common stock.

Applied Materials has approved an 11% increase in the quarterly cash dividend from $0.09 to $0.10 per share, payable on June 13.

Spansion and United Microelectronics Corp. announced the joint development of a 40nm process that integrates UMC’s 40nm LP logic process with Spansion’s embedded charge trap flash memory technology. As part of the non-exclusive agreement, UMC is licensed to manufacture products based on this technology for Spansion.

Cortus, a provider of 32-bit processor IP, and speciality foundry Dongbu HiTek are teaming up to offer platform solutions. The design platforms will be based on the Dongbu HiTek 0.13-micron eFlash technology and Cortus APS3R processor and peripheral IP.

IDT has transferred the assets and design team of its smart-metering IC product lines to Atmel in an all-cash transaction.

Significant reductions in capital equipment spending among DRAM makers are expected to stabilize DRAM prices at a minimum, but more likely will help drive prices further upward throughout the balance of the year, according to IC Insights.

Capex budgets are also being trimmed for NAND flash (though not nearly as much as DRAM), and that, along with ongoing unit demand, has put upward pressure on ASPs for these memory devices as well.

By Mark LaPedus
Lux Research has released its top 10 emerging companies in 2012. It features leaders in bio-based materials, 3D-printing, photovoltaics, drug delivery, energy efficiency and a fabless chip maker.

Soitec announced the grand opening of its North American solar manufacturing facility in San Diego. The concentrator photovoltaic (CPV) modules produced in San Diego will support hundreds of MWp of contracts for utility-scale projects in California.

IHS has released its top 10 predictions for the solar industry in 2013. Here’s one prediction: Many integrated players, particularly those based in China, will fold up shop in 2013.

Ericsson will take a non-cash charge related to its 50% stake in ST-Ericsson. Ericsson continues to believe that the modem technology has a strategic value for the wireless industry. ST-Ericsson is working on a technology based on SOI. Ericsson will continue to explore various strategic options for the future of ST-Ericsson assets. To acquire the full majority of ST-Ericsson is, however, not an option.

In a blog, Gold Standard Simulations has offered some advice to the SOI community: Metal-gate-first FD-SOI is good but gate-last could be spectacular.

Strain technology has been a key enabler for improving transistor performance. But there is a question whether stressors will maintain their effectiveness in IC scaling. Also which stressors will be most effective as the industry moves from planar to finFETs? According to a paper from Applied Materials and Synopsys at IEDM, the answer is clear: “S/D epitaxy remains an effective source of strain engineering for both aggressively and conservatively scaled finFETs. Not merging the S/D epitaxy between adjacent fins and recess etch into the fin before S/D epitaxy is recommended for maximizing the gain. With high active P concentration Si:C becomes an effective stressor for NMOS. Contact and gate metal fills provide new knobs for engineering strain in finFET devices for the 22nm node and remain effective with conservative scaling of contact/gate CD only.”

Worldwide wafer fab equipment (WFE) spending is forecast to total $27 billion in 2013, a 9.7% decline from 2012, according to Gartner. In 2012, WFE spending is on pace to reach $29.9 billion, a decrease of 17.4% from 2011 spending. The market is projected to return to growth in 2014.

North America-based manufacturers of semiconductor equipment posted a book-to-bill ratio of 0.79 in November, according to SEMI. This compares to a ratio of 0.75 in October.

Hewlett-Packard’s Inkjet and Printing Solutions division has reaffirmed its use of Mentor Graphics’ Pyxis Custom IC Design Platform as HP’s standard solution for custom IC design and verification. In addition, HP has selected Mentor’s Questa CDC as its standard solution for clock-domain crossing (CDC) verification.

Mentor announced comprehensive design, manufacturing, and post tapeout enabling support for Samsung’s 14nm IC manufacturing processes. In addition, Mentor announced advances in its T3Ster+TeraLED measurement and characterization hardware.

Ultratech has acquired the assets of Cambridge Nanotech. Based in Cambridge, Mass., Cambridge is a supplier of atomic layer deposition (ALD) systems.

ASML Holding and Cymer provided a status update regarding ASML’s previously announced pending acquisition of all of the outstanding shares of Cymer. ASML is responding to a request for additional information from the Antitrust Division of the U.S. Department of Justice regarding the transaction. This second request is part of the regulatory review process under the Hart-Scott-Rodino Antitrust Improvements Act of 1976. ASML and Cymer continue to anticipate completion of the transaction in the first half of 2013.

In a rare move, the Federal Trade Commission (FTC) is blocking a semiconductor acquisition. The FTC issued an administrative complaint seeking to stop Integrated Device Technology’s proposed $330 million acquisition of PLX Technology. The deal allegedly would give the combined firm a near-monopoly in the market for a type of integrated computer circuits called PCIe switches. In response, IDT and PLX have mutually agreed to terminate their merger agreement.

Micron posted a loss. “Unit shipments in both segments were impacted by unspecified manufacturing issues, although we do not believe these related to yields and more about execution on the back-end. Without these issues, we believe Micro would have beat consensus forecasts,” said Hans Mosesmann, an analyst with Raymond James. “Management provided a brief update on the Elpida acquisition, reiterating its expectation for the close sometime in 1H 2013. We also see positive strategic merits from the deal, including a significant addition to the company’s mobile DRAM portfolio (mobile DRAM share goes from ~4% to ~21%), with Elpida having a supply agreement with Apple.”

For the first time in 14 years, Nokia will not sit atop the global cellphone business on an annual basis at the end of 2012. Samsung is set to seize the mobile handset market’s top rank, according to IHS iSuppli.

Driven by continued demand for smartphones, tablet PCs, and other personal media devices, the total flash memory market (NAND and NOR) is forecast to grow 2% to $30.4 billion in 2012, surpassing the $28.0 billion DRAM market in sales for the first time, according to IC Insights.

IMS Research recently released its fourth annual video surveillance trends for the year ahead. Here’s one trend: The increased popularity of HD and megapixel resolution security cameras has been a hot topic in the video surveillance industry.

VLSI Research is raising its 2013 IC forecast to a +10% jump. “We are much more bullish and expect this to be an ASP-driven upturn due to the constraints in the capacity that the industry will face next year, especially in the memory market. As a result, we project IC units to increase 7% and ASPs to rise 3%. We’re seeing plenty of positive ‘Christmas black-hole’ indicators that the first half will be much hotter than thought before Thanksgiving.”

The semi equipment market has been downgraded to -16% in 4Q ’12, according to VLSI. The fab tool market in 2012 is expected to be minus 12.5%. 2013 is unchanged at -5.3%.

By Ed Sperling
Competition in semiconductor manufacturing has always been intense at the leading edge, but it’s now also heating up at older process nodes.

While it’s extremely difficult to compete with the likes of GlobalFoundries, Samsung, TSMC and Intel at 28nm and 22/20nm, where the investment in equipment and the manufacturing process can be measured in billions of dollars, the cost to build and fully equip fabs at 65nm and beyond is measured in millions. That significantly changes the ROI equation, particularly when mainstream is still being defined as 55nm and older nodes.

“Over the last few years we’ve seen the volume remain at 65nm,” said Walter Ng, vice president IP ecosystems at GlobalFoundries’ IP, during a panel discussion yesterday at the Global Technology Conference. “But there are a lot of companies doing things that are very relevant today even at 0.25 (microns).”

GlobalFoundries isn’t alone in spotting this trend. “Even though it’s sexy to talk about the leading edge, about 75% of ARM’s royalty comes from cores developed in 2006 and earlier,” said John Heinlein, vice president of marketing for the physical IP division at ARM.

ARM's Heinlein: Mainstream is 55nm and older.

The reasons are almost entirely economic, and they are fostering debate about the continued relevance of Moore’s Law beyond 20nm. That’s not to say the most advanced process nodes are wanting for customers or technology. But there are fewer customers at 28nm and 22nm than there were at 65nm, and the trend points to even fewer chips being designed at future nodes. Moreover, while chipmakers used to move from one process node to the next every two to three years, that is no longer a requirement. Even the most advanced devices have a mix of chips from different process technologies because the volume of chips needed to recoup design and production costs increases at each new process node—and at 14nm it’s hard to imagine many markets that can sustain the necessary volume.

These changes haven’t been lost on a handful of new startup foundries in places like China and Singapore, which see a successful business at older process nodes. In fact, the race for this part of the market has spawned a renewed interest in beefing up some of the technology, particularly when it comes to power and high performance. At 130nm, power was considered an afterthought, for example. But now that these chips are being combined with other semiconductors developed at the leading-edge processes, even they have to be retrofitted to deal with power issues at the architectural stages.

“If you have an existing product, you can look at adding oscillators or an EEPROM developed at an older node to reduce the system cost,” said Jeff Lukanc, director of engineering at IDT. “You have to look at the economics of the lower cost. It’s not always a slam-dunk, but if you look at mixed signal design and RF design, at the leading edge nodes it’s really tough.”

This will become critical in stacked die, where multiple die are thinned out and then stacked together. Power budgets need to be developed for the entire 3D package, not just a single die, so every component needs to be as power-efficient as possible.

“There’s a point at which a heterogeneous multichip package will become attractive,” Lukanc said.

When exactly that happens no one is certain, but foundries and design services companies say they are now creating demonstration chips that will be used in stacked configurations, and memory companies have announced stacked-die packages that are expected to be integrated with logic chips starting in 2012 through an interposer layer or using through-silicon vias.