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Posts Tagged ‘IC Design’

3D ASIP Conference Hears from EDA, IC Gear Companies

Friday, December 18th, 2015

By Jeff Dorsch, Contributing Editor

John Ferguson of Mentor Graphics provided the electronic design automation perspective on packaging technology at the 12th annual 3D ASIP conference in Redwood City, Calif.

“There’s a lot of interest and a lot of excitement about fan-out wafer-level packaging,” the director of marketing for Mentor’s Calibre DRC product line said, presenting “opportunities and challenges.”

The process of “bringing IC design and package design close together” presents many questions, Ferguson observed. Package design software usually runs on Windows, while EDA tools are on Linux, he noted. “It’s not so easy to mix and match them,” he said.

What manufacturing output to employ? GDSII, Gerber, or OBD++?

“Not all these things have answers yet,” Ferguson acknowledged. “The pieces are not all there yet. We’re partnering with several companies.”

Ferguson touted Mentor’s Xpedition Package Integrator suite for dealing with fan-out wafer-level packaging design. “It brings you across all the domains,” he said. The Mentor software will enable designers to “visualize it and optimize it,” he added.

The conference also heard from executives of three semiconductor equipment companies.

Markus Wimplinger, corporate technology development and intellectual property director at EV Group, spoke about temporary and permanent bonding in chip packaging, comparing chip-to-chip, chip-to-wafer, and wafer-to-wafer bonding.

Chip-to-chip and chip-to-wafer “are more flexible,” while wafer-to-wafer “has great promise,” he said.

David Butler, vice president of product management and marketing at SPTS Technologies, may have taken the prize for longest presentation title with “More Die, Stronger Die. Smaller, Thinner Packages Drives Die Singulation by Plasma Etch.”

“Saws damage die,” he said. “Plasma dicing is better.”

SPTS partnered with DISCO to develop effective die singulation through plasma dicing, according to Butler. “Plasma dicing provides about two times [improvement] in die strength for small die, thin die,” he said.

Rajiv Roy, vice president of business development and director of marketing for Rudolph Technologies, spoke about lithography and inspection requirements for fan-out wafer-level packaging, while touting the company’s experience in those areas.

Wafer and panel warpage can be a concern in FO-WLP manufacturing, he noted. “JetStep successfully measured and corrected for die placement errors,” Roy said, referring to Rudolph’s JetStep Advanced Packaging Lithography Systems, which can accommodate round or square/rectangular substrates.

Blog review September 8, 2014

Monday, September 8th, 2014

Jeff Wilson of Mentor Graphics writes that, in IC design, we’re currently seeing the makings of a perfect storm when it comes to the growing complexity of fill. The driving factors contributing to the growth of this storm are the shrinking feature sizes and spacing requirements between fill shapes, new manufacturing processes that use fill to meet uniformity requirements, and larger design sizes that require more fill.

Is 3D NAND a Disruptive Technology for Flash Storage? Absolutely! That’s the view of Dr. Er-Xuan Ping of Applied Materials. He said a panel at the 2014 Flash Memory Summit agreed that 3D NAND will be the most viable storage technology in the years to come, although our opinions were mixed on when that disruption would be evident.

Phil Garrou takes a look at some of the “Fan Out” papers that were presented at the 2014 ECTC, focusing on STATSChipPAC (SCP) and the totally encapsulated WLP, Siliconware (SPIL) panel fan-out packaging (P-FO), Nanium’s eWLB Dielectric Selection, and an electronics contact lens for diabetics from Google/Novartis.

Ed Koczynski says he now knows how wafers feel when moving through a fab. Leti in Grenoble, France does so much technology integration that in 2010 it opened a custom-developed people-mover to integrate cleanrooms (“Salles Blanches” in French) it calls a Liaison Blanc-Blanc (LBB) so workers can remain in bunny-suits while moving batches of wafers between buildings.

Handel Jones of IBS provides a study titled “How FD-SOI will Enable Innovation and Growth in Mobile Platform Sales” that concludes that the benefits of FD-SOI are overwhelming for mobile platforms through Q4/2017 based on a number of key metrics.

Gabe Moretti of Chip Design blogs that a grown industry looks at the future, not just to short term income.  EDA is demonstrating to be such an industry with significant participation by its members to foster and support the education of its future developers and users through educational licenses and other projects that foster education.

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