By Mark LaPedus
About every five years or so, a new and hot market emerges in the specialty foundry business that resembles a frenetic gold rush.

The last big gold rush occurred around 2008, when more than a dozen foundries jumped into the bipolar-CMOS-DMOS (BCD) market to capitalize on the booming power-management sector. Now, the next gold rush is centering on an emerging technology—the radio frequency (RF) silicon-on-insulator (SOI) market.

Today, IBM, STMicroelectronics and TowerJazz offer RF SOI foundry processes for the merchant market. Over time, analysts estimate that a dozen or more foundries could offer RF SOI. Altis Semiconductor and Grace Semiconductor have announced plans to enter the RF SOI fray. Two others, Lapis Semiconductor and Silanna, have put RF SOI on their foundry roadmaps. And sources indicate that GlobalFoundries, MagnaChip and TSMC are developing RF SOI or evaluating the technology.

Foundries are jumping on the RF SOI bandwagon amid a boom for select parts, particularly within the RF front-end for the latest smartphones and tablets. Typically, the RF front-end consists of power amplifiers (PAs), RF switches, tunable capacitors and filters. Generally, the PA and switch are based on gallium arsenide (GaAs), while the tunable capacitors and filters use various technologies.

RF SOI and its variant, silicon-on-sapphire (SOS), recently have made inroads for the RF switch—at the expense of GaAs. Most PAs are still based on GaAs, but the tide is slowly turning. For example, Peregrine Semiconductor is developing an SOS-based PA for a future smartphone at Apple, according to RBC Capital Markets.

Generally, RF chipmakers make GaAs-based devices in their own fabs. Chips based on RF CMOS, RF SOI and SOS generally are outsourced to the foundries. RF SOI is not a difficult technology to develop, but the real issue is that the sector could meet the same fate as BCD. As it turned out, the BCD market was not big enough to support a dozen foundries, prompting a shakeout in the arena.

In all likelihood, there is room for only a handful of RF SOI foundry players. “I would say IBM and TSMC are the only ones that have the economies of scale (in RF SOI),” said Doug Freedman, an analyst at RBC. “IBM is the leader in RF SOI right now, with TSMC trying to play catch-up. There are some other vendors like TowerJazz in the market, as well.”

From a supply/demand perspective, there is already ample RF SOI capacity to meet demand right now. “I have heard that capacity in RF SOI is adequate,” said Christopher Taylor, an analyst with Strategy Analytics. “I would have my doubts about the prospects of serious shortages barring compelling information to the contrary. Also, in light of the fact that RF SOI does not really push into the CMOS, small-node frontier, there is potentially quite a bit of capacity available from older fabs and foundries at the higher nodes.”

Rushing into RF SOI
The stakes are high, especially as RF content continues to increase in the latest mobile devices. In total, the PA market is expected to grow from $1.7 billion in 2008 to $3.8 billion by 2015, according to RBC. The multi-throw RF switch market is projected to grow from $262 million in 2008 to $1.2 billion by 2015, according to RBC. And the tunable capacitor market is expected to reach $500 million by 2016, it said.

“Driving this growth is rising handset and tablet units, which requires a greater amount of PA ICs,” RBC’s Freedman said. “Principally driving (RF switch) growth is rising radio bands. Driving (tunable capacitor) growth is the wider frequency range of bands and the need to reduce antenna size without performance trade-off.”

There is also an increase in design complexity amid a transition from 3G networks to the next-generation, 4G/LTE wireless standard. “LTE and carrier aggregation are thorny problems even in the best of situations,” said Michael Noonen, executive vice present of global sales, marketing, quality and design at GlobalFoundries. “You also want to be as Spartan as possible in the RF front-end design from a battery consumption standpoint.”

GlobalFoundries, which has been expanding its RF process offerings, is “very much interested” in RF SOI, Noonen said. “We have a lot of experience with SOI, but there are also other approaches in RF,” he said.

Indeed, OEMs face a series of complex device and process choices. For years, GaAs has dominated the RF landscape. GaAs has a larger energy gap and is faster than silicon, but it is more expensive to manufacture. RF CMOS, RF SOI, SOS and silicon-germanium (SiGe) are also in the mix. The RF version of SOI combines CMOS with a highly-resistive, thick-film SOI substrate.

RF SOI is an alternative to GaAs, with equivalent insertion loss and noise isolation characteristics. RF SOI also enables OEMs to integrate various chips on the same die. Another technology, SOS, makes use of an insulating sapphire substrate. And SiGe is built with silicon transistors to create RF circuits.
Meanwhile, after years of promises, RF SOI and its variants are finally cracking the RF front-end. OEMs are moving from GaAs pHEMT to RF SOI and SOS for the RF switch, said Paul Boudre, chief operating officer at Soitec, an SOI wafer supplier. “GaAs pHEMT will not disappear, but it will remain for more specific devices,” Boudre said.

Actually, the buzz started when Apple incorporated Peregrine’s SOS-based RF switches in the iPhone 5. Samsung’s Galaxy S4 and other smartphones are also using SOS-based switches, according to RBC. SOS is a proprietary technology that is only offered by Peregrine. Its SOS chips are made on a foundry basis by Lapis, MagnaChip and Silanna.

Rodd Novak, chief marketing officer of Peregrine, said SOS has better insulating properties than RF SOI. SOS also uses sapphire wafers, making it a more expensive than RF SOI. But the overall cost for SOS is declining. This is because sapphire wafers are ramping up in high-volume markets like LEDs, which will impact the cost of SOS, Novak said.

Peregrine recently rolled out a new version of SOS, based on 0.35-micron technology. “Before, we grew an epi (layer) on top of our sapphire process,” Novak said. “Now, we are taking a very clean silicon substrate and bonding that to the sapphire. That process enables better performance.”

Apple to drive SOI?
The fact that Apple and other OEMs have adopted SOS and RF SOI for the RF switch has given the technology some credence. It also has caused a stampede of foundry players looking to enter the RF SOI sweepstakes.

Now, with help from the foundries, RF chipmakers are looking to displace SOS-based switches with traditional and less-expensive RF SOI technology. “RF switches are typically based on GaAs pHEMT, SOS and SOI, with SOI gaining more and more market share away from the other and more expensive technologies,” said Marco Racanelli, senior vice president and general manager at TowerJazz.

In addition to cost, OEMs are also interested in capacity. In one effort to ensure supply, IBM recently signed a second-source foundry deal for its 0.18-micron, RF SOI process with Altis.

Besides the RF switch, the next big market for RF SOI and SOS could be the PA, with Apple emerging as the possible driving force. “We believe that Peregrine is developing a unique integrated PA solution that is targeting the next generation of Apple’s PA product needs,” said RBC’s Freedman. “(This) could add approximately $1.25 in content, assuming (Apple integrates) five to six single PAs in 3G smartphones. We note that in 4G, PA content opportunity rises to approximately $3.00 due to rising single chip PAs per device.”

In another example, Qualcomm recently rolled out the RF360, an RF front-end that includes a PA based on SOI. Today, however, the jury is still out for PAs based on RF SOI and SOS. For the PA, GaAs still has a higher power-efficiency over CMOS.

Still, the handwriting is on the wall for GaAs. “For the PA, SiGe BiCMOS has strong market share in WiFi, while GaAs HBT has strong market share in cellular. RF CMOS is relegated to the very low-end 2G/2.5G cellular space,” TowerJazz’ Racanelli said. “SOI for the PA is only in R&D and may not deliver the best performance by itself. But combined with switches and other functions, (SOI-based PAs) could become relevant as new architectures are adopted. Our view is that SiGe has the best tradeoff in performance. The cost structure is closer to CMOS/SOI. SiGe is likely to gain more ground in the future.”

Also in the RF front-end, there is a tunable capacitor, which tunes the antennae to boost efficiencies. Peregrine is selling SOS-based tunable devices. Paratek and STMicroelectronics are selling components based on barium strontium titanate (BST). And WiSpry is offering a MEMS solution.

“There are two vectors worth exploring here,” GlobalFoundries’ Noonen said. “If you can do something in CMOS, it will be done in CMOS. We will see other ways to approach the problem. Using a tunable capacitor based on MEMs, for instance, you can attack the problem from an entirely different angle.”

Indeed, in the RF front-end, there is no one-size-fits-all technology; OEMs likely will adopt several types of chips and processes. “We will also see more functionality in the RF subsystem,” Noonen said. “The idea is to bring RF into more of a mainstream technology.”

By Mark LaPedus
After its formation nearly 20 months ago, a 450mm consortium has reached its latest milestone by recently completing a cleanroom and installing the first 450mm demonstration tools in the facility.

The so-called Global 450 Consortium (G450C) also has set a goal to bring 450mm fabs into high-volume manufacturing at the 10nm or 7nm nodes by 2018. That gives the industry a little less than five years to develop the production tools for 450mm fabs, which are expected to cost a whopping $10 billion or more. Based in Albany, N.Y., the G450C has five members—GlobalFoundries, Intel, IBM, Samsung and TSMC.

But between now and 2018, there is a staggering amount of work to be done. Based on the current progress for select equipment, fab technologies and standards, the path towards 450mm will be a bumpy road and it’s unclear if the industry can meet the 2018 target.

The most obvious problem is lithography. For example, ASML Holding is not expected to deliver a production-worthy, 450mm version of its extreme ultraviolet (EUV) lithography scanner until 2018. Other challenges include lithographic cost-of-ownership and throughput.

On the wafer-processing front, Applied, Lam, TEL and others are moving full speed ahead in 450mm. TEL also is proposing an “open platform” standard—a move that has received a lukewarm response. Meanwhile, there is some movement in metrology, as a new consortium has recently been formed to address the challenges in 450mm.

And the industry is still debating over various 450mm fab standards, such as aisle space and ceiling height. There is even a debate over the type of cranes needed to install 450mm tools. Other standards, such as gas interface boxes, cooling water manifolds, and hookups for power, are also in the works.

That’s just the tip of the iceberg. The goal for the G450C is not only to help develop these technologies, but it also has the arduous task of getting the various players to synchronize on the roadmap. “It’s going to require a collaborative and concerted effort to introduce (450mm technology) in an efficient manner,” said Steve Johnston, director of external programs and technology strategy in the Technology Manufacturing Engineering Group at Intel, at a recent SEMI event. “All of this requires flawless and synchronized execution across the industry and at multiple levels.”

Avoiding past mistakes
Indeed, the industry hopes to avoid past mistakes. In the mid-1990s, the IC industry wanted to make the shift from 200mm to 300mm fabs. The equipment industry had the 300mm tools ready in the late 1990s, but chipmakers pushed out their 300mm fabs amid an IC downturn. Equipment vendors ended up holding the bag and lost a fortune. Shortly thereafter, chipmakers began to ramp up their 300mm fabs, but the events left a bad taste in vendors’ mouths.

Recently, Intel, Samsung and TSMC have been pushing for 450mm fabs. The argument is that the industry needs to make a wafer transition every 15 years to stay on Moore’s Law. Moving to 450mm wafers will give chipmakers a 2.25x boost in wafer area and a 30% cost reduction, according to chipmakers.

For some time, however, fab tool vendors were lukewarm about 450mm. There are only a handful of customers who would buy 450mm tools, and it’s unclear who will foot the R&D bill for the technology.

More recently, 450mm has become a reality. Intel and TSMC have outlined plans to build 450mm fabs. And in 2011, the G450C was established at the College of Nanoscale Science and Engineering’s NanoTech Complex. The G450C recently opened a cleanroom. Its roadmap also calls for 450mm pilot lines in 2015 and 2016, with high-volume production targeted for 2018.

“Synchronization and collaboration are very important to avoid the same type of issues we ran into in the late 1990s with the transition to 300mm,” said Kirk Hasserjian, corporate vice president for the Silicon Systems Group at Applied Materials.

There are other issues, namely supply-chain readiness, return-on-investment and R&D funding. “The (R&D funding) issue requires a very different business model,” Hasserjian said. “That has not been completely resolved. We have the consortium activities, which have provided some level of funding.”

Fab tool challenges
The industry has moved to fund at least one technology, namely lithography. Intel, Samsung and TSMC recently invested in ASML, in an effort to accelerate ASML’s efforts in 450mm and EUV. And with separate funding from Intel, Nikon is developing a 193nm immersion scanner for 450mm.

ASML itself has initiated 450mm programs on two separate platforms and four wavelengths, including EUV. The goal is to deliver “early version tools” in 2015 to 2016, with 450mm production systems due out by 2018, said Jim Koonmen, general manager of Brion Technologies, a division of ASML.

The development of a 450mm EUV scanner is expected to be a herculean effort. Today, ASML is struggling to deliver 300mm EUV tools amid delays with the power sources. Cost is also an issue, as ASML’s pre-production EUV scanners cost $100 million or more per unit today.

Throughput is also an issue. The throughput for a 450mm scanner in general is projected to be only about one-half of a 300mm tool, Koonmen said. A 300mm tool has a throughput of about 250 wafers per hour (wph), while a 450mm system can run 100-125 wph at 1.1x the cost, he said.

“If you look at the entire semiconductor process, there are steps that do get a lot of leverage from larger wafer sizes and can realize cost reduction,” he said. “Unfortunately, with lithography, there simply isn’t that much of a benefit in going to larger wafer sizes. We are scanning as fast as we can. The number of fields is going to increase when we go to larger wafers, but that just means your throughput for each 450mm wafer is going to go down. So you’ve got double the number of fields, but you are going at half the throughput. That in itself is not easy to do. In order to handle a 450mm wafer, you need to have larger stages with larger masks, and that creates a whole bunch of issues for us.”

Meanwhile, amid the problems with EUV, the industry is hedging its bets by developing 193nm immersion scanners for 450mm. Optical is a proven technology, but the solution is expensive. At 10nm or 7nm, chipmakers must also use expensive multiple patterning schemes.

Delivery schedules for 193nm immersion are more certain, however. “450mm is expected to be in production by 2018,” said Hamid Zarringhalam, executive vice president at Nikon Precision. “We will ship development tools earlier than that.” By 2015, Nikon plans to ship “early learning tools” based on 193nm immersion for 450mm, Zarringhalam said. Nikon has already garnered “multiple orders” for the systems, he added.

On the wafer processing side, there are also some technical and cost challenges. “Prices could rise 30% to 50% for 450mm tools, as they did when the wafer size shifted to 300mm from 200mm,” said analyst David Motozo Rubenstein, who is also the author of a blog entitled “Chips and Dips.”

Applied, Lam, TEL and others are developing standalone 450mm tools. TEL also is proposing the idea of having an “open and modular platform” for 450mm. This would enable fab tool vendors to develop various plug-and-play process modules for the open platform, thereby reducing costs and development times. TEL and its rivals could develop modules for the platform. “The open platform is a concept for the 450mm high-volume manufacturing era,” said Aki Sekiguchi, vice president and general manager for SPE marketing at TEL.

The open platform could benefit smaller companies that don’t have the resources to develop standalone tools. But larger companies are not eager to endorse an open platform, because it will give its rivals a competitive edge. “We are looking at it,” said Applied’s Hasserjian. “We are not doing what TEL is doing and advocating a modular platform.”

Metrology challenges

Another challenge is the development of 450mm metrology gear. “There are not many companies that can invest six years in advance,” said Menachem Shoval, chairman of Metro450, an Israeli-based consortium that is developing 450mm metrology technology. “Even without going 450mm, there are huge challenges for metrology in terms of going down from 22nm to 14nm to 10nm to 7nm.”

This is especially true when moving from today’s planar devices to finFETs at 22nm and beyond. “Going to 3D has created numerous challenges for us,” said John Allgair, senior member of the technical staff at GlobalFoundries. “We see tenfold measurement problems as we go to 3D. A lot of things you see in 2D tend to get amplified as we go to these 3D structures. Then, we see some real challenges when it comes to compositional analysis. In finFET devices, we’ve got compositional measurements like SiGe with a percentage of germanium and a percentage of boron on a 3D structure. That’s a very complex measurement. Finally, we try and do measurements on test structures. The test structures don’t always mimic what’s actually taking place on your device. That really adds to the complexity of trying to manufacture finFETs in a stable manner.”

One solution to the problem is to collaborate through a consortium, Metro450′s Shoval said. Last year, for example, the Metro450 consortium was formed by the following companies—Applied Materials, Nova, Jordan Valley, Nanomotion and Intel. The group also consists of four universities in Israel, with some 60% of the funding coming from the Israeli government.

“Each company develops its own technology,” Shoval said. “They are competing with each other. But we can collaborate on those parts which are common. We will work on platforms, but not on detection.”

One of the goals for the Metro450 group is to meet the design rule targets by 2017. It is also devising technologies that are 2.5x faster than 300mm, thereby meeting the cost requirements for 450mm. To reach its goals, the group is working on five specific technologies: wafer handling; sampling optimization; wafer damage and contamination; calibration; and data processing.

“We plan to complete our work in three years,” Shoval said. “So companies will still have about three years to complete the development of their high-volume manufacturing tools.”

By Mark LaPedus
Qualcomm has the highest market share for baseband solutions in handsets, resulting in a position far out in front of its competitors. ST-Ericsson has strong products on the market with competitive features. But one analyst at ABI Research questions why ST-Ericsson was broken up just as it finally came out with a highly competitive product, which was based on FD-SOI.

The worldwide semiconductor foundry market totaled $34.6 billion in 2012, a 16.2% increase from 2011, according to final results by Gartner. TSMC maintained the No. 1 spot in the rankings in 2012. Strong performance on 32nm yields and the availability of sub-45nm wafer capacity at the Dresden, Germany, fabs allowed GlobalFoundries to advance to the No. 2 position in 2012. UMC‘s market share decreased due to reduced wafer shipments. Driven by the wafers consumed by Apple, Samsung moved up four spots to the No. 5 position with 175.5% growth in 2012.

At this year’s Symposium on VLSI Technology, Intel will report technical details of its embedded DRAM with 22nm technology on bulk silicon wafers. Intel realized a 0.029mm2 DRAM cell capable of meeting >100us retention at 95 C. In the DC-DC converter session, Intel will present a switched capacitor step-down converter designed in a 22nm tri-gate CMOS technology. The VLSI Symposium is slated for June 11–14 in Kyoto, Japan.

At the VLSI event, STMicroelectronics and CEA-LETI will report six transistor SRAM (6T-SRAM) cells for high-density and low-voltage. The technology is fabricated at the 28nm node using FD-SOI technology for the first time.

At the VLSI Symposium, IBM and GlobalFoundries will report a SiGe channel tri-gate pFET with aggressively scaled fin width and gate length dimensions. It is fabricated using SiGe on an insulator substrate. Excellent electrostatic control down to Lg= 18nm and Wfin<18nm has been reported.

At the event, IMEC and GlobalFoundries will present the first demonstration of strained germanium channel pFETs fabricated on SiGe strain relaxed buffers, which is surrounded by STI region. Also, they introduced raised SiGe source/drain structures (Ge concentration= 75%) with an implant-free quantum well, replacement metal-gate process and germanide in contacts to solve void issues.

In addition, STMicrolectronics, Samsung, GlobalFoundries and IBM will report a 64nm pitch BEOL integration and material strategy. A self-aligned-via (SAV) approach was exploited for single pattern via extendibility, enabling via placement at CPP with a single mask.

SEMI reported that for the quarter ending Dec. 31, 2012, the worldwide photovoltaic manufacturing equipment book-to-bill ratio remained well below parity, at 0.45, for the seventh consecutive quarter. Booking levels continue to be low as PV manufacturers grapple with oversupply across the supply chain.

Khaled Juffali Company (KJC), a Saudi Arabian investment company, and Soitec, signed a memorandum of understanding (MOU) to cooperate in driving solar industry growth in Saudi Arabia and the Middle East. Under the MOU, the two companies will create a joint venture to market and sell concentrator photovoltaic (CPV) systems in the Kingdom of Saudi Arabia.

Hwa Chong Institution emerged as the winner of the Applied Materials Clean Tech Competition in Singapore. The project focused on utilizing calcium carbonate found in clam shells to remove toxic metal ions from waste water.

The separate hardware and software teams in companies are notorious for not being on the same page, thereby putting product development times and cost at risk. Mentor Graphics CEO Walden Rhines outlined some new and practical solutions to the problem.

Mentor Graphics announced the release of the Mentor Embedded Sourcery CodeBench Virtual Edition product, a native software environment for developing embedded systems pre- and post-silicon. The tool provides a tighter connection between hardware and software co-development, but allows software developers to use existing programming tools with extensions.

Cadence announced results for the first quarter of fiscal year 2013. Cadence also completed its previously announced acquisition of Tensilica.

Advantest will acquire W2BI, a provider of system level test automation software focusing on wireless communications.

Shipments of smart glasses may rise to as high 6.6 million units in 2016, up from just 50,000 in 2012, for a total of 9.4 million units for the five-year period, according to an upside forecast from IMS Research.

The worldwide mobile phone market grew 4% year over year in the seasonally slow first quarter of 2013 as smart phones out-shipped feature phones for the first time, according to IDC. Nokia, BlackBerry and HTC have dropped out of the top rankings.

By Jeff Chappell
There may have been a time when AMD founder Jerry Sanders famous quote: “real men (i.e., real companies) have their own fabs” rang true, but in today’s business climate it seems quaint at best.

Fabless or fab-lite business models are more popular than ever today, while some IDMs have turned back the clock, so to speak, looking to improve capacity utilization and revenues by offering foundry services—Intel and Samsung among them. Then there is the fact that the third-largest chipmaker in 2012, in terms of revenue, was a pure-play foundry.

As the 28nm node capacity ramp continues in the foundry market in 2013, following unexpected demand and capacity bottlenecks in 2012, today’s foundry market is the end result of market trends and forces with old roots. But those trends and forces have been compounded in modern times by extreme financial and market necessities, not to mention technology.

In one sense, however, at its core, the foundry market hasn’t changed since Taiwan Semiconductor Manufacturing Co. (TSMC) launched as the industry’s first pure-play foundry in 1987: Chip companies look to foundries, either as a customer or as a provider, to maximize productivity and thereby minimize costs. That part of the game hasn’t changed, whether it involves a component supplier designing power modules with 0.18-micron design rules for manufacturing on 200mm wafers, or one of the two GPU giants producing their next-generation graphics processors based on the latest technology.

The trend for years now has been fabless or fab-lite; even Sanders’ own AMD spun out its manufacturing arm several years ago to create one of the world’s largest pure-play foundries, GlobalFoundries. This has naturally in turn spawned the growth of the pure-play foundry market from its birth some 26 years ago.

Indeed, last year the overall foundry market enjoyed revenues of $29.6 billion, managing year-over-year growth of 12%, which is three times that of the chip industry over all in 2012. That growth caught everyone by surprise including the foundries themselves; 28nm capacity was tight for much of the year, even as yields improved dramatically—so much so that it reportedly impacted some capital equipment purchases, in spite of tight foundry capacity.

But that illustrates the biggest and most obvious change in the foundry industry in modern times: The foundries themselves are involved directly with developing leading-edge semiconductor technology. In fact, with the industry looking at the end of planar CMOS at the leading edge for some devices with the advent of 3D transistor architectures and the high-k materials they require, leading foundries no longer can rely on a mix of conventional scaling, publicly available data and equipment and process technology suppliers to get their jobs done. Research and development now must be within their purview, at least for those playing at the leading edge.

“Historically foundries don’t do R&D, their clients do it,” noted Dean Freeman, a research vice president at Gartner Research. That’s not so, today.

Nothing illustrates that fact better than TSMC’s R&D budget. In 2012 the company spent 33.8 billion NT, or about $1.13 billion, on R&D—a quarter of its revenue. This year the company plans to spend 40.4 billion NT, or about $1.35 billion, which includes adding some 500 people to its employee headcount, bolstering its R&D staff from 3,400 people to 3,900.

Indeed, leading foundries have joined the leading IDMs and technology consortia as purveyors of—not just manufacturers of—advanced technology.

While TSMC and its foundry brethren in the first tier of the pure-play market—Globalfoundries and United Microelectronics Corp. (UMC)—continue to build out 28nm capacity, they are also hard at work on the 20nm node and the subsequent hybrid 14/16nm finFET based on a 20nm back-end of line process. In fact, TSMC just announced first tapeouts of an ARM A-57 processor, based on the 64-bit ARMv8 processor series and built with 16nm transistor technology, including finFETs. This followed their rival’s announcement of a few months earlier. In February, GlobalFoundries announced a “first implementation” of a dual-core ARM A9 processor using the company’s 14nm-XM FinFET transistor architecture.

Follow the money
Being on the very leading edge of technology is driving growth among the first-tier foundries.

Like many others in the industry, TSMC and its chairman and CEO, Morris Chang, are quite bullish on the continued demand for 28nm technology as well as the development of 20nm technology. In general, 28nm designs, with their combination of lower power consumption and speedier transistors, have consequently proven cost-effective for a chip industry currently driven by mobile devices—smartphones, tablets and ultra lightweight notebooks. During TSMC’s review of its 2012 results earlier this year, Chang said the company will continue to aggressively grow its 28nm capacity and output; 2013 capacity and output will triple that of 2012, he said.

“It’s all about lower power with functionality and no sacrifice on the power requirements,” observed Kathryn Ta, managing director of strategic marketing for Applied Materials’ Silicon Systems Group. The equipment and process technology supplier’s foundry customers are seeing a need to move to 3D transistor architectures with minimal leakage, she said, because of those power requirements.

Development will continue at 20nm and 16nm as well at TSMC and its rivals. This year, 88% of the 9 billion NT that TSMC will spend on capital expenditures will go to 28nm, 20nm and 16nm capacity; an additional 5% will be spent on additional R&D equipment. Chang predicted that by Q3 of this year high-k metal gate production will surpass that of standard oxynitride gates, a gap that naturally will widen in Q4 and beyond.

“Enough discussions have taken place with enough customers … to lead us to believe that in both its first and second year of production (2014 and 2015, respectively) the volume of 20nm SoCs will be larger than that of 28nm in its first and second years of production (2012 and 2013),” Chang said.

He further noted that this represented the state of the art, and not just for the foundry industry, but for the industry as whole. This may indeed prove to be true in a few years as those 20nm and 16nm/14nm SoC devices move into production. It’s a far cry from the days when foundries were traditionally technological also-rans.

But then the first-tier foundries at the leading edge are still playing catch-up in the meantime with those IDMs at the leading edge, namely Intel. The world’s biggest chipmaker has kept Moore’s Law on track on the CPU side of the ITRS roadmap, last year having brought its Ivy Bridge processors to market. These feature 22nm transistors replete with finFETs; Intel’s own roadmap calls for 14nm designs to be in production in 2014; in terms of mobile SoCs like those the foundries are talking about, the company has promised its 22nm Atom SoCs will be in production in 2015.

“Intel seems to be able to continue to shrink because they spend a fortune on R&D,” said Gartner’s Freeman. “The foundries are pushing hard to catch up,” He noted that while both GlobalFoundries and TSMC have 16nm/14nm chips featuring finFETs in development, they are taking a shortcut, so to speak, by employing 20nm metal interconnects. “It’s close to what Intel is doing. Intel’s design may be more sophisticated, but the lithography is the same.”

Plenty of room, and business, at the trailing end
But not everybody in the foundry market is playing at the leading edge. The same market and industry forces that have induced the bigger pure-play foundries to move beyond their historical roles also have created a two-tiered pure-play foundry market. In the first tier are those that have the deep pockets to play in this space: TSMC, Globalfoundries, UMC, and to a lesser extent China’s Semiconductor Manufacturing International Corp. (SMIC).

Then there are the second-tier companies, those that are still fulfilling a traditional foundry role—at trailing edge processes, but nevertheless needed or even essential semiconductor manufacturing technology and capacity. Indeed, many second-tier foundries do quite well with their particular market niches and technologies. In the world of mobile consumer gadgets, including but not limited to smartphones and tablets, there are still many components fabricated on established, trailing-edge technology, such as sensors, microcontrollers and power components.

Even in 2013, where CPUs with 22nm transistors and mobile SoCs with 28nm transistors represent the current state of the art, some 40% of all silicon used to manufacture chips goes into mature devices fabricated on 200mm wafers. That’s typically 0.18-micron designs or larger. And much, if not most, of that is coming from pure-play foundries.

At the top of that second-tier foundry market, Israel’s TowerJazz, for example, has found a relatively comfortable niche making high-speed devices for a broad range consumer applications utilizing 0.13-micron designs and larger. It also makes CMOS image sensors with 0.16- and 0.11-micron design rules. In terms of financials, this has translated to record revenues: last year TowerJazz posted revenues of $638.8 million, an increase of 5% over the previous year.

Freeman suggested there are plenty of opportunities for these second-tier foundries. The so-called “Internet of Things,” for example, is a major driver behind sensor applications, as it is for the controllers needed to coordinate the data these sensors produce—data that can be managed via mobile Internet devices. These supplemental and complementary applications typically don’t need cutting-edge technology.

As has always been the case in the foundry industry, as leading-edge technology becomes trailing-edge, there will be new opportunities for second-tier foundries, as well. Some of the larger second-tier foundries eventually may have the opportunity to compete with first-tier companies head-to-head with 28nm capacity if they have deep-enough pockets to invest.

In the bifurcated smartphone market, for example, low-end smartphones that originally utilized chips manufactured with 40nm technology soon will migrate to chips with 28nm technology, as capacity ramps and it becomes even more cost effective, said Applied’s Ta. Even as the leading-edge players are driven beyond the 28nm node and the adoption of 3D gate architectures, the industry could very well see an extended 28nm node, driven by this market for lower-end smartphones and other mobile devices, she said.

But What About …
Things rarely ever prove to be so clearly defined in the chip industry. With players such as Samsung, Intel and IBM among others flirting with the foundry business, and some of the larger first-tier foundries suffering the same financial headaches that have plagued the IDMs in the past—problems that drove some of them to a fabless model in the fist place—there are some significant unknowns.

While 3D, high-k metal gate architectures, i.e, finFETs and the like, seem to be the wave of the near future, there are still those in the industry that tout the efficacy of fully depleted silicon-on-insulator (FD-SOI) as either an alternative to complement to 3D gate technology, for example.

IBM and its technology alliance partners have considered FD-SOI as a possible outcome of the semiconductor technology roadmap in the near future, Ta noted. “We see most of the effort on the finFET/Intel approach, but some of our customers are still talking about SOI,” perhaps used in some combination with finFETs, she added.

Gartner’s Freeman noted that Intel’s finFET devices are already fully depleted devices, although SOI could conceivably provide a bit less leakage; as such it may be an option at future nodes. Given the transistor speed and power usage achieved by its 22nm Atom processors, which are manufactured on top of bulk silicon technology, that seems unlikely though for Intel and those choosing to follow its lead. Freeman further observed that GlobalFoundries, once a proponent of FD-SOI, has backed off somewhat, although some of its largest customers remain committed to an FD-SOI strategy for the foreseeable future. IBM, for one, has publicly stated it will use FD-SOI, finFETs and stacked die together at future nodes.

But what does this mean for the leading-edge foundries? As always they will have to be able to manufacture what their customers want. It may be that some chipmakers will choose to go the FD-SOI route and that could prove a competitive opportunity for any foundry.

Another wild card that the top-tier foundries will need to take into account is the overlapping of technology nodes, which may become more pronounced with the extension of the 28nm node coupled with the rush to get 20nm devices into production. “It’s happening faster than previous node transitions have happened,” Applied’s Ta, noting that it’s driven by the low-power promise of finFETs. In the past node transitions typically took two to 2.5 years; “This time we may see a 1.5 year transition to finFETs,” she added.

Another question mark in the foundry market itself is SMIC. While most would still classify the Chinese foundry as a top-tier foundry, it is in a very real way straddling the gap between first and second tier. The company, once relatively close behind TSMC and UMC, has foundered in red ink and legal woes in recent years. While it has subsequently experienced an impressive turnaround financially under the helm of current CEO Tzu-Yin Chiu in 2012, it’s capital expenditures fell dramatically, even as capacity utilization hit 95% in Q2, and it is well behind its rivals in terms of technology.

Customer tapeouts of 28nm devices won’t take place until the end of this year; One of SMIC’s largest domestic customers, Spreadtrum, already has been forced to move to rival TSMC to meet its current plans for 28nm devices.

SMIC’s Chiu has said that the company’s 28nm technology will include both standard polysilicon oxynitride devices and high-k metal gates, and that it has plans to manufacture finFET devices at the 20nm node. In the meantime, it has found a saving grace in applications typically manufactured by second-tier players: smart cards, CMOS image sensors and power management chips.

Which way will SMIC go? Will it continue its impressive turn around by abandoning the leading edge or will it continue to play technological catch up? Or perhaps a little bit of both?

Time will tell. But it’s certainly an interesting time for the foundry business, and certain that for the foreseeable future the pure-play foundries will have to work hard at the cutting edge of semiconductor technology.

By Mark LaPedus
The industry is aggressively pursuing directed self-assembly (DSA) as an alternative patterning technology for future chip designs.

DSA, which enables fine pitches through the use of block copolymers, is in the R&D pilot line stage today. The fab tools, process flows and materials are basically ready, but there are still several challenges to bring the technology from the lab to the fab.

Perhaps the most glaring gap involves the ability to design chips around DSA. The existing EDA tools are not optimized for DSA, leaving many skeptics to ask a simple question: Can chipmakers design real and useful chips around DSA? Today, the answer is no or maybe someday.

Still, the lack of a design methodology opens up the door for new innovation and the emergence of a new field—design-for-DSA (DFD). In fact, there are some early methodologies surfacing for DFD. One idea is to tweak the current EDA tools for DSA. Another concept is to use 1D layouts. In another approach, Stanford University is developing a methodology using an alphabet soup of characters.

And not to be outdone, Cadence is working with GlobalFoundries to devise yet another approach. The technology, called Squish, uses an underlying classification engine and topological patterns as a means to enable IC designs using DSA, said Luigi Capodieci, director of DFM/CAD and an R&D fellow at GlobalFoundries.

“We have developed the first implementation of DSA modeling,” Capodieci said. “It’s a different way to look at physical design. The introduction of Squish topological patterns is a new way to look at how polygons and shapes come together. We can also enumerate how the patterns come together in a way we can match them.”

To make DSA viable, Capodieci also said that the EDA industry must look at the problem differently and develop an entirely new design methodology. “We need innovation,” he said. “We need a fundamental methodological change in how we put together the physical design.”

Assembling a design
DSA is not a next-generation lithography (NGL) tool per se. It’s more of a complementary and double-patterning scheme. There are two basic types of DSA methods: graphoepitaxy and chemical epitaxy. In graphoepitaxy, a guide is patterned using existing lithography tools. Using a track, the guide is spin-coated, rinsed and spin-coated again with copolymers. The copolymers self-assemble and the guide is then etched. In chemical epitaxy, self-assembly is guided by lithographically determined chemical patterns.

Over the last year, Albany Nanotech, CEA-Leti, IBM and IMEC have set up 300mm R&D pilot lines for DSA. Major chipmakers are doing their R&D work within these organizations and have shown their initial test structures using DSA.

It’s one thing to show intricate patterns and test structures, but it’s an entirely different matter to design chips around the technology. “It’s not good enough to have SEM pictures and show them at a conference,” said Lars Liebmann, a distinguished engineer for design technology co-optimization at IBM. “I can’t do anything with that. To really get your foot into the door you have to demonstrate some circuit-relevant patterns. If you show me a SEM, also show me a circuit pattern where a designer would say: ‘I can do something with that.’”

To satisfy the design community, DSA must meet some basic criteria. “You have to be able to integrate this patterning approach into a real CMOS flow. You have to demonstrate etch selectivity. And any new patterning technique should come with a set of compact models,” Leibmann said.

And, of course, there must be a robust design methodology and EDA tools. “The tools are not ready for DSA,” said Juan Rey, senior director of engineering at Mentor Graphics. “Essentially, the DSA community has developed a credible path for some layers. However, there is quite a bit of extensive research needed for full-chip-level development.”

All told, DSA still remains in the early stages of development and not ready for prime time. “We’ve seen some outstanding first steps in DSA,” Rey said. “But it’s pretty clear that more progress is required. The technology is still immature.”

Wanted: DFD
For some, the design-for-DSA debate centers around one question. “The question is not whether the EDA tools ready,” said GlobalFoundries’ Capodieci. “The question is what are the EDA tools required for DSA?”

One of the prevailing ideas is to use a complementary lithography approach as outlined by Intel. First, poly and metal lines are arranged into 1D gridded arrays. Then, a cut step is done to form a specified pattern. All told, DSA could enable lines and spaces, contact hole shrinks and even patterning a sea of fins.

Using a variant of complementary lithography, IBM has demonstrated the ability to pattern 29nm-pitch fins, which are etched onto a silicon-on-insulator (SOI) substrate. For DSA in general, IBM is using its own, in-house tools as well as conventional technology, said Kafai Lai, a senior scientist/engineer at IBM. “Our computational infrastructure basically builds upon conventional computational lithography platform. Many existing technical elements such as mask decomposition and coloring algorithms, model-based sub-resolution assist features (SRAF) and printable assist features (PRAF), source mask optimization (SMO), DSA optical proximity correction (DSA OPC), OPC verification, are still the building blocks of the DSA infrastructure. The optimum flow for DSA implementation depends on the feature types or the process layers of concern,” Lai said in a recent paper at SPIE.

“We have developed a set of computational lithography tools to enable us to evaluate the application of DSA to full-chip patterning. These toolsets involve new DSA-specific components such as DSA mask decomposition for guiding patterns, DSA-specific OPC or mask optimization and DSA-OPC verification. A fast DSA compact model is the backbone of these new CL components and we have reported such a fast DSA model for vias. A similar compact model for DSA L/S is under development now,” he added.

In any case, 1D layouts may enable DSA-friendly designs, but chipmakers must adhere to some rigid and restrictive design rules. “The designers will say I’m in left field, but I really think we need to spend more time working on the grid approach,” said Christopher Bencher, member of the technical staff at Applied Materials.

Using the 1D layout approach, memory makers could be the early adopters for DSA. For logic, Bencher and others have proposed a scheme that enables a sea of fins for use in future finFET designs. “For example, in the chemical epitaxy approach, you make holes everywhere to start with. Later, you will do a lithographic step, where you select which holes you want to keep and which ones you want to get rid of,” he said.

The downside to this approach is the inability to obtain a good aerial image of the holes. Still, Bencher said the 1D layout approach has several advantages over the rival alphabet-soup method. In this approach, a designer has the ability to choose a collection of shapes to develop a design. “As you try and stuff more and more (shapes on a pattern), the amount of positional error starts to go up,” he added.

The 1D gridded array approach also has some challenges. “You have to demonstrate some form of self-aligned trimming,” said IBM’s Leibmann. “Otherwise, in tight pitch gratings, it’s not useful at all because you can’t customize it. There is also no tool with the overlay capability to actually map that selectively without either damaging the fins you want to keep or residuals from the fins you want to erase.”

For this and other reasons, it’s unclear if the foundry industry can deploy this methodology. “Gridded with ultra-regular designs won’t work for us,” said Richard Farrell, a principal engineer at GlobalFoundries. “The biggest problem is that we incur a 3% to 5% area penalty for a gridded design, which is something we can’t give up.”

In the 1D layout approach, the IC industry would still require a new class of tools from the established EDA companies or startups willing to take a gamble. “This is possible, but you have to have a dedicated group of people with some capital who are willing to think differently,” said GlobalFoundries’ Capodieci. “But if we just wait for the commercial opportunity to present itself, we will miss the boat.”

Working with Cadence, GlobalFoundries proposes Squish, a design-for-DSA methodology that appears to combine the alphabet-soup approach and today’s pattern matching/classification technology. “This is like doing a Google search,” Capodieci said. “We actually create artificial structures in which patterns can come together.”

For example, the Squish methodology can create 1,716 or so different configurations or representations for a proposed IC layout. “We have the tools we need for classifying geometric and physical designs,” he said. “In literally a few hours, we can analyze a full-chip layout.”

Once this or another methodology is proven viable, the next step is to actually design and make a chip using DSA. “The next challenge for the industry is to process a couple of layers of a processor core using DSA,” he said. “We need a call for action.”

Crying Need For Tunable Materials
Tunable materials that adapt to environmental changes are in their infancy and currently limited, according to researchers at the Wyss Institute at Harvard University and Harvard’s School of Engineering and Applied Sciences.

Researchers at Harvard have devised a new class of adaptive materials made from liquid films and nanoporous elastic substrates. The new materials, inspired by tears in the act of crying, are based on a technology called Slippery Liquid-Infused Porous Surfaces (SLIPS).

The materials act as a coating, which repels anything it comes in contact with. Tunable materials can be used in fuel transport, textiles, optical systems, and other applications. For example, the materials could be used on a tent, which blocks light during the day and becomes water-repellent when it is raining. The materials could be used for self-adjusting contact lenses.

According to Harvard, a liquid flows within the pores, causing the smooth and defect-free surface to roughen through a continuous range of topographies. Then, the liquid is transformed into a finely tuned material, which can be dynamically adjusted from an optical transparent or wet state.

Harvard has demonstrated simultaneous control of the film’s transparency and its ability to manipulate various low-surface-tension droplets. “In addition to transparency and wettability, we can fine-tune basically anything that would respond to a change in surface topography, such as adhesive or anti-fouling behavior,” said Xi Yao, Wyss Institute and SEAS postdoctoral fellow, on the entity’s Web Site.

SOI Meets DSA
Using directed self-assembly (DSA), IBM has demonstrated the ability to pattern 29nm-pitch fins, which are etched onto a silicon-on-insulator (SOI) substrate. The process could enable next-generation finFETs based on SOI.

DSA uses templates to guide the phase separation of a block co-polymer film. As part of its DSA process, IBM has demonstrated an etch transfer technology. It has demonstrated the process using three integration materials: silicon, silicon nitride, and silicon dioxide based on tetraethyl orthosilicate.

The company studied the critical dimensions, line edge roughness (LER), and line width roughness during the pattern transfer process. IBM demonstrated that co-optimization of the materials and etch process can improve the final transferred pattern.

A fin patterning example for a logic library design.11(a) Fin design. (b) Directed self-assembly (DSA) fins after etch transfer into a silicon-on-insulator (SOI) substrate. The pitch of all dense lines is 29nm. Source: SPIE.

All told, IBM demonstrated that the use of post-etch annealing can further reduce the LER of DSA-patterned SOI lines from ∼3nm to less than 2nm. “By co-optimizing both the circuit design and patterning process, we expect to enable DSA patterning of semiconductor devices and circuits in a 300mm product development environment,” according to IBM on the SPIE Web site.

Battery Boost
Battery technology is not keeping up with Moore’s Law. Consumers want more and longer battery life in cellular phones, tablets and notebook PCs. And even emerging products such as electric vehicles require a longer battery life.

ETH-Zurich is looking at ways to optimize the electrodes in batteries, thereby making them more efficient. In doing so, ETH-Zurich is exploring the discharging and charging process in lithium ion electrodes. Using X-ray tomography, researchers are able to screen lithium ion battery electrodes and reconstruct the microstructures.

Researchers discovered that the electrodes are comprised of numerous particles. The smaller particles are on the edge of the cathode, while the larger ones are in the interior, according to researchers. Smaller particles form compact structures, while the larger ones tend to be porous.

Porosity has an impact on energy density and the speeds at which the ions move through the electrodes, according to researchers. “A lithium battery’s anode is mostly made of graphite,” according to ETH-Zurich’s Web site. “The tortuosity of graphite electrodes might be improved through the use of round graphite particles. The drawback here is that up to seventy per cent of the valuable raw material is wasted during production–one reason why many battery manufacturers still use plate-shaped graphite as an anode material.”

ETH-Zurich also discovered a facile synthesis of monodisperse colloidal tin (Sn) and Sn/SnO2 nanocrystals with mean sizes tunable over the range 9–23nm and size distributions below 10%. Electrochemical measurements demonstrated that 10nm Sn/SnO2 nanocrystals enable high Lithium insertion/removal cycling stability, according to researchers.

—Mark LaPedus

By Mark LaPedus
What impact will Intel have on the overall foundry business? In a research note, Weston Twigg, an analyst with Pacific Crest Securities, said: “Competition between Intel and the foundries, and the foundries and each other, should force high spending at the leading edge over the next two to three years. We remain bullish on equipment demand as long as Intel continues to play an aggressive role in the x86 versus ARM battle and its new foundry effort. We believe Intel is attempting to exploit its manufacturing technology advantage, which should pressure rivals TSMC and Samsung to maintain aggressive node transition plans.”

Staying in the leading-edge process technology race requires deep pockets. At 20nm and beyond, chipmakers will have to raise the CapEx ante to stay in the race. “Capital and production costs are rising faster than historic levels as logic and foundry producers migrate to 20nm and below,” Twigg said. “We expect equipment costs to rise 25% at the 22nm node and 28% at the 14nm node. New gate technologies, along with multiple-patterning steps and pitch-splitting techniques, are driving costs higher.”

GlobalFoundries has announced several milestones in the 2.5D/3D chip arena—a series of events that brings the technology one step closer to mass production.

In coordination with the National Academy of Sciences, GlobalFoundries helped host a conference titled, “New York’s Nanotechnology Model: Building the Innovation Economy” at the Hudson Valley Community College in Troy, N.Y.

Fabless ASIC house Socle Technology named Michael Noonen as its new chairman. Noonen is still the executive vice president of global sales and marketing at GlobalFoundries, which is an investor in Socle.

The Silicon Integration Initiative (Si2) said that the ESD Working Group of the OpenPDK Coalition has released an ESD Protection Design Flow Methodology. The ESD Working Group that developed this document included representatives from IBM, Intel, GlobalFoundries, NXP, Samsung, and STMicroelectronics.

Mentor Graphics announced availability of a comprehensive IP-to-system, UPF-based low-power verification flow.

ARM and Cadence disclosed the details behind their collaboration to implement the first ARM Cortex-A57 processor on TSMC’s 16nm finFET process.

Peregrine Semiconductor said that its UltraCMOS phase locked loop (PLL) frequency synthesizer and prescaler devices are designed into six Globalstar mobile communication satellites that were launched into orbit in February. UltraCMOS is an advanced RF silicon-on-Insulator (SOI) process.

Randhir Thakur, executive vice president and general manager of the Silicon Systems Group at Applied Materials, has been named a fellow of the Institute of Electrical and Electronics Engineers (IEEE).

Sematech executive Raj Jammy has joined Intermolecular as senior vice president and general manager of the semiconductor group.

RF Micro Devices announced the appointment of James Clifford, a former executive at Qualcomm, as vice president of foundry services.

More than one quarter of installed wafer capacity worldwide is dedicated to producing IC devices using process geometries smaller than 40nm, according to IC Insights.

In 2012, Intel retained the No. 1 market share position for the 21st year in a row, according to Gartner. Qualcomm climbed from No. 6 in 2011 to No. 3, and now trails only Intel and Samsung. Texas Instruments retained its fourth-place ranking, although Toshiba slipped to fifth place.

By Mark LaPedus

GlobalFoundries has announced several milestones in the 2.5D/3D chip arena–a series of events that brings the technology one step closer to mass production.

On the 3D front, GlobalFoundries has produced its first functional 20nm silicon wafers with integrated through-silicon vias (TSVs). At its Fab 8 facility in Saratoga County, N.Y., the silicon foundry vendor manufactured TSV test wafers using its 20nm-LPM process technology.

At the same time, the company also demonstrated a 32mm x 26mm interposer test vehicle for 2.5D chips. For some time, it has been developing a 65nm interposer manufacturing line within its Fab 7 complex in Singapore.

These are key steps to enable the eventual production of 2.5D and 3D chips. GlobalFoundries’ next step is to work in conjunction with its chip-assembly partners. At some point in the future, the OSATs will take the TSV-enabled wafers and then assemble and qualify 3D test vehicles for customers.

GlobalFoundries is making progress on other fronts. It is taping out a 3D design for an undisclosed customer and is working with two others on 2.5D. “2.5D is already here,” said David McCann, vice president of packaging technology at GlobalFoundries.  “Our industry has been talking about the promise of 3D chip stacking for years, but this development is another sign that the promise will soon be a reality.”

Other foundries, including IBM, Samsung, Tezzaron, TSMC and UMC, are also ramping up or developing their respective 2.5D/3D capabilities. But advanced chip stacking has several challenges and is still a few years away from mass production. Some estimate that volume production won’t occur until 2014 or 2015.

E. Jan Vardaman, president of TechSearch International, said the ability to obtain stacked memory is one of the stumbling blocks for 3D designs.  Devices based on the Wide I/O-2 standard are not due out until 2014 or 2015. “Everyone is waiting for the memory cubes,” Vardaman said. “The main question is when are the memory cubes going to ship?”

There are other issues as well. “I think that a number of people are trying out new materials to handle the bond/debond step. That takes more time,” she said. “Many companies indicated they still needed floor planning tools.”

Cost, of course, is still a factor. “Once the technology issues are resolved, the industry will need to bring up the yields in order to lower the cost,” she added.

Still, GlobalFoundries is moving full speed ahead in the arena. Last year, the company entered the 2.5D/3D chip-stacking foundry market and began to install the production tools within its Fab 8 complex.

Now, the company has developed the first 20nm silicon with TSVs, which measure 6u in diameter and 60u deep. “Our integration strategy works for TSV,” McCann said. It is also obtaining good results and yields with its silicon interposer technology in Singapore, he added.

GlobalFoundries’ strategy is far different than TSMC and Samsung, both of which are offering turnkey solutions. In contrast, GlobalFoundries will handle the traditional front-end steps and the “via creation” process. Then, the foundry vendor will hand off the traditional backend steps—such as temporary bonding/debonding, grinding, assembly and test—to the third-party packaging houses.

GlobalFoundries’ strategy, according to McCann, is more flexible and has more advantages over the turnkey model. “Our supply chain is an open model,” he said.

Like its rivals, GlobalFondries utilizes a “via-middle” approach to TSV integration. To overcome the challenges associated with the migration of TSV technology from 28nm to 20nm, the company has developed a proprietary contact protection scheme. This scheme enables the company to integrate the TSVs with minimal disruption to the 20nm-LPM platform technology, demonstrating SRAM functionality with critical device characteristics in line with those of standard 20nm-LPM silicon.

The Next Wonder Material
Graphene is generating a wave of interest in the semiconductor community. Supposedly, the next new and wonder material is molybdenite, a mineral of molybdenum disulfide (MoS2) that resembles graphene.

Some time ago, researchers from École Polytechnique Fédérale de Lausanne (EPFL) talked about building molybdenite chips. Now, EPFL has combined two materials, graphene and molybdenite, to enable a flash memory prototype.

Scientists have combined two materials with advantageous electronic properties – graphene and molybdenite – into a flash memory prototype that is very promising in terms of performance, size, flexibility and energy consumption. Source: EPFL

Graphene is a better conductor. It consists of one-atom-thick planar sheets, which are packed in honeycomb crystal lattice structures. But it doesn’t have a band gap, meaning it can’t be turned off in a system. Unlike graphene, MoS2 has an ideal band gap. MoS2 also has conducting properties.

The flash memory prototype from EPFL resembles a sandwich. On the bottom, there is a layer of graphene. The electrodes from this layer transmits electricity to the middle layer, which is based on MoS2. The MoS2 layer channels the electrons. On the top, there is an element made up of several layers of graphene, which captures electric charge.

On EPFL’s Web site, Andras Kis, director of EPFL’s Laboratory of Nanometer Electronics and Structures (LANES), said: “Combining these two materials enabled us to make great progress in miniaturization, and also using these transistors we can make flexible nanoelectronic devices.”

Mimicking The Brain
IBM has discovered a new way to operate chips using tiny ionic currents. These are streams of charged atoms that could mimic the event-driven way in which the human brain operates.

This means that nonvolatile chips using this novel phenomenon could be used to store and transport data in a more efficient manner.

Researchers from IBM have demonstrated the ability to reversibly transform metal oxides between insulating and conductive states. This is demonstrated by the insertion and removal of oxygen ions driven by electric fields at oxide-liquid interfaces.

Optical image of a typical ionic liquid (IL) gated device with a droplet of IL on top of the gate electrode and the oxide channel. The gold squares are pads used to make contact to the device via wire-bonding. On right is the magnified image of the device showing the channel (brownish yellow) and the gold electrical contacts (bright yellow). The contacts on the right and left of the channel are the source and drain contacts. The four other contact are used for 4-wire resistance & Hall measurements. (Credit: IBM)

Once the oxide materials, which are innately insulating, are transformed into a conducting state, IBM showed that the materials maintain a stable metallic state even when power to the device is removed.

To achieve this technology, IBM applied a positively charged ionic liquid electrolyte to an insulating oxide material, vanadium dioxide, and converted the material to a metallic state. The material held its metallic state until a negatively charged ionic liquid electrolyte was applied, to convert it back to its original, insulating state, according to IBM.

“Our ability to understand and control matter at atomic scale dimensions allows us to engineer new materials and devices that operate on entirely different principles than the silicon-based information technologies of today,” said Stuart Parkin, fellow at IBM Research, on the company’s Web site. “Going beyond today’s charge-based devices to those that use miniscule ionic currents to reversibly control the state of matter has the potential for new types of mobile devices. Using these devices and concepts in novel three-dimensional architectures could prevent the information technology industry from hitting a technology brick wall.”

Quantum Dot Solar
By embedding quantum dots within a collection of nanowires, the Massachusetts Institute of Technology (MIT) has found a way to boost the efficiencies of solar cells.

Solar cells based on quantum dots are still in their infancy. Still, the technology can be made in a room-temperature process, thereby avoiding the complications associated with traditional solar cell production. Another advantage of quantum dot solar cells is that they can be tuned to absorb light over a wide range, said Joel Jean, a doctoral student in MIT’s Department of Electrical Engineering and Computer Science.

MIT’s quantum dot solar cell was devised by using a layer of gold at the top. A layer of indium-tin-oxide was used at the bottom to form the two electrodes of the solar cell.

Then, researchers devised vertical arrays of zinc-oxide (ZnO) nanowires. The nanowires can decouple light absorption from carrier collection in lead sulfide (PbS) quantum dot solar cells. This, in turn, can increase power conversion efficiencies by 35%, according to MIT. The resulting ordered bulk heterojunction devices achieve short-circuit current densities in excess of 20 mA cm−2 and efficiencies of up to 4.9%, according to researchers.

All told, MIT believes it can boost overall efficiency beyond 10%.

—Mark LaPedus

By Ed Sperling
So many warnings about data overload have been issued over the past decade that people generally have stopped paying attention to them. The numbers are so astronomical that increases tend to lose meaning.

Nowhere is this more evident than in the semiconductor metrology world, where files are measured in gigabytes. And at each new process node, as the number of transistors and features increase—and the number of measurements increase—so does the amount of data that has to be stored and processed.

At the extreme edge of this barrage of data is critical dimension-scanning electron microscopy. Its files are measured in tens or hundreds of gigabytes. Just being able to decipher this much data requires a higher level of abstraction. There is no equipment powerful enough to process it within a reasonable time frame, and no way to retrieve that data quickly. In data terminology, it has to be mined just to be useful.

A scanning electron microscope, or SEM, takes measurements by sending out an electron beam, which interacts with electrons in the material being scanned. That sends back signals, which are mapped by the equipment. The more critical dimensions that need to be mapped, the greater the amount of data that needs to be processed and stored.

Source of the problem
“Everyone wants to use in-line characterization because you can see what you’re measuring,” said Carol Gustafson, metrology sector manager at IBM. “Other tools can’t show what it looks like. With CD-SEM you get numbers and images. A characterization lab can’t produce the quality of information that we can, but it’s a lot of data. And in the development phase, integrators and engineers like to look at in-chip information because it expands the number of targets you can look at.”

A lot of data is an understatement. Even IBM, which is credited with inventing data mining, won’t tackle this problem without help.

“In an area like this within IBM, at a 300mm wafer fab, with partners going in and out all the time, along with their customers, IT likes to keep a high view of the world,” said Gustafson. “But at 22nm we have more mask levels, and we have to measure more things. That also gives us the opportunity metrology, and that increases the amount of data because now we’re dealing with the complexity of developing and understanding an OPC cycle or budgeting in litho patterning and yields issues. There are also more locations to look at what’s going on.”

IBM isn’t alone in trying to navigate this sea of data. What’s new, though, is trying to make sense out of the data to improve everything from a chip’s performance and power to yield.

“Since you’re already taking the image, it’s a question of how you take full use of that data,” said John Allgair, senior member of the technical staff and Fab 8 patterning metrology manager at GlobalFoundries. “We’ve been able to do traditional measurements of a feature or a line width. We’ve also seen some progress to 2D information or being able to add a contour around a feature, so you get the entire feature instead of a point. But it would be nice if we also could get height information with that. Right now you can partially get there with signal modeling or by tilting, or a combination of both.”

That’s more data, though. Add in more mask layers and increased density and the amount of data goes up yet again.

Solutions
Both Applied Materials and Hitachi have been working to provide solutions to the data overload problem in CD-SEM. Of the two, Applied is the only one to bundle it with a multi-core machine. That machine contains 1 TB of RAM, which is large even by supercomputer standards.

Applied’s new data mining software, called TechEdge Prizm, provides CD-SEM tool/recipe/process issue identification, issue diagnosis, and toolfleet matching. That delivers the abstraction layer necessary for critical insights within a reasonable period of time. What used to take days or weeks now can be done in seconds, and that’s particularly important because metrology increasingly is moving into the realm of distributions rather than hard numbers.

Consider line-edge roughness (LER), for example, where fixed numbers no longer exist. Rather than just reporting the data, Prizm also provides the context necessary to utilize that data in a meaningful way. “When you’re dealing with line-edge roughness, there is not just one number,” said Paul Llanos, product development manager for Prizm data mining software at Applied. “You can apply different algorithms and get different numbers. Even in production, it requires more work for optimizing measurement strategies.”

LER was never an issue at older nodes because the measurement technology was sufficient to take readings that were accurate enough. But as feature sizes continue to shrink, even minor fluctuations in LER can impact performance for a device layer. There is a direct correlation between LER and resolution of a lithographic image, and like 193nm lithography, the entire manufacturing industry has been searching for a better solution. This is easier said than done, however. CD-SEM so far has proved to be the least damaging technology, which renders it the most trusted choice at current process nodes. Other technologies can take measurements more accurately, but frequently at the expense of the features being measured.

“At 20nm the data is not as clean as it was at older nodes,” said Llanos. “For challenging levels such as via-intrench, you can rebuild the target offline to consider different measurement strategies but only if the source data exists and can be accessed quickly.. This capability was being drowned out by the volume of data. What we’ve done is get smarter about aggregating the data, so you can get a more granular look at the wafer—what makes it run well versus poorly.”

This kind of data is being used in other portions of the manufacturing process, as well. “When we first rolled this out, it was only the CD-SEM engineers who had access,” said Dana Tribula, vice president and chief marketing officer for Applied Global Services at Applied Materials. “Now there are more than 100 engineers who use it on a regular basis.”

The genesis of a commercial version of this technology was less about a product than solving problems, though. Applied originally developed the technology as an internal tool, and IBM has been working with a variant of this approach for some time.

“Prizm puts lots of CD-SEM parameters together for us,” said IBM’s Gustafson. “We can look at multiple levels at the same time and multiple levels for the same litho level. We also can look at CD-SEM images that show changing aspects, patterns, SIT quality, and you can look at the parameters and images.”

The future
While this is a major step forward in managing the data, the reality is that resolution is falling short at advanced nodes. Lithography is both the key—and the stumbling block—to continued feature shrinks.

Approaches such as scatterometry are promising, but they have their own set of problems. The future also may entail a combination of what are now highly proprietary technologies. GlobalFoundries submitted a paper at SPIE that focused on combining measurements from multiple tools.

“The more tools interact the better,” said Gustafson. “The question is whether the vendors are willing to do that or whether IT will have to make it happen. At least we have industry standards on formatting these days. That’s good, because while the resolution is okay at 22nm, at 14nm certain levels are going to struggle. In particular, the critical levels are going to start to fall apart. And as we continue to shrink, measurements will become more critical and more complicated.”

She’s not alone in seeing that. GlobalFoundries’ Allgair said there are serious questions about what happens beyond 14nm. “CD-SEM is still our most frequently used of any tool out there, but if you look at the papers submitted this year there are concerns about its evolution and the improvements that will be possible.”

But no matter what technology ultimately wins out, the reality is that the amount of data will continue to increase significantly with every new tweak and every new technology hurdle. Just managing that data will be a growing problem. Effectively using it will be even tougher.