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2D Materials May Be Brittle

Tuesday, November 15th, 2016

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By Ed Korczynski, Sr. Technical Editor

International researchers using a novel in situ quantitative tensile testing platform have tested the uniform in-plane loading of freestanding membranes of 2D materials inside a scanning electron microscope (SEM). Led by materials researchers at Rice University, the in situ tensile testing reveals the brittle fracture of large-area molybdenum diselenide (MoSe2) crystals and measures their fracture strength for the first time. Borophene monolayers with a wavy topography are more flexible.

A communication to Advanced Materials online (DOI: 10.1002/adma.201604201) titled “Brittle Fracture of 2D MoSe2” by Yinchao Yang et al. disclosed work by researchers from the USA and China led by Department of Materials Science and NanoEngineering Professor Jun Lou at Rice University, Houston, Texas. His team found that MoSe2 is more brittle than expected, and that flaws as small as one missing atom can initiate catastrophic cracking under strain.

“It turns out not all 2D crystals are equal. Graphene is a lot more robust compared with some of the others we’re dealing with right now, like this molybdenum diselenide,” says Lou. “We think it has something to do with defects inherent to these materials. It’s very hard to detect them. Even if a cluster of vacancies makes a bigger hole, it’s difficult to find using any technique.” The team has posted a short animation online showing crack propagation.

2D Materials in a 3D World -222

While all real physical things in our world are inherently built as three-dimensional (3D) structures, a single layer of flat atoms approximates a two-dimensional (2D) structure. Except for special superconducting crystals frozen below the Curie temperature, when electrons flow through 3D materials there are always collisions which increase resistance and heat. However, certain single layers of crystals have atoms aligned such that electron transport is essentially confined within the 2D plane, and those electrons may move “ballistically” without being slowed by collisions.

MoSe2 is a dichalcogenide, a 2D semiconducting material that appears as a graphene-like hexagonal array from above but is actually a sandwich of Mo atoms between two layers of Se chalcogen atoms. MoSe2 is being considered for use as transistors and in next-generation solar cells, photodetectors, and catalysts as well as electronic and optical devices.

The Figure shows the micron-scale sample holder inside a SEM, where natural van der Waals forces held the sample in place on springy cantilever arms that measured the applied stress. Lead-author Yang is a postdoctoral researcher at Rice who developed a new dry-transfer process to exfoliate MoSe2 from the surface upon which it had been grown by chemical vapor deposition (CVD).

Custom built micron-scale mechanical jig used to test mechanical properties of nano-scale materials. (Source: Lou Group/Rice University)

The team measured the elastic modulus—the amount of stretching a material can handle and still return to its initial state—of MoSe2 at 177.2 (plus or minus 9.3) gigapascals (GPa). Graphene is more than five times as elastic. The fracture strength—amount of stretching a material can handle before breaking—was measured at 4.8 (plus or minus 2.9) GPa. Graphene is nearly 25 times stronger.

“The important message of this work is the brittle nature of these materials,” Lou says. “A lot of people are thinking about using 2D crystals because they’re inherently thin. They’re thinking about flexible electronics because they are semiconductors and their theoretical elastic strength should be very high. According to our calculations, they can be stretched up to 10 percent. The samples we have tested so far broke at 2 to 3 percent (of the theoretical maximum) at most.”

Borophene

“Wavy” borophene might be better, according to finding of other Rice University scientists. The Rice lab of theoretical physicist Boris Yakobson and experimental collaborators observed examples of naturally undulating metallic borophene—an atom-thick layer of boron—and suggested that transferring it onto an elastic surface would preserve the material’s stretchability along with its useful electronic properties.

Highly conductive graphene has promise for flexible electronics, but it is too stiff for devices that must repeatably bend, stretch, compress, or even twist. The Rice researchers found that borophene deposited on a silver substrate develops nanoscale corrugations, and due to weak binding to the silver can be exfoliated for transfer to a flexible surface. The research appeared recently in the American Chemical Society journal Nano Letters.

Rice University has been one of the world’s leading locations for the exploration of 1D and 2D materials research, ever since it was lucky enough to get a visionary genius like Richard Smalley to show up in 1976, so we should expect excellent work from people in their department of Materials Science and NanoEngineering (CSNE). Still, this ground-breaking work is being done in labs using tools capable of handling micron-scale substrates, so even after a metaphorical “path” has been found it will take a lot of work to build up a manufacturing roadway capable of fabricating meter-scale substrates.

—E.K.

Solid State Watch: May 13-19, 2016

Monday, May 23rd, 2016
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Solid State Watch: June 12-18, 2015

Thursday, June 18th, 2015
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Research Alert: March 10, 2015

Tuesday, March 10th, 2015

Graphene meets heat waves

In the race to miniaturize electronic components, researchers are challenged with a major problem: the smaller or the faster your device, the more challenging it is to cool it down. One solution to improve the cooling is to use materials with very high thermal conductivity, such as graphene, to quickly dissipate heat and thereby cool down the circuits.

At the moment, however, potential applications are facing a fundamental problem: how does heat propagate inside these sheets of materials that are no more than a few atoms thick?

In a study published in Nature Communications, a team of EPFL researchers has shed new light on the mechanisms of thermal conductivity in graphene and other two-dimensional materials. They have demonstrated that heat propagates in the form of a wave, just like sound in air. This was up to now a very obscure phenomenon observed in few cases at temperatures close to the absolute zero.Their simulations provide a valuable tool for researchers studying graphene, whether to cool down circuits at the nanoscale, or to replace silicon in tomorrow’s electronics.

Quasi-Lossless Propagation

If it has been difficult so far to understand the propagation of heat in two-dimensional materials, it is because these sheets behave in unexpected ways compared to their three-dimensional cousins. In fact, they are capable of transferring heat with extremely limited losses, even at room temperature.

Generally, heat propagates in a material through the vibration of atoms. These vibrations are are called “phonons”, and as heat propagates though a three-dimensional material,, these phonons keep colliding with each other, merging together, or splitting. All these processes can limit the conductivity of heat along the way. Only under extreme conditions, when temperature goes close to the absolute zero (-200 0C or lower), it is possible to observe quasi-lossless heat transfer.

A wave of quantum heat

The situation is very different in two dimensional materials, as shown by researchers at EPFL. Their work demonstrates that heat can propagate without significant losses in 2D even at room temperature, thanks to the phenomenon of wave-like diffusion, called “second sound”. In that case, all phonons march together in unison over very long distances. “Our simulations, based on first-principles physics, have shown that atomically thin sheets of materials behave, even at room temperature, in the same way as three-dimensional materials at extremely low temperatures” says Andrea Cepellotti, the first author of the study. “We can show that the thermal transport is described by waves, not only in graphene but also in other materials that have not been studied yet,” explains Cepellotti. “This is an extremely valuable information for engineers, who could exploit the design of future electronic components using some of these novel two-dimensional materials properties.”

UT Dallas technology could make night vision, thermal imaging affordable

Engineers at The University of Texas at Dallas have created semiconductor technology that could make night vision and thermal imaging affordable for everyday use.

Researchers in the Texas Analog Center of Excellence (TxACE) in the University’s Erik Jonsson School of Engineering and Computer Science created an electronic device in affordable technology that detects electromagnetic waves to create images at nearly 10 terahertz, which is the highest frequency for electronic devices. The device could make night vision and heat-based imaging affordable.

Presently, night vision and thermal imagers are costly, in part because they are made with specialty semiconductor devices or need isolation from the environment.

The UT Dallas device is created using Schottky diodes in Complementary Metal-Oxide Semiconductor (CMOS) technology. CMOS is used to make affordable consumer electronic devices such as personal computers, game consoles and high-definition TVs. In addition to being affordable, these devices could be more easily incorporated into smartphones.

“There are no existing electronic detection systems operating in CMOS that can reach above 5 terahertz,” said Zeshan Ahmad, lead author of the work, electrical engineering doctoral candidate and a research assistant in TxACE. “We designed our chip in such a way that it can be mass produced inexpensively, has a smaller pixel and operates at higher frequencies.”

Dr. Kenneth O, professor of electrical engineering in the Jonsson School and director of TxACE, noted the time it took for the field to reach this frequency in CMOS.

“This is a truly remarkable accomplishment,” said Dr. O, holder of the Texas Instruments Distinguished Chair.

“Twenty years ago, we were struggling to build CMOS circuits operating at 1 gigahertz. Now we are building circuits working at frequencies that are 10,000 times higher.”

The device could eventually be used for imaging animals near a road while driving at night; imaging intruders in darkness; providing light for night hiking; and estimating how many people are in a room to better control heating, air conditioning and light. It also could be used for other tasks such as finding pipes covered by concrete or walls.

“This technology could provide a very superior means to use the infrared portion of the spectrum,” said Dr. Robert Doering, research strategy manager at Texas Instruments.” Electronic control of generating infrared directly from CMOS integrated circuits will enable a wide variety of important new applications.”

The next step in the research is to realize CMOS devices that can reach even higher frequencies, up to 40 terahertz.

Breakthrough in OLED technology

Organic light emitting diodes (OLEDs), which are made from carbon-containing materials, have the potential to revolutionize future display technologies, making low-power displays so thin they’ll wrap or fold around other structures, for instance.

Conventional LCD displays must be backlit by either fluorescent light bulbs or conventional LEDs whereas OLEDs don’t require back lighting. An even greater technological breakthrough will be OLED-based laser diodes, and researchers have long dreamed of building organic lasers, but they have been hindered by the organic materials’ tendency to operate inefficiently at the high currents required for lasing.

Now a new study from a team of researchers in California and Japan shows that OLEDs made with finely patterned structures can produce bright, low-power light sources, a key step toward making organic lasers. The results are reported in a paper appearing this week on the cover of the journal Applied Physics Letters, from AIP Publishing.

The key finding, the researchers say, is to confine charge transport and recombination to nanoscale areas, which extends electroluminescent efficiency roll off the current density at which the efficiency of the OLEDs dramatically decreases — by almost two orders of magnitude. The new device structures do this by suppressing heating and preventing charge recombination.

“An important effect of suppressing roll-off is an increase in the efficiency of devices at high brightness,” said Chihaya Adachi of Kyushu University, who is a co-author of the paper. “This results in lower power to obtain the same brightness.”

“For years scientists working in organic semiconductors have dreamed of making electrically-driven organic lasers,” said Thuc-Quyen Nguyen of the University of California, Santa Barbara, another co-author. “Lasers operate in extreme conditions with electric currents that are significantly higher than those used in common displays and lighting. At these high currents, energy loss processes become stronger and make lasing difficult.

“We see this work, which reduces some loss processes, as one step on the road toward realizing organic lasers,” Nguyen added.

OLEDs operate through the interaction of electrons and holes. “As a simple visualization,” Adachi said, “one can think of an organic semiconductor as a subway train with someone sitting in every seat. The seats represent molecules and the people represent energetic particles, i.e., electrons. When people board the train from one end, they have extra energy and want to go to the relaxed state of sitting. As people board, some of the seated people rise and exit the train at the other end leaving empty seats, or ‘holes,’ for the standing people to fill. When a standing person sits, the person goes to a relaxed state and releases energy. In the case of OLEDs, the person releases the energy as light.”

Production of OLED-based lasers requires current densities of thousands of amperes per square centimeter (kA/cm2), but until now, current densities have been limited by heating. “At high current densities, brightness is limited by annihilation processes,” Adachi said. “Think of large numbers of people on the train colliding into each other and losing energy in ways other than by sitting and releasing light.”

In previous work, Adachi and colleagues showed OLED performance at current densities over 1 kA/cm2 but without the necessary efficiency required for lasers and bright lighting. In their current paper, they show that the efficiency problem can be solved by using electron-beam lithography to produce finely-patterned OLED structures. The small device area supports charge density injection of 2.8 kA/cm2 while maintaining 100 times higher luminescent efficiency than previously observed. “In our device structure, we have effectively confined the entrance and exit to the middle of the train. People diffuse to the two less crowded ends of the train and reduce collisions and annihilation.”

Research Alert: February 17, 2015

Thursday, February 19th, 2015

A new spin on spintronics

A team of researchers from the University of Michigan and Western Michigan University is exploring new materials that could yield higher computational speeds and lower power consumption, even in harsh environments.

Most modern electronic circuitry relies on controlling electronic charge within a circuit, but this control can easily be disrupted in the presence of radiation, interrupting information processing. Electronics that use spin-based logic, or spintronics, may offer an alternative that is robust even in radiation-filled environments.

Making a radiation-resistant spintronic device requires a material relevant for spintronic applications that can maintain its spin-dependence after it has been irradiated. In a paper published in the journal Applied Physics Letters, from AIP Publishing, the Michigan research team presents their results using bulk Si-doped n-GaAs exposed to proton radiation.

How Does Spintronics Work?

Modern electronic devices use charges to transmit and store information, primarily based upon how many electrons are in one place or another. When a lot of them are at a given terminal, you can call that ‘on.’ If you have very few of them at the same terminal, you can call that ‘off,’ just like a light switch. This allows for binary logic depending on whether the terminal is ‘on’ or ‘off.’ Spintronics, at its simplest, uses the ‘on/off’ idea, but instead of counting the electrons, their spin is measured.

“You can think of the spin of an electron as a tiny bar magnet with an arrow painted on it. If the arrow points up, we call that ‘spin-up.’ If it points down, we call that ‘spin-down.’ By using light, electric, or magnetic fields, we can manipulate, and measure, the spin direction,” said researcher Brennan Pursley, who is the first author of the new study.

While spintronics holds promise for faster and more efficient computation, researchers also want to know whether it would be useful in harsh environments. Currently, radioactivity is a major problem for electronic circuitry because it can scramble information and in the long term degrade electronic properties. For the short term effects, spintronics should be superior: radioactivity can change the quantity of charge in a circuit, but should not affect spin-polarized carriers.

Studying spintronic materials required that the research team combine two well established fields: the study of spin dynamics and the study of radiation damage. Both tool sets are quite robust and have been around for decades but combining the two required sifting through the wealth of radiation damage research. “That was the most difficult aspect,” explains Pursley. “It was an entirely new field for us with a variety of established techniques and terminology to learn. The key was to tackle it like any new project: ask a lot of questions, find a few good books or papers, and follow the citations.”

Technically, what the Michigan team did was to measure the spin properties of n-GaAs as a function of radiation fluence using time-resolved Kerr rotation and photoluminescence spectroscopy. Results show that the spin lifetime and g-factor of bulk n-GaAs is largely unaffected by proton irradiation making it a candidate for further study for radiation-resistant spintronic devices. The team plans to study other spintronic materials and prototype devices after irradiation since the hybrid field of irradiated spintronics is wide open with plenty of questions to tackle.

Long term, knowledge of radiation effects on spintronic devices will aid in their engineering. A practical implementation would be processing on a communications satellite where without the protection of Earth’s atmosphere, electronics can be damaged by harsh solar radiation. The theoretically achievable computation speeds and low power consumption could be combined with compact designs and relatively light shielding. This could make communications systems faster, longer-lived and cheaper to implement.

Novel solid-state nanomaterial platform enables terahertz photonics

Compact, sensitive and fast nanodetectors are considered to be somewhat of a “Holy Grail” sought by many researchers around the world. And now a team of scientists in Italy and France has been inspired by nanomaterials and has created a novel solid-state technology platform that opens the door to the use of terahertz (THz) photonics in a wide range of applications.

During the past decade, materials research has played an essential role in filling the THz gap, beginning with the development of THz quantum cascade lasers, which rely heavily on semiconductor heterostructured artificial nanomaterials. The development of THz spectroscopy, nanospectroscopy and THz imaging expanded the range of powerful tools for the characterization of a broad range of materials — including one-dimensional or two-dimensional semiconductors, biomolecules and graphene.

The missing piece? A complementary detection technology capable of fulfilling THz application-oriented needs in fields such as biomedical diagnostics, security, cultural heritage, quality and process controls, and high data-rate wireless communications that require ad hoc integrated generation and detection systems.

As the scientists report in the journal APL Materials, from AIP publishing, by using an approach that exploits the excitation of plasma waves in the channel of field-effect transistors (FET), they were able to create the first FET detectors based on semiconductor nanowires, designed in a plethora of architectures — including tapers, heterostructures and metamaterial-antenna coupled. While they were at it, they also developed the first THz detectors made of mono- or bi-layer graphene.

“Our work shows that nanowire FET technology is versatile enough to enable ‘design’ via lithography of the detector’s parameters and its main functionalities,” explained Miriam Serena Vitiello, lead author of the paper as well as research scientist and group leader of Terahertz Photonics Group in the Nanoscience Institute at CNR and Scuola Normale Superiore in Pisa, Italy.

What’s the nanowire detector capable of? It offers “a concrete perspective of application-oriented use, since it operates at room temperature — reaching detection frequencies greater than 3 THz, with maximum modulation speed in the MHz range, and noise equivalent powers that are already competitive with the best commercially available technologies,” Vitiello said.

In terms of applications, because the nanodetectors can be tapped for large-area fast imaging across both the THz and the sub-terahertz spectral ranges, don’t be surprised to see them commercialized in the near future for a variety of spectroscopic and real-time imaging applications — possibly even in the form of fast multi-pixel THz cameras.

Next, the scientists’ goals are to “push the device’s performance in the ultrafast detection realm, explore the feasibility of single photon detection by using novel architectures and material choices, develop compact focal plane arrays, and to integrate on-chip the nanowire detectors with THz quantum cascade microlasers,” noted Vitiello. “This will allow us to take THz photonics to a whole new level of ‘compactness’ and versatility, where it can finally begin to address many killer applications.”

Novel crumpling method takes flat graphene from 2-D to 3-D

Researchers at the University of Illinois at Urbana-Champaign have developed a unique single-step process to achieve three-dimensional (3D) texturing of graphene and graphite. Using a commercially available thermally activated shape-memory polymer substrate, this 3D texturing, or “crumpling,” allows for increased surface area and opens the doors to expanded capabilities for electronics and biomaterials.

“Fundamentally, intrinsic strains on crumpled graphene could allow modulation of electrical and optical properties of graphene,” explained SungWoo Nam, an assistant professor of mechanical science and engineering at Illinois. “We believe that the crumpled graphene surfaces can be used as higher surface area electrodes for battery and supercapacitor applications. As a coating layer, 3D textured/crumpled nano-topographies could allow omniphobic/anti-bacterial surfaces for advanced coating applications.”

Graphene–a single atomic layer of sp2-bonded carbon atoms–has been a material of intensive research and interest over recent years. A combination of exceptional mechanical properties, high carrier mobility, thermal conductivity, and chemical inertness, make graphene a prime candidate material for next generation optoelectronic, electromechanical, and biomedical applications.

“In this study, we developed a novel method for controlled crumpling of graphene and graphite via heat-induced contractile deformation of the underlying substrate,” explained Michael Cai Wang, a graduate student and first author of the paper, “Heterogeneous, Three-Dimensional Texturing of Graphene,” which appeared in the journal Nano Letters. “While graphene intrinsically exhibits tiny ripples in ambient conditions, we created large and tunable crumpled textures in a tailored and scalable fashion.”

“As a simpler, more scalable, and spatially selective method, this texturing of graphene and graphite exploits the thermally induced transformation of shape-memory thermoplastics, which has been previously applied to microfluidic device fabrication, metallic film patterning, nanowire assembly, and robotic self-assembly applications,” added Nam, whose group has filed a patent for their novel strategy. “The thermoplastic nature of the polymeric substrate also allows for the crumpled graphene morphology to be arbitrarily re-flattened at the same elevated temperature for the crumpling process.”

“Due to the extremely low cost and ease of processing of our approach, we believe that this will be a new way to manufacture nanoscale topographies for graphene and many other 2D and thin-film materials.”

The researchers are also investigating the textured graphene surfaces for 3D sensor applications.

“Enhanced surface area will allow even more sensitive and intimate interactions with biological systems, leading to high sensitivity devices,” Nam said.

Solid State Watch: January 23-29, 2015

Friday, January 30th, 2015

Solid State Watch: December 12-19, 2014

Saturday, December 20th, 2014
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Research Alert: November 18, 2014

Tuesday, November 18th, 2014

New process isolates promising material

After graphene was first produced in the lab in 2004, thousands of laboratories began developing graphene products worldwide. Researchers were amazed by its lightweight and ultra-strong properties. Ten years later, scientists now search for other materials that have the same level of potential.

“We continue to work with graphene, and there are some applications where it works very well,” said Mark Hersam, the Bette and Neison Harris Chair in Teaching Excellence at McCormick, who is a graphene expert. “But it’s not the answer to all the world’s problems.”

Part of a family of materials called transition metal dichalcogenides, molybdenum disulfide (MoS2) has emerged as a frontrunner material for exploration in Hersam’s lab. Like graphene, it can be exfoliated into atomically thin sheets. As it thins to the atomic limit, it becomes fluorescent, making it useful for optoelectronics, such as light-emitting diodes, or light-absorbing devices, such as solar cells. MoS2 is also a true semiconductor, making it an excellent candidate for electronics, and it historically has been used in catalysis to remove sulfur from crude oil, which prevents acid rain.

Hersam’s challenge was to find a way to isolate atomically thin sheets of this promising material at a larger scale. For the past six years, his lab has developed methods for exfoliating thin layers of graphene from graphite, using solution-based methods.

“You would think it would be easy to do the same thing for molybdenum disulfide,” he said. “But the problem is that while the exfoliation is similar to graphene, the separation is considerably more challenging.”

Hersam’s research is described in the paper “Thickness sorting of two-dimensional transition metal dichalcogenides via copolymer-assisted gradient ultracentrifugation,” which was published in the Nov. 13 issue of Nature Communications.

To sort graphene layers, Hersam used centrifugal force to separate materials by density. To do this, he and his group added the material to a centrifuge tube along with a gradient of water-based solution. Upon centrifugation, the denser species move toward the bottom, creating layers of densities within the centrifuge tube. Graphene sorts into single layer sheets toward the top, then bilayer sheets, trilayer, and so on. Because graphene has a relatively low density, it easily sorts compared to higher density materials.

“If I use the exact same process with molybdenum disulfide, its higher density will cause it to crash out,” Hersam said. “It exceeds the maximum density of the gradient, which required an innovative solution.”

Hersam needed to take the inherently dense material and effectively reduce its density without changing the material itself. He realized that this goal could be achieved by tuning the density of the molecules used to disperse MoS2. In particular, the use of bulkier polymer dispersants allowed the effective density of MoS2 to be reduced into the range of the density gradient. In this manner, the sheets of MoS2 floated at layered positions instead of collecting as the bottom of the centrifuge tube. This technique works not just for MoS2, but for other materials in the transition metal dichalcogenides family.

“Now we can isolate single layer, bilayer, or trilayer transition metal dichalcogenides in a scalable manner,” Hersam said. “This process will allow us to explore their utility in large-scale applications, such as electronics, optoelectronics, catalysis, and solar cells.”

Revolutionary solar-friendly form of silicon shines

Silicon is the second most-abundant element in the earth’s crust. When purified, it takes on a diamond structure, which is essential to modern electronic devices–carbon is to biology as silicon is to technology. A team of Carnegie scientists led by Timothy Strobel has synthesized an entirely new form of silicon, one that promises even greater future applications. Their work is published in Nature Materials.

Although silicon is incredibly common in today’s technology, its so-called indirect band gap semiconducting properties prevent it from being considered for next-generation, high-efficiency applications such as light-emitting diodes, higher-performance transistors and certain photovoltaic devices.

Metallic substances conduct electrical current easily, whereas insulating (non-metallic) materials conduct no current at all. Semiconducting materials exhibit mid-range electrical conductivity. When semiconducting materials are subjected to an input of a specific energy, bound electrons can move to higher-energy, conducting states. The specific energy required to make this jump to the conducting state is defined as the “band gap.” While direct band gap materials can effectively absorb and emit light, indirect band gap materials, like diamond-structured silicon, cannot.

In order for silicon to be more attractive for use in new technology, its indirect band gap needed to be altered. Strobel and his team–Carnegie’s Duck Young Kim, Stevce Stefanoski and Oleksandr Kurakevych (now at Sorbonne) –were able to synthesize a new form of silicon with a quasi-direct band gap that falls within the desired range for solar absorption, something that has never before been achieved.

The silicon they created is a so-called allotrope, which means a different physical form of the same element, in the same way that diamonds and graphite are both forms of carbon. Unlike the conventional diamond structure, this new silicon allotrope consists of an interesting open framework, called a zeolite-type structure, which is comprised of channels with five-, six- and eight-membered silicon rings.

They created it using a novel high-pressure precursor process. First, a compound of silicon and sodium, Na4Si24, was formed under high-pressure conditions. Next, this compound was recovered to ambient pressure, and the sodium was completely removed by heating under vacuum. The resulting pure silicon allotrope, Si24, has the ideal band gap for solar energy conversion technology, and can absorb, and potentially emit, light far more effectively than conventional diamond-structured silicon. Si24 is stable at ambient pressure to at least 842 degrees Fahrenheit (450 degrees Celsius).

“High-pressure precursor synthesis represents an entirely new frontier in novel energy materials,” remarked Strobel. “Using the unique tool of high pressure, we can access novel structures with real potential to solve standing materials challenges. Here we demonstrate previously unknown properties for silicon, but our methodology is readily extendible to entirely different classes of materials. These new structures remain stable at atmospheric pressure, so larger-volume scaling strategies may be entirely possible.”

“This is an excellent example of experimental and theoretical collaboration,” said Kim. “Advanced electronic structure theory and experiment have converged to deliver a real material with exciting prospects. We believe that high-pressure research can be used to address current energy challenges, and we are now extending this work to different materials with equally exciting properties.”

This work was supported DARPA and Energy Frontier Research in Extreme Environments (EFree), an Energy Frontier Research Center funded by the U.S. Department of Energy, Office of Science.

New way to move atomically thin semiconductors for use in flexible devices

Researchers from North Carolina State University have developed a new way to transfer thin semiconductor films, which are only one atom thick, onto arbitrary substrates, paving the way for flexible computing or photonic devices. The technique is much faster than existing methods and can perfectly transfer the atomic scale thin films from one substrate to others, without causing any cracks.

At issue are molybdenum sulfide (MoS2) thin films that are only one atom thick, first developed by Dr. Linyou Cao, an assistant professor of materials science and engineering at NC State. MoS2 is an inexpensive semiconductor material with electronic and optical properties similar to materials already used in the semiconductor industry.

“The ultimate goal is to use these atomic-layer semiconducting thin films to create devices that are extremely flexible, but to do that we need to transfer the thin films from the substrate we used to make it to a flexible substrate,” says Cao, who is senior author of a paper on the new transfer technique. “You can’t make the thin film on a flexible substrate because flexible substrates can’t withstand the high temperatures you need to make the thin film.”

Cao’s team makes MoS2 films that are an atom thick and up to 5 centimeters in diameter. The researchers needed to find a way to move that thin film without wrinkling or cracking it, which is challenging due to the film’s extreme delicacy.

“To put that challenge in perspective, an atom-thick thin film that is 5 centimeters wide is equivalent to a piece of paper that is as wide as a large city,” Cao said. “Our goal is to transfer that big, thin paper from one city to another without causing any damage or wrinkles.”

Existing techniques for transferring such thin films from a substrate rely on a process called chemical etching, but the chemicals involved in that process can damage or contaminate the film. Cao’s team has developed a technique that takes advantage of the MoS2′s physical properties to transfer the thin film using only room-temperature water, a tissue and a pair of tweezers.

MoS2 is hydrophobic – it repels water. But the sapphire substrate the thin film is grown on is hydrophilic – it attracts water. Cao’s new transfer technique works by applying a drop of water to the thin film and then poking the edge of the film with tweezers or a scalpel so that the water can begin to penetrate between the MoS2 and the sapphire. Once it has begun to penetrate, the water pushes into the gap, floating the thin film on top. The researchers use a tissue to soak up the water and then lift the thin film with tweezers and place it on a flexible substrate. The whole process takes a couple of minutes. Chemical etching takes hours.

“The water breaks the adhesion between the substrate and the thin film – but it’s important to remove the water before moving the film,” Cao says. “Otherwise, capillary action would case the film to buckle or fold when you pick it up.

“This new transfer technique gets us one step closer to using MoS2 to create flexible computers,” Cao adds. “We are currently in the process of developing devices that use this technology.”

Air-gaps in Copper Interconnects for Logic

Friday, October 31st, 2014

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By Ed Korczynski, Sr. Technical Editor, SST/SemiMD

The good people at ChipWorks have released some of the first public data on Intel’s new 14nm-node process, and the results indicate that materials limitations in on-chip electrical interconnects are adding costs. Additional levels of metal have been added, and complex “air-gap” structures have been added to the dielectric stack. Flash memory chips have already used air-gaps, and IBM has already used a subtractive variant of air-gaps with >10 levels of metal for microprocessor manufacturing, but this is the first known use of additive air-gaps for logic after Intel announced that a fully-integrated process was ready for 22nm-node chips.

Mark Bohr of Intel famously published data in 1995 (DOI:  10.1109/IEDM.1995.499187) on the inherent circuit speed limitations of interconnects, showing proportionality to the resistance (R) of the metal lines multiplied by the capacitance (C) of the dielectric insulation around the metal (Fig.1). The RC product thus should be minimized for maximum circuit speed, but the materials used for both the metal and the dielectric insulation around metal lines are at limits of affordability in manufacturing.

There are no materials that super-conduct electricity at room temperature, and only expensive and room-sized supercomputers and telecommunications base-stations can afford to use the liquid-nitrogen cooling that is needed for known superconductors to function. Carbon Nano-Tubes (CNT) and 2D atomic-layers of carbon in the form of graphene can conduct ballistically, but integration costs and electrical contact resistances limit use. Copper metal remains as the best electrical conductor for on-chip interconnects, yet as horizontal lines and vertical vias continue to shrink in cross-sectional area the current density has reached the limit of reliability. The result is the increase in the number of metal layers to 13 for 14nm-node Intel microprocessors, while IBM used 15 layers for 22nm-node Power8 chips.

Low-k Dielectrics and Pore Sizes

The dielectric constant (“k”) of silicon oxide is ~4, and ~3.5 with the addition of fluorine to the oxide (SiOF). Carbon-Doped Oxide (CDO or SiOC or SiOC:H) with k~3.0 has been integrated well into interconnect stacks. Some polymers can provide k values in the 2.0-2.7, but they cannot be integrated into most interconnects due to lack of mechanical strength, chemical resistance, and overall stability. Air has k=1, and there have been specialized chips made using metal wires floating in air, but lack of physical structure results in poor manufacturing yield and weak reliability.

A clever compromise is to use both SiOC with k~3 and air with k~1 in a stack, which results in an integrated k value weighted by the percent of the volume taken up by each phase. Porous Low-k (PLK) with 10% porosity allows for an integrated k of ~2.7 for modest improvement, but increasing porosity to just 20% for k~2.4 results in connected random pores that reduce reliability. To reliably integrate 20-30% air into SiOC, the pores cannot be random but must be engineered as discrete gaps in the structure.

In 2007, IBM announced that it would engineer air-gaps in microprocessors, but the company claimed to be using an extremely complex process for integration involving a self-assembled thin-film mask to anisotropically etch out holes between lines and then further isotropic etching to form elongated pores. Though relatively complex and expensive, this process allows for the use of any 2D layout for lines in a given metal layer.

Additive Air-gap Process-Design Integration

For fab lines that are still working with aluminum metal and additive dielectrics, air-gaps are a defect that occurs with imperfect dielectric fill. When not planned as part of the design, air-gaps formed in a lower-layer can be exposed to etchants during subsequent processing resulting in metal shorts or opens. However, Figure 2 shows that it is possible to engineer air-gaps by Chemical-Vapor Deposition (CVD) of dielectric material into line-space structures with proper process control and design layout restrictions. Twenty years ago, this editor worked for an OEM on CVD processes for dielectric fill, and the process can be tuned to be highly repeatable and relatively low-cost if a critical masking step can be avoided. In 1998, Shieh et al. from Stanford (Shieh, Saraswat & McVittie. IEEE Electron Dev. Lett., January 1998) showed proof-of-concept for this approach to lower k values.

Figure 2: CVD can be easily tuned to initially coat sidewalls (top), then pinch-off (middle), and finally form a closed pore (bottom) during one step. (Source: Ed Korczynski)

Four years ago at IEDM 2010, Intel presented details of how to engineer air-gaps using CVD. As this editor wrote at that time in an extensive analysis:

The lithographic masking step is needed for two reliability reasons. First, by excluding air-gap formation in areas near next-layer vias, alignment between layers can be more easily done. Second, wide spaces are excluded where the final non-conformal CVD step wouldnt automatically pinch-off to close the gaps; leaving full SiOC(H) in wider spaces also helps with mechanical strength. The next layer is patterned with a conventional dual-damascene flow, with the option to add air-gaps.

Now we know that Intel kept air-gaps on the metaphorical shelf by skipping use at the 22nm-node. The 2014 IEDM paper from Intel will discuss details of 14nm-node air-gaps:   two levels at 80nm and 160nm minimum pitches, yielding a 17% reduction in capacitance delays.

This process requires regularly spaced 1D line arrays as a design constraint, which may also be part of the reason for additional metal layers to allow for 2D connections through vias. Due to lithography resolution advantages with 1D “gridded” layouts, other logic fabs may soon run 1D designs at which point additive air-gaps like that used by Intel will provide a relatively easy boost to IC speeds.

Blog review October 20, 2014

Monday, October 20th, 2014

Matthew Hogan of Mentor Graphics blogs about how automotive opportunities are presenting new challenges for IC verification. A common theme for safety systems involves increasingly complex ICs and the need for exceptional reliability.

Anish Tolia of Linde blogs that technology changes in semiconductor processing and demands for higher-purity and better-characterized electronic materials have driven the need for advanced analytical metrology. Apart from focusing on major assay components, which are the impurities detailed in a Certificate of Analysis (CoA), some customers are also asking that minor assay components or other trace impurities must be controlled for critical materials used in advanced device manufacturing.

Karey Holland of Techcet provides an excellent review of SEMI’s Strategic Materials Conference. The keynote presentation, “Materials Innovation for the Digital 6th Sense Era,” was by Matt Nowak of Qualcomm. He discussed both the vision of the Internet of Things (IoT), the required IC devices (including analog & sensors) and implications to materials (and cost to manufacture) from these new IC devices.

The age of the Internet of Things is upon us, blogs Pete Singer. There are, of course, two aspects of IoT. One is at what you might call the sensor level, where small, low power devices are gathering data and communicating with one another and the “cloud.” The other is the cloud itself. One key aspect will be security, even for low-level devices such as the web-connected light bulb. Don’t hack my light bulb, bro!

Linde Electronics has developed the TLIMS/SQC System. Anish Tolia writes that this system includes an information management database plus SQC/SPC software and delivers connectivity with SAP, electronically pulling order information from SAP to TLIMS and pushing CoA data from TLIMS to SAP.

Ed Korczynski blogs about how IBM researchers showed the ability to grow sheets of graphene on the surface of 100mm-diameter SiC wafers, the further abilitity to grow epitaxial single-crystalline films such as 2.5-μm-thick GaN on the graphene, the even greater ability to then transfer the grown GaN film to any arbitrary substrate, and the complete proof-of-manufacturing-concept of using this to make blue LEDs.

Phil Garrou says it’s been awhile since we looked at what is new in the polymer dielectric market so he checked with a number of dielectric suppliers – specifically Dow Corning, HD Micro and Zeon — and asked what was new in their product lines.

Karen Lightman, Executive Director, MEMS Industry Group, had the pleasure to learn more about the challenges and opportunities affecting MEMS packaging at a recent International Microelectronics Assembly and Packaging Society (IMAPS) workshop held in her hometown of Pittsburgh and at her alma mater, Carnegie Mellon University (CMU).

Ed Korczynski blogs that The Nobel Prize in Physics 2014 was awarded jointly to Isamu Akasaki, Hiroshi Amano, and Shuji Nakamura “for the invention of efficient blue light-emitting diodes which has enabled bright and energy-saving white light sources.”

Yes, GlobalFoundries is hot on FD-SOI. Yes, Qualcomm’s interested in it for IoT. Yes, ST’s got more amazing low-power FD-SOI results. These are just some of the highlights that came out of the Low Power Conference during Semicon Europa in Grenoble, France (7-9 October 2014) blogs Adele Hars.

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