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Applied Materials Fields Cobalt Solution for MOL

Thursday, June 7th, 2018

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By Pete Singer, Editor-in-Chief

Applied Materials has introduced a set of processes that enable cobalt to be used instead of tungsten and copper for contacts and middle-of-line interconnects. Higher levels of metal, which typically have wider dimensions, will still employ copper as the material of choice, but at more advanced nodes, cobalt will likely be the best option as linewidths continue to shrink. Tungsten will still be used at the gate contact level.

To enable the use of cobalt, Applied has combined several materials engineering steps – pre-clean, PVD, ALD and CVD – on the Endura® platform. Moreover, Applied has defined an integrated cobalt suite that includes anneal on the Producer® platform, planarization on the Reflexion® LK Prime CMP platform and e-beam inspection on the PROVision™ platform. The process flow is shown in FIGURE 1.

While challenging to integrate, cobalt brings significant benefits to chips and chip making: lower resistance and variability at small dimensions; improved gapfill at very fine dimensions; and improved reliability. The move to cobalt, which is underway at Intel, GlobalFoundries and other semiconductor manufacturing companies, is the first major change in materials used as conductors since copper dual damascene replaced aluminum in 1997. “You don’t see inflections this large very often,” said Jonathan Bakke, global product manager, Metal Deposition Products at Applied Materials. “This is a complete metallization change.”

At IEDM last year, Intel said it would use cobalt for its 10nm logic process for several of the lower metal levels, including a cobalt fill at the trench contacts and cobalt M0 and M1 wiring levels. The result was much-improved resistivity– a 60 percent reduction in line resistance and a 1.5X reduction in contact resistance – and improved reliability.

Today, critical dimensions of contacts and interconnects are about 20 nm, plus or minus a few nanometers depending on the customer and how it’s defined. “As you get smaller – and you typically get about 30% smaller with each node — you’re running out of room for tungsten. Copper is also facing challenges in both gap fill and electromigration,” Bakke said.

As shown in FIGURE 2, cobalt has advantages over copper when dimensions shrink to about 10nm. They are presently at 30 nm. It’s not yet clear when that cross-over point will arrive, but decisions will be based on how much resistivity and electromigration improvement can be gained.

Applied Materials started developing cobalt-based processes in the mid-2000s, and released the Volta CVD Cobalt system in 2013, which was designed to encapsulate copper interconnects in cobalt, which helped improve gap fill and electromigration. “It was shortly thereafter that we started depositing thick CVD cobalt films for metalization. We quickly realized that there’s a lot of challenges with doing this kind of metalization using cobalt because of its unique properties,” Bakke said. Cobalt can be reflowed and recrystallized, which eliminates seams and leads to larger grain sizes, which reduces resistivity. “We started looking at things like interfaces, adhesion and microstructure of the cobalt to make sure that it was an efficient material and it had very low resistance and high yield for in-device manufacturers,” he added. One perfected, it took several years before the processes were fully qualified at customers. “This year is when we start to see proliferation and expect HDM manufacturing of real devices with cobalt,” Bakke said.

Companies Ready Cobalt for MOL, Gate Fill

Thursday, December 21st, 2017

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By Dave Lammers

Cobalt for middle-of-the-line and trench contacts emerged at the International Electron Devices Meeting, as Intel, GlobalFoundries, and Applied Materials discussed how to best take advantage of cobalt’s properties.

For its forthcoming 10nm logic process, Intel Corp. used cobalt for several of the lower metal levels, including a cobalt fill at the trench contacts and cobalt M0 and M1 wiring levels. The result was much-improved resistivity and reliability, compared with the traditional metallization at those levels.

Cobalt was used for the local interconnects of the Intel 10nm process, improving line resistance by 60 percent. (Source: Intel)

Chris Auth, director of logic technology at Intel’s Portland Technology Center, said the contacted line resistance “provides a good indicator of the benefits of cobalt versus tungsten,” with a 60 percent reduction in line resistance and a 1.5X reduction in contact resistance.

While cobalt was used for the local interconnects, the upper 10 metal layers were copper, with a cobalt cap used for layers M2-M5 to provide a 50X improvement in electro-migration. Intel continued to use tungsten for the gate fill.

John Pellerin, a vice president at GlobalFoundries who directs global research and development, said GlobalFoundries decided that for its 7nm logic technology, ramping in mid-2018, it would replace tungsten with cobalt at the trench contact level, which is considered the first level of the middle-of-the-line (MOL).

“We are evaluating it for implementation into the next level of contact above that. Cobalt trench level contacts are process of record (POR) for the 7nm technology,” Pellerin said in an interview at the 2017 IEDM, held Dec. 2-6 in San Francisco.

High performance logic often involves four-fin logic cells to drive the maximum amount of current from the largest transistor width. “You have to get that current out of the transistor. That is where the MOL comes into play. Junction and MOL resistance optimization is key to taking advantage of a four-fin footprint, and it takes a multi-front optimization to take advantage of that equation.

Pellerin said the biggest challenge with tungsten trench contacts is that the CVD process tends to leave a seam void. “We are always fighting seam voids. With cobalt deposition we get an intrinsic resistance improvement, and don’t get seam voids by pushing tungsten down in there,” Pellerin said.

Tighter Metal Pitches

Scotten Jones, president of consultancy IC Knowledge (Boston), said semiconductor vendors will introduce cobalt when it makes sense. Because it is a new material, requiring considerable costs prior to insertion, companies will use it when they need it.

“Global has trench contacts, while Intel uses cobalt at three levels. But the reason is that Intel has a 36nm minimum metal pitch with its 10nm process, while Global is at 40nm with its 7nm process. It is only at the point where the line gets narrow enough that cobalt starts to make sense.”

Applied Cobalt Solutions

As cobalt begins to replace tungsten at the smaller-dimension interconnect layers, Applied Materials is readying process flows and E-beam inspection solutions optimized for cobalt.

Namsung Kim, senior director of engineering management at Applied Materials, said cobalt has a bulk resistivity that is similar to tungsten, but the barrier thickness required for tungsten at leading-edge transistors is swinging the advantage to cobalt as dimensions shrink.

Line resistance probability plot of cobalt versus tungsten at 12nm critical dimensions. (Source: Applied Materials)

“Compared with tungsten, cobalt has a very thin barrier thickness, so you can fill up with more material. At our Maydan Technology Center, we’ve developed a reflow process for cobalt that is unique,” Kim said. The cobalt reflow process uses an annealing step to create larger cobalt grain sizes, reducing the resistance. And because there is no source of fluorine in the cobalt deposition steps, a thin barrier layer can suffice.

At IEDM, Naomi Yoshida, a distinguished member of the technical staff at Applied, presented a paper describing Applied’s research using cobalt to fill a 5nm-logic-generation replacement metal gate (RMG). The fill is deposited above the high-k dielectric and work function metals, and at the 5nm node and beyond there is precious little room for the gap fill metal.

Yoshida said modern transistors use multiple layers of work-function metals to control threshold voltages, with high-performance logic requiring low Vt’s and IoT devices requiring relatively high Vt’s. After the different work function layers are deposited, the fill material is deposited.

At the 5nm node, Applied Materials estimates that the contacted poly pitch (CPP) will shrink to about 42nm, while the gate length (Lg) will be less than 12nm. “There is very limited space for the fill materials, so customers need a more conductive metal in a limited space. That is the major challenge,” Yoshida said in an interview at the IEDM.

Work Function Maintained

Naomi Yoshida: room for gate fill disappearing

The Applied R&D work showed that if the barrier layer for a tungsten fill is reduced too much, to a 2nm or 3nm TiN layer for example, the effective work function (eWF) degrades by as much as 500mV eWF and the total gate conductance suffers. With the CVD process used to deposit a tungsten RMG fill, there was “significant fluorine diffusion” into the work function metal layer in the case of a 2nm TiN barrier.

By contrast, the cobalt fill maintained the NMOS band-edge eWF with the same 2nm TiN barrier.

Gradually, cobalt will be adopted more widely for the contacts, interconnects, and RMG gate fill steps. “It is time to think about how to achieve more conductance in the gate material. Previously, people said there was a negligible contribution from the gate material, but now with the smaller gates at 5nm, gate fill metal makes a huge contribution to resistance, and barrier thickness reduction is important as well,” Yoshida said.

E-beam Inspection

Nicolas Breil: E-beam void inspection useful for cobalt contacts

Applied Materials also has developed an e-beam inspection solution, ProVision, first introduced in mid-2016, and has optimized it for inspecting cobalt voids. Nicolas Breil, a director in the company’s contact module division, said semiconductor R&D organizations are busy developing cobalt contact solutions, optimizing the deposition, CMP, and other steps. “For such a dense and critical level as the contact, it always needs very careful engineering. They key is to get results as fast as possible, but being fast can be very expensive.”

Amir Wachs, business development manager at Applied’s process diagnostics and control business unit in Rehovat, Israel, said the ProVision e-beam inspection system has a resolution of 1nm, at 10,000-20,000 locations per hour, taking a few hundred measurements on each field of view.

“Voids form when there are adhesion issues between the cobalt and TiN. One of the key issues is the correct engineering of the Ti nitride and PVD cobalt and CVD cobalt. To detect embedded voids requires a TEM inspection, but then customers get very limited statistics. There might be a billion contacts per chip, and with conventional TEM you might get to inspect two.”

The ProVision system speeds up the feedback loop between inspection and co-optimization. “Customers can assess the validity of the optimization. With other inspection methods, co-optimization might take five days to three weeks. With this type of analysis, using ProVision, customers can do tests early in the flow and validate their co-optimization within a few hours,” Wachs said.

Logic Densities Advance at IEDM 2017

Monday, December 18th, 2017

By Dave Lammers

The 63rd International Electron Devices Meeting brought an optimistic slant to transistor density scaling. While some critics have declared the death of Moore’s Law, there was little evidence of that — on the density front at least — at the IEDM, held Dec. 2-6 in San Francisco.

And an Intel engineering manager gave a presentation at IEDM that took a somewhat optimistic view of EUV lithography readiness, auguring further patterning improvements, starting with contacts and vias.

GlobalFoundries, which is skipping the 10nm node, presented its 7nm logic technology, expects to move into manufacturing in mid-2018. John Pellerin, vice president of global R&D, said the foundry has worked closely with its two lead customers, AMD and IBM, to define a high-performance-computing 7nm logic technology that achieves a 2.8X improvement of routed logic density compared with its 14nm technology.

Pellerin said the current 7nm process of record (POR) delivers “the right mix of performance, power, and area (PPA),” adding that GlobalFoundries plans to bring in EUV patterning at an undefined later point in the 7+ generation for further improvements.

Contact Over Active Gate

Chris Auth, director of advanced transistor development at Intel Corp., described a 10nm logic technology that sharply increased the transistor density compared with the 14nm generation, partly due to a contact-over-active-gate (COAG) architecture. The 10nm ring oscillator performance was improved by 20 percent compared with the comparable 14nm test vehicle.

Chris Auth, who presented Intel’s 10nm technology paper at IEDM, was surrounded by questioners following the presentation.

Auth said the COAG approach was a key contributor to Intel’s ability to increase its transistor density by 2.7 times over the company’s previous generation, to 100 million transistors per square millimeter of silicon. While the traditional approach puts the contact via over the isolation area, COAG places the contact via directly over the gate. Auth said the approach does require a second etch stop layer and other process complexities, but contributes “a sizable 10 percent reduction in area.” Elimination of the dummy gate for cell boundary isolation, and the use of cobalt at three layers (see related story), also contributed.

While there has been much hand wringing in the industry over the costs involved with multi-level patterning, Auth didn’t appear phased by it. Intel used a self-aligned quad patterning (SAQP) scheme to create fins with a tight pitch. The SAQP approach required two sacrificial layers, with lithography defining the first large pattern and four additional steps to remove the spacers and create the final lines and spaces.

The Intel 10nm fins are 46nm in height.

The SAQP approach starts by exposing a 130nm line, depositing the two spacers, halving the pattern to 68nm, and again to 34nm. “It is a grating and cut process similar to what we showed at 22nm, except it is SAQP instead of SADP,” using patterning to form a grating of fins, and cutting the ends of the fins with a cut mask.

“There were no additional lithography steps required. The result was fins that are tighter, straighter, and taller, with better drive current and matching” than Intel’s 14nm-generation fins, he said. Intel continued to use self-aligned double patterning (SADP) for M 2-5, and for gate patterning.

GlobalFoundries — which has been in production for 18 months with the 14nm process used by AMD, IBM, and others — plans to ramp its 7nm logic generation starting in mid-2018. The 7nm high-density SRAM cell measures .0269 um2, slightly smaller than TSMC’s published 7nm cell, while Intel reported a .0312 um2 cell size for its 10nm process.

Intel argues that the traditional way of calculating density improvements needs to be replaced with a metric that combines NAND and scan flip-flop densities. (Source: Intel)

GlobalFoundries chief technology officer Gary Patton said, “all of us are in the same zip code” when it comes to SRAM density. What is increasingly important is how the standard cells are designed to minimize the track height and thereby deliver the best logic cell technology to designers, Patton said.

EUV Availability Needs Improvements

Britt Turkot, senior principal engineer at Intel, discussed the readiness of EUV lithography at an IEDM session, giving a cautiously bullish report. With any multi-patterning solution for leading-edge silicon, including etch and CMP steps, placement error is the biggest challenge. With quad patterning, Turkot said multiple masks are involved, creating “compounded alignment errors.”

EUV has its own challenges, including significant secondary ions from the EUV photons. The key challenge for much of the decade, source power, seems to be partially resolved. “We are confident that the 250 Watts of source power needed for volume manufacturing will be ready once the field tools are upgraded,” she said.

Pellicles may be another challenge, with ASML expected to have a polysilicon-based pellicle ready in time for EUV production. However, she said a polysilicon membrane “does give quite a hit to the transmissivity” of the mask. “The transmissivity impact is quite significant,” she acknowledged during the Q&A period following her talk.

Intel has succeeded in repairing some mask defects, Turkot said, and implements pattern shifting so that other defects do not impinge on the patterned wafer.

Asked by a member of the audience about EUV availability or up-time, Turkot said “one day, availability can be great,” and less than good on other days, with “long unscheduled downs.” Intel is predicting 88 percent availability next year, she said in response to a question.

Pellicle Needed for Wiring Layers

Scotten Jones, president of semiconductor cost consultancy IC Knowledge (Boston), said companies may be able to get by without a pellicle for EUV patterning of contacts and via layers late next year. However, a pellicle will be needed for patterning the lower-level wiring layers, absorbing 10-15 percent of the photons and impacting EUV patterning throughput accordingly.

“Companies can do the contacts and vias without a pellicle, but doing the metal layers will required a pellicle and that means that a ton of work still needs to be done. And then at 5nm, the dose you need for the resist goes up dramatically,” Jones said, adding that while it will take some time for ASML to roll out the 250 W source, “they should be able to do it.”

GlobalFoundries will take possession of its second EUV scanner in December 2017, while Intel is believed to own four EUV systems.

Pellerin said GlobalFoundries defined the ground rules for its 7nm process so that the foundry can do a phased implementation of EUV without causing its customers “design discontinuity, bringing a benefit to design costs.”

John Pellerin, v.p. of R&D, said GlobalFoundries plans a phased implementation of EUV without “design discontinuity.”

The foundry will first do the hole levels and then move into the tight-pitch metal levels as mask defectivity improves. “The mask ecosystem needs to evolve,” Pellerin said.

Cost-per-Function on Track

In a keynote speech at IEDM, Lisa Su, the CEO of Advanced Micro Devices, said over the last 10 years the semiconductor industry has succeeded in doubling transistor density every 2-2.4 years. But she said the performance gains have been much smaller. “We are making progress, but it is taking a tremendous amount of work,” said Su, who received a best paper award at the IEDM 25 years earlier.

About 40 percent of the CPU performance improvement now comes from pure process technology, Su said, while the remainder comes from better microarchitectures, power management, and integration of system components such as an on-chip memory controller. While instructions per cycle are increasing at a 7 percent annual clip, Su said “the tricks have run out.”

Overall, the leading semiconductor companies seem to continue to make progress on transistor density. And costs per transistor may also be on track. Kaizad Mistry, co-director of logic technology development at Intel, contends that with its Intel’s 10nm process Intel’s per-transistor costs are actually better than the historical  curve.

Jones said the IC Knowledge cost analysis of TSMC’s processes indicates TSMC also is hewing to historical improvements on the per-transistor cost front. However, the foundries are catching up to Intel.

Intel Cadence Lagging

“What really strikes me is that Intel brought out its 45nm process in 2007, 32nm in 2009, and 22nm in 2011, but then it took three years to do 14nm. We are about to be in the year 2018, and Intel still doesn’t have its 10nm process done. It is a very nice process, but it is not out yet, and TSMC’s 7nm process is ramping right now. By the time Intel gets to 7nm, the foundries may be at 3nm. GlobalFoundries skipped a generation but is ramping its 7nm next year. All will have processes competitive to Intel at the same time, or even earlier,” Jones said.

While foundries such as GlobalFoundries, Samsung, and TSMC may be able to quickly offer advanced logic platforms, the wider semiconductor industry faces design cost challenges, Jones said. “Yes, the cost-per-transistor is going down, and that’s nice, but the cost of a design with finFETs is in the 100-million-dollar range. Intel can do it, but many smaller companies can’t afford to design with FinFETs.”

That is why both GlobalFoundries and Samsung are offering FD-SOI based platforms that use planar transistors, reducing design costs.

“The Internet of Things market is going to be nine million things, at relatively low volumes. IoT companies are finding it hard to justify the cost of a FinFET design, but with the cheaper design costs, SOI gives them an economical path,” Jones said.

Embedded FPGAs Offer SoC Flexibility

Wednesday, October 4th, 2017

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By Dave Lammers, Contributing Editor

It was back in 1985 that Ross Freeman invented the FPGA, gaining a fundamental patent (#4,870,302) that promised engineers the ability to use “open gates” that could be “programmed to add new functionality, adapt to changing standards or specifications, and make last-minute design changes.”

Freeman, a co-founder of Xilinx, died in 1989, too soon to see the emerging development of embedded field programmable logic arrays (eFPGAs). The IP cores offer system-on-chip (SoC) designers an ability to create hardware accelerators and to support changing algorithms. Proponents claim the approach provides advantages to artificial intelligence (AI) processors, automotive ICs, and the SoCs used in data centers, software-defined networks, 5G wireless, encryption, and other emerging applications.

With mask costs escalating rapidly, eFPGAs offer a way to customize SoCs without spinning new silicon. While eFPGAs cannot compete with custom silicon in terms of die area, the flexibility, speed, and power consumption are proving attractive.

Semico Research analyst Rich Wawrzyniak, who tracks the SoC market, said he considers eFPGAs to be “a very profound development in the industry, a capability that is going to get used in lots of places that we haven’t even imagined yet.”

While Altera, now owned by Intel, and Xilinx, have not ventured publicly into the embedded space, Wawrzyniak noted that a lively bunch of competitors are moving to offer eFPGA intellectual property (IP) cores.

Multiple competitors enter eFPGA field

Achronix Semiconductor (Santa Clara, Calif.) has branched out from its early base in stand-alone FPGAs, using Intel’s 22nm process, to an IP model. It is emphasizing its embeddable Speedcore eFPGAs that can be added to SoCs using TSMC’s 16FF foundry process. 7nm IP cores are under development.

Efinix Inc. (Santa Clara recently rolled out its Efinix Programmable Accelerator (EPA) technology.

Efinix (efinixinc.com) claims that its programmable arrays can either compete with established stand-alone FPGAs on performance, but at half the power, or can be added as IP cores to SoCs. The Efinix Programmable Accelerator technology can provide a look up table (LUT)-based logic cell or a routing switch, among other functions, the company said.

Efinix was founded by several managers with engineering experience at Altera Corp. at various times in their careers — Sammy Cheung, Tony Ngai, Jay Schleicher, and Kar Keng Chua — and has financial backing from two Malaysia-based investment funds.

Flex Logix Technologies, (Mountain View, Calif.) (www.flex-logix.com) an eFPGA startup founded in 2014, recently gained formal admittance to TSMC’s IP Alliance program. It supports a wide array of foundry processes, providing embedded FPGA IP and software tools for TSMC’s 16FFC/FF+, 28HPM/HPC, and 40ULP/LP.

Flex Logix supports several process generations at foundry TSMC. The 16nm test chip is being evaluated. (Source: Flex Logix)

QuickLogic adds SMIC to foundry roster

Menta  (http://www.menta-efpga.com/) is another competitor in the FPGA space. Based in Montpellier, France, Menta is a privately held company founded a decade ago that offers programmable logic IP targeted to both GLOBALFOUNDRIES (14LPP) and TSMC (28HPM and 28HPC+) processes.

Menta offers either pre-configured IP blocks, or custom IPs for SoCs or ASICs. The French company supports its IP with a tool set, called Origami, which generates a bitstream from RTL, including synthesis. Menta said it has fielded four generations of products that in use by customers now “for meeting the sometimes conflicting requirements of changing standards, security updates and shrinking time-to-market windows of mobile and consumer products, IoT devices, networking and automotive ICs.”

QuickLogic, a Silicon Valley stalwart founded in 1988, also is expanding its eFPGA capability. In mid-September, QuickLogic (Sunnyvale, Calif.) (quicklogic.com) announced that its eFPGA IP can now be used with the 40nm low-leakage process at Shanghai-based Semiconductor Manufacturing International Corp. (SMIC). QuickLogic also offers its eFPGA technology on several of the mature GLOBALFOUNDRIES processes, and is participating in the foundry’s 22FDX IP program.

Wawrzyniak, who tracks the SoC market for Semico Research, said an important market is artificial intelligence, using eFPGA gates to add a flexible convolutional neural network (CNN) capability. Indeed, Flex Logix said one of its earliest adopters is an AI research group at Harvard University that is developing a programmable AI processor.

A seminal capability

The U.S. government’s Defense Advanced Projects Agency (DARPA) also has supported Flex Logix by taking a license, endorsing an eFPGA capability for defense and aerospace ICs used by the U.S. military.

With security being such a concern for the Internet of Things edge devices market, Wawrzyniak said eFPGA gates could be used to secure IoT devices against hackers, a potentially large market.

“The major use is in apps and instances where people need some programmability. This is a seminal, basic capability. How many times have you heard someone say, ‘I wish I could put a little bit of programmability into my SoC.’ People are going to take this and run with it in ways we can’t imagine,” he said.

Bob Wheeler, networking analyst at The Linley Group, said the intellectual property (IP) model makes sense for startups. Achronix, during the dozen years it developed and then fielded its standalone FPGAs, “was on a very ambitious road, competing with Altera and Xilinx. Achronix went down the road of developing parts, and that is a tall order.”

While the cost of running an IP company is less than fielding stand-alone parts, Wheeler said “People don’t appreciate the cost of developing the software tools, to program the FPGA and configure the IP.” The compiler, in particular, is a key challenge facing any FPGA vendor.

Wheeler said Achronix https://www.achronix.com/ , has gained credibility for its tools, including its compiler, after fielding its high-performance discrete FPGAs in 2016, made on Intel’s 22nm process.

Achronix offers Speedcore eFPGAs, based on the same architecture as its standalone FPGAs. (Source: Achronix Semiconductor)

And Wheeler cautioned that IP companies face the business challenge of getting a fair return on their development efforts, especially for low-cost IoT solutions where companies maintain tight budgets for the IP that they license.

Achronix earlier this year announced that its 2017 revenues will exceed $100 million, based on a seven-times increase in sales of its Speedster 22i FPGA family, as well as licensing of its Speedcore embedded IP products, targeted to TSMC’s leading-edge 16 nm node, with 7nm process technology for design starts beginning in the second half of this year. Achronix revenues “began to significantly ramp in 2016 and the company reached profitability in Q1 2017,” said CEO Robert Blake.

Escalating mask costs

Flex Logix CEO Geoff Tate

Geoff Tate, now the CEO of Flex Logix Technologies, earlier headed up Rambus for 15 years. Tate said Flex Logix (www.flex-logix.com uses a hierarchical interconnect, developed by co-founder Cheng Wang and others while he earned his doctorate at UCLA. The innovative interconnect approach garnered the Lewis Outstanding Paper award for Wang and three co-authors at the 2014 International Solid-State Circuits Conference (ISSCC), and attracted attention from venture capitalists at Lux Ventures and Eclipse Ventures.

Tate said one of those VCs came to him one day and asked for an evaluation of Wang & Co.’s technology. Tate met with Wang, a native of Shanghai, and found him to be anything but a prima donna with a great idea. “He seemed very motivated, not just an R&D guy.”

While most FPGAs use a mesh interconnect in an X-Y grid of wires, Wang had come up with a hierarchical interconnect that provided high density without sacrificing performance, and proved its potential with prototype chips at UCLA.

“Chips need to be more flexible and adaptable. FPGAs give you another level of programmability,” Tate noted.

Meanwhile, potential customers in networking, data centers, and other markets were looking for ways to make their designs more flexible. An embedded FPGA block could help customers adapt a design to new wireless and networking protocols. Since mask costs were escalating, to an estimated $5 million for 16nm designs and more than double that for 7nm SoCs, customers had another reason to risk working with a startup.

TSMC has supported Flex Logix, in mid-September awarding the company the TSMC Open Innovation Platform’s Partner of the Year Award for 2017 in the category of New IP.

“Our lead customer has a working chip, with embedded FPGA on it. They are in the process of debugging rest of their chip. Overall, we are still in the early stages of market development,” Tate said, explaining that semiconductor companies are understandably risk-averse when it comes to their IP choices.

Asked about the status of its 16nm test chip, Tate said “the silicon is out of the fab. The next step is packaging, then evaluation board assembly.  We should be doing validation testing starting in late September.”

Potential customers are in the process of sending engineers to Flex Logix to look at metrics of the largest 16nm arrays, such as IR drop, vest vectors, switching simulations, and the like. “They making sure we are testing in a thorough fashion. If we screw them over, they’ll tell everybody, so we have got to get it right the first time,” Tate said.

GlobalFoundries Turns the Corner

Friday, September 29th, 2017

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By David Lammers

Claiming that GlobalFoundries “is a different company than two years ago,” executives said the foundry’s strategies are starting to pay off in emerging markets such as 5G wireless, automotive, and high-performance processors.

CEO Sanjay Jha, speaking at the GlobalFoundries Technology Conference, held in Santa Clara, Calif. recently, said that to succeed in the foundry segment requires that customers “have confidence that they are going to get their wafers at the right time and with the right quality. That has taken time, but we are there.”

CEO Sanjay Jha: “differentiated” processes are key.

Innovation is another essential requirement for success, Jha said, arguing that R&D dollars must include spending on “differentiated” approaches. Alain Mutricy, senior vice president of product development, acknowledged that only recently have customers turned to GlobalFoundries as more than just a second-source to TSMC. For the first few years, “most companies used us to keep (wafer) prices down,” he said, while noting GlobalFoundries bears some responsibility for that by not investing nearly enough, early on, in IP libraries and EDA tool development.

Founded in March 2009 as a spinout of the manufacturing arm of Advanced Micro Devices, Global Foundries’ Abu Dhabi-based owner soon acquired Singapore’s Chartered Semiconductor in January 2010, and further expanded through the July 2015 acquisition of IBM Microelectronics. It is now engaged in building what Jha said will be the largest wafer fab in China, in Chengdu, capable of processing a million wafers a year. The Chengdu fab, operated by GlobalFoundries but with investments from the local government, will begin with 180nm and 130nm products now fabbed in Singapore, and then add 22FDX IC production to meet demand from Chinese customers.

While the road to profitability has been a hard one, Len Jelinek, chief technology analyst at HIS Markit, said GlobalFoundries is now “cash flow positive,” with the flagship Malta, N.Y. fab “essentially full” at an estimated 40,000 wafer starts per month. That is a big turnaround from four years ago, he said.

Malta fab’s capacity doubling

Nathan Brookwood, longtime microprocessor watcher at Insight64, said while AMD no longer has an ownership stake in GlobalFoundries, it does have wafer supply agreements with the foundry. The fact that AMD’s Zen-based microprocessors and newest graphics chips are all made on the 14nm Finfet process at Fab 8 “means that AMD is now actually using the wafer supply it is committed to taking. That helps both companies.”

Andrea Lati, director of market research at VLSI Research, said while TSMC “is clearly a very well-run company that is marching ahead,” GlobalFoundries also is making progress. Again, AMD’s success is a large part of that, Lati said, noting that “AMD is definitely doing very well for the last couple of years, and has good prospects, along with Nvidia, in the graphics side.”

In a telephone interview, Tom Caulfield, senior vice president and general manager of the GlobalFoundries’ Malta fab, said “we are continually adding capacity in 14nm as we get a window on to the demand from our customers. In 2016 and 2017 we made additional investments.”

While not putting a specific number on Malta’s capacity, Caulfield said that if the beginning of 2016 is taken as a baseline, by the end of 2018 the wafer capacity at Malta’s Fab 8 will have more than doubled.

“AMD refreshed its entire portfolio with 14nm, exclusively made here at Malta, and we are chasing more demand than we planned on. AMD’s success is a proxy for our success. We are in this hand in hand,” Caulfield said.

Asked if a new fab was being considered at Malta, Caulfield said “At some point we will need more brick and mortar. Eventually we will run out of space, but we still have some time in front of us.

FDX in the wings

Scotten Jones, who runs a semiconductor cost modeling consultancy, IC Knowledge LLC, said competition is also heating up at the 28nm node, once controlled almost exclusively by TSMC. As GlobalFoundries, Samsung — and more recently, SMIC and UMC — have ironed out their own 28nm processes, the profitability of TSMC’s 28nm business has tightened, Jones said.

The competitive spotlight is now on the 22FDX SOI-based process developed by GlobalFoundries, buttressed by an embedded 22nm eMRAM capability developed along with MRAM pioneer Everspin Technologies.

Gary Patton, chief technology officer at GlobalFoundries, said the SOI-based 22nm node supports forward biasing, while the 12nm FDX technology will support both forward and back-biasing, to either boost performance or conserve power. Patton said the 12FDX process will provide 26 percent more performance and 47 percent less power consumption than the 22FDX process, with prototypes expected in the second half of 2018 and volume production beginning in 2019.

CTO Gary Patton: Technology development boosted by IBM engineers.

Patton said “maybe we haven’t done enough” to explain the differences between the 14nm FinFet technology and the SOI-based FDX technologies. The FinFET transistors have enough drive current to drive signals across fairly large die sizes, while the FDX technology is best suited to die sizes of 150 sq. mm and smaller, he said.

Jones said his cost analysis shows that the design costs for the planar FDX chips are much less expensive than for FinFETs, which require “some fairly expensive EDA tools.” That combines with a much smaller mask count, due to multi-patterning.

Patton said the 22FDX designs require 40 percent fewer masks that comparable 14nm FinFET-based designs. “With the SOI technology customers have the option of using body biasing, which has been used in the industry for the past three or four years. We can operate at .4 Volts, and customers are putting RF on the same chip as digital.”

Asked if he thought the FDX processes would gain traction in the marketplace, Jones answered in the affirmative. “I think it will find its place. It is still early. These kinds of new technologies take time to get established,” Jones said.

Jha said two companies have developed products based on 22FDX, Dream Chip Technologies, an advanced driver assistance system (ADAS) supplier, which last February said it has completed a computer vision SoC based on the 22FDX process, and Ineda Systems, which seeks to integrate RF and digital capabilities on its 22FDX-based processors, targeted at the Internet of Things market.

Mutricy said 70 companies purchased the 22FDX foundation IP provided by Invecas for the 22FDX process, with 18 tapeouts on track for production next year.

Patton said the addition of 500 technologists from IBM’s microelectronics division has aided the technology development operation. “GlobalFoundries is absolutely a different company than it was just two years ago,” Patton said at the GTC event.

Silicon Photonics Technology Developments

Thursday, April 6th, 2017

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By Ed Korczynski, Sr. Technical Editor

With rapidly increasing use of “Cloud” client:server computing there is motivation to find cost-savings in the Cloud hardware, which leads to R&D of improved photonics chips. Silicon photonics chips could reduce hardware costs compared to existing solutions based on indium-phosphide (InP) compound semiconductors, but only with improved devices and integration schemes. Now MIT researchers working within the US AIM Photonics program have shown important new silicon photonics properties. Meanwhile, GlobalFoundries has found a way to allow for automated passive alignment of optical fibers to silicon chips, and makes chips on 300mm silicon wafers for improved performance at lower cost.

In a recent issue of Nature Photonics, MIT researchers present “Electric field-induced second-order nonlinear optical effects in silicon waveguides.” They also report prototypes of two different silicon devices that exploit those nonlinearities: a modulator, which encodes data onto an optical beam, and a frequency doubler, a component vital to the development of lasers that can be precisely tuned to a range of different frequencies.

This work happened within the American Institute for Manufacturing Integrated Photonics (AIM Photonics) program, which brought government, industry, and academia together in R&D of photonics to better position the U.S. relative to global competition. Federal funding of $110 million was combined with some $500 million from AIM Photonics’ consortium of state and local governments, manufacturing firms, universities, community colleges, and nonprofit organizations across the country. Michael Watts, an associate professor of electrical engineering and computer science at MIT, has led the technological innovation in silicon photonics.

“Now you can build a phase modulator that is not dependent on the free-carrier effect in silicon,” says Michael Watts in an online interview. “The benefit there is that the free-carrier effect in silicon always has a phase and amplitude coupling. So whenever you change the carrier concentration, you’re changing both the phase and the amplitude of the wave that’s passing through it. With second-order nonlinearity, you break that coupling, so you can have a pure phase modulator. That’s important for a lot of applications.”

The first author on the new paper is Erman Timurdogan, who completed his PhD at MIT last year and is now at the silicon-photonics company Analog Photonics. The frequency doubler uses regions of p- and n-doped silicon arranged in regularly spaced bands perpendicular to an undoped silicon waveguide. The space between bands is tuned to a specific wavelength of light, such that a voltage across them doubles the frequency of the optical signal passing. Frequency doublers can be used as precise on-chip optical clocks and amplifiers, and as terahertz radiation sources for security applications.

GlobalFoundries’ Packaging Prowess

At the start of the AIM Photonics program in 2015, MIT researchers had demonstrated light detectors built from efficient ring resonators that they could reduce the energy cost of transmitting a bit of information down to about a picojoule, or one-tenth of what all-electronic chips require. Jagdeep Shah, a researcher at the U.S. Department of Defense’s Institute for Defense Analyses who initiated the program that sponsored the work said, “I think that the GlobalFoundries process was an industry-standard 45-nanometer design-rule process.”

The Figure shows that researchers at IBM developed an automated method to assemble twelve optical fibers to a
silicon chip while the fibers are dark, and GlobalFoundries chips can now be paired with this assembly technology. Because the micron-scale fibers must be aligned with nanometer precision, default industry standard has been to expensively align actively lit fibers. Leveraging the company’s work for Micro-Electro-Mechanical Sensors (MEMS) customers, GlobalFoundries uses an automated pick-and-place tool to push ribbons of multiple fibers into MEMS groves for the alignment. Ted Letavic, Global Foundries’ senior fellow, said the edge coupling process was in production for a telecommunications application. Silicon photonics may find first applications for very high bandwidth, mid- to long-distance transmission (30 meters to 80 kilometers), where spectral efficiency is the key driver according to Letavic.

FIGURE: GlobalFoundries chips can be combined with IBM’s automated method to assemble 12 optical fibers to a silicon photonics chip. (Source: IBM, Tymon Barwicz et al.)

GobalFoundries has now transferred its monolithic process from 200mm to 300mm-diameter silicon wafers, to achieve both cost-reduction and improved device performance. The 300mm fab lines feature higher-N.A. immersion lithography tools which provide better overlay and line width roughness (LWR). Because the of the extreme sensitivity of optical coupling to the physical geometry of light-guides, improving the patterning fidelity by nanometers can reduce transmission losses by 3X.

—E.K.

Innovations at 7nm to Keep Moore’s Law Alive

Thursday, January 19th, 2017

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By Dave Lammers, Contributing Editor

Despite fears that Moore’s Law improvements are imperiled, the innovations set to come in at the 7nm node this year and next may disprove the naysayers. EUV lithography is likely to gain a toehold at the 7nm node, competing with multi-patterning and, if all goes well, shortening manufacturing cycles. Cobalt may replace tungsten in an effort to reduce resistance-induced delays at the contacts, a major challenge with finFET transistors, experts said.

While the industry did see a slowdown in Moore’s Law cost reductions when double patterning became necessary several years ago, Scotten Jones, who runs a semiconductor consultancy focused on cost analysis, said Intel and the leading foundries are back on track in terms of node-to-node cost improvements.

Speaking at the recent SEMI Industry Strategy Symposium (ISS), Jones said his cost modeling backs up claims made by Intel, GlobalFoundries, and others that their leading-edge processes deliver on die costs. Cost improvements stalled at TSMC for the16nm node due to multi-patterning, Jones said. “That pause at TSMC fooled a lot of people. The reality now may surprise those people who said Moore’s Law was dead. I don’t believe that, and many technologists don’t believe that either,” he said.

As Intel has adopted a roughly 2.5-year cadence for its more-aggressive node scaling, Jones said “the foundries are now neck and neck with Intel on density.” Intel has reached best-ever yield levels with its finFET-based process nodes, and the foundries also report reaching similar yield levels for their FinFET processes. “It is hard, working up the learning curve, but these companies have shown we can get there,” he said.

IC Knowledge cost models show the chip industry is succeeding in scaling density and costs. (Source: Scotten Jones presentation at 2017 SEMI ISS)

TSMC, spurred by its contract with Apple to supply the main iPhone processors, is expected to be first to ship its 7nm products late this year, though its design rules (contacted poly pitch and minimum metal pitch) are somewhat close to Intel’s 10nm node.

While TSMC and GlobalFoundries are expected to start 7nm production using double and quadruple patterning, they may bring in EUV lithography later. TSMC has said publicly it plans to exercise EUV in parallel with 193i manufacturing for the 7nm node. Samsung has put its stake in the ground to use EUV rather than quadruple patterning in 2018 for critical layers of its 7nm process. Jones, president of IC Knowledge LLC, said Intel will have the most aggressive CPP and MPP pitches for its 7nm technology, and is likely to use EUV in 2019-2020 to push its metal pitches to the minimum possible with EUV scanners.

EUV progress at imec

In an interview at the 62nd International Electron Devices Meeting (IEDM) in San Francisco in early December, An Steegen, the senior vice president of process technology at Imec (Leuven, Belgium), said Imec researchers are using an ASML NXE 3300B scanner with 0.3 NA optics and an 80-Watt power supply to pattern about 50 wafers per hour.

“The stability on the tool, the up time, has improved quite a lot, to 55 percent. In the best weeks we go well above 70 percent. That is where we are at today. The next step is a 125-Watt power supply, which should start rolling out in the field, and then 250 Watts.”

Steegen said progress is being made in metal-containing EUV resists, and in development of pellicles “which can withstand hydrogen in the chamber.”

If those challenges can be met, EUV would enable single patterning for vias and several metal layers in the middle of the line (MOL), using cut masks to print the metal line ends. “For six or seven thin wires and vias, at the full (7nm node) 32nm pitch, you can do it with a single exposure by going to EUV. The capability is there,” Steegen said.

TSMC’s 7nm development manager, S.Y. Wu, speaking at IEDM, said quadruple patterning and etch (4P4E) will be required for critical layers until EUV reaches sufficient maturity. “EUV is under development (at TSMC), and we will use 7nm as the test vehicle.”

Huiming Bu was peppered with questions following a presentation of the IBM Alliance 7nm technology at IEDM.

Huiming Bu, who presented the IBM Alliance 7nm paper at IEDM, said “EUV delivers significant depth of field (DoF) improvement” compared with the self-aligned quadruple (SAQP) required for the metal lines with immersion scanners.

A main advantage for EUV compared with multi-patterning is that designs would spend fewer days in the fabs. Speaking at ISS, Gary Patton, the chief technology officer at GlobalFoundries, said EUV could result in 30-day reductions in fab cycle times, compared with multiple patterning with 193nm immersion scanners, based on 1.5 days of cycle time per mask layer.

Moreover, EUV patterns would produce less variation in electrical performance and enable tighter process parameters, Patton said.

Since designers have become accustomed to using several colors to identify multi-patterning layers for the 14nm node, the use of double and quadruple patterning at the 7nm node would not present extraordinary design challenges. Moving from multi-patterning to EUV will be largely transparent to design teams as foundries move from multi-patterning to EUV for critical layers.

Interconnect resistance challenges

As interconnects scale and become more narrow, signals can slow down as electrons get caught up in the metal grain boundaries. Jones estimates that as much as 85 percent of parasitic capacitance is in the contacts.

For the main interconnects, nearly two decades ago, the industry began a switch from aluminum to copper. Tungsten has been used for the contacts, vias, and other metal lines near the transistor, partly out of concerns that copper atoms would “poison” the nearby transistors.

Tungsten worked well, partly because the bi-level liner – tantalum nitride at the interface with the inter-level dielectric (ILD) and tantalum at the metal lines – was successful at protecting against electromigration. The TaN-Ta liner is needed because the fluorine-based CVD processes can attack the silicon. For tungsten contacts, Ti serves to getter oxygen, and TiN – which has high resistance — serves as an oxygen and fluorine barrier.

However, as contacts and MOL lines shrunk, the thickness of the liner began to equal the tungsten metal thicknesses.

Dan Edelstein, an IBM fellow who led development of IBM’s industry-leading copper interconnect process, said a “pinch point” has developed for FinFETs at the point where contacts meet the middle-of-the-line (MOL) interconnects.

“With cobalt, there is no fluorine in the deposition process. There is a little bit of barrier, which can be either electroplated or deposited by CVD, and which can be polished by CMP. Cobalt is fairly inert; it is a known fab-friendly metal,” Edelstein said, due to its longstanding use as a silicide material.

As the industry evaluated cobalt, Edelstein said researchers have found that cobalt “doesn’t present a risk to the device. People have been dropping it in, and while there are still some bugs that need to be worked out, it is not that hard to do. And it gives a big change in performance,” he said.

Annealing advantages to Cobalt

Contacts are a “pinch point” and the industry may switch to cobalt (Source: Applied Materials)

An Applied Materials senior director, Mike Chudzik, writing on the company’s blog, said the annealing step during contact formation also favors cobalt: “It’s not just the deposition step for the bulk fill involved – there is annealing as well. Co has a higher thermal budget making it possible to anneal, which provides a superior, less granular fill with no seams and thus lowers overall resistance and improves yield,” Chudzik explained.

Increasing the volume of material in the contact and getting more current through is critical at the 7nm node. “Pretty much every chipmaker is working aggressively to alleviate this issue. They understand if it’s not resolved then it won’t matter what else is done with the device to try and boost performance,” Chudzik said.

Prof. Koike strikes again

Innovations underway at a Japanese university aim to provide a liner between the cobalt contact fill material and the adjacent materials. At a Sunday short course preceding the IEDM, Reza Arghavani of Lam Research said that by creating an alloy of cobalt and approximately 10 percent titanium, “magical things happen” at the interfaces for the contact, M0 and M1 layers.

The idea for adding titanium arose from Prof. Junichi Koike at Tohoku University, the materials scientist who earlier developed a manganese-copper solution for improved copper interconnects. For contacts and MOL, the Co-Ti liner prevents diffusion into the spacer oxide, Arghavani said. “There is no (resistance) penalty for the liner, and it is thermally stable, up to 400 to 500 degrees C. It is a very promising material, and we are working on it. W (tungsten) is being pushed as far as it can go, but cobalt is being actively pursued,” he said.

Stressor changes ahead

Presentations at the 2016 IEDM by the IBM Alliance (IBM, GlobalFoundries, and Samsung) described the use of a stress relaxed buffer (SRB) layer to induce stress, but that technique requires solutions for the defects introduced in the silicon layer above it. As a result of that learning process, SRB stress techniques may not come into the industry until the 5 nm node, or a second-generation 7nm node.

Technology analyst Dick James, based in Ottawa, said over the past decade companies have pushed silicon-germanium stressors for the PFET transistors about as far as practical.

“The stress mechanisms have changed since Intel started using SiGe at the 90nm node. Now, companies are a bit mysterious, and nobody is saying what they are doing. They can’t do tensile nitride anymore at the NFET; there is precious little room to put linear stress into the channel,” he said.

The SRB technique, James said, is “viable, but it depends on controlling the defects.” He noted that Samsung researchers presented work on defects at the IEDM in December. “That was clearly a research paper, and adding an SRB in production volumes is different than doing it in an R&D lab.”

James noted that scaling by itself helps maintain stress levels, even as the space for the stressor atoms becomes smaller. “If companies shorten the gate length and keep the same stress as before, the stress per nanometer at least maintains itself.”

Huiming Bu, the IBM researcher, was optimistic, saying that the IBM Alliance work succeeded at adding both compressive and tensile strain. The SRB/SSRW approach used by the IBM Alliance was “able to preserve a majority – 75 percent – of the stress on the substrate.”

Jones, the IC Knowledge analyst, said another area of intense interest in research is high-mobility channels, including the use of SiGe channel materials in the PMOS FinFETS.

He also noted that for the NMOS finFETs, “introducing tensile stress in fins is very challenging, with lots of integration issues.” Jones said using an SRB layer is a promising path, but added: “My point here is: Will it be implemented at 7 nm? My guess is no.”

Putting it in a package

Steegen said innovation is increasingly being done by the system vendors, as they figure out how to combine different ICs in new types of packages that improve overall performance.

System companies, faced with rising costs for leading-edge silicon, are figuring out “how to add functionality, by using packaging, SOC partitioning and then putting them together in the package to deliver the logic, cache, and IOs with the right tradeoffs,” she said.

Mentor Graphics Joins GLOBALFOUNDRIES FDXcelerator Partner Program

Thursday, December 22nd, 2016

Mentor Graphics Corp. (NASDAQ: MENT) today announced that it has joined GLOBALFOUNDRIES’ FDXcelerator Partner Program. FDXcelerator program partners support customers of GLOBALFOUNDRIES FDX™ technologies by providing a variety of design solutions, including approved design methodology, IP development expertise, hardware/software system integration expertise, and other critical software, services, and support. They participate in FDXcelerator Partner Program events, and receive early access to the GLOBALFOUNDRIES FDX roadmap and associated technology offerings.

“Mentor Graphics is proud to have expanded our long-term relationship with GLOBALFOUNDRIES to include the FDXcelerator Partner Program,” said Joe Sawicki, vice-president and general manager of the Design-to-Silicon division at Mentor Graphics. “We look forward to delivering an enhanced set of solutions to mutual customers in support of GLOBALFOUNDRIES FDX offerings that will enable the development of high quality low-power designs based upon FD-SOI technology.”

Mentor Graphics offerings participating in the FDXcelerator program include:

  • Multiple design implementation solutions from Digital IC Design, including the Oasys-RTL™ floorplanning and synthesis platform and Nitro-SoC™ next-generation place and route platform.
  • The Calibre® platform, including the Calibre DFM tool suite, the most comprehensive set of IC design verification tools in the EDA industry. Calibre tools will be designated as the sign-off tools for FDX across all GLOBALFOUNDRIES design creation flows.
  • The Analog FastSPICE (AFS)™ Platform, the fastest, most accurate, and highest capacity simulation for nanometer-scale circuits, and the Eldo® Platform, the most advanced circuit verification for analog-centric circuits. Collaboration with GLOBALFOUNDRIES includes device and circuit level certification for 22FDX, and support of reference flows for 22FDX.
  • The Tessent® product suite of comprehensive silicon test and yield analysis solutions includes a full design for test reference flow for 22FDX designs, and provides the industry’s highest test quality, lowest test cost, and fastest time to root cause of test failures.

“We are very pleased that Mentor Graphics has joined our FDXcelerator Partner Program,” said Alain Mutricy, senior vice president of product management at GLOBALFOUNDRIES. “The combination of Mentor’s EDA offerings and our FDX technologies provide customers with the solutions that will enable success in delivering products for today’s highly competitive IC markets.”

MRAM Takes Center Stage at IEDM 2016

Monday, December 12th, 2016

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By Dave Lammers, Contributing Editor

The IEDM 2016 conference, held in early December in San Francisco, was somewhat of a coming-out party for magneto-resistive memory (MRAM). The MRAM presentations at IEDM were complemented by a special MRAM-focused poster session – organized by the IEEE Magnetics Society in cooperation with the IEEE Electron Devices Society (EDS) – with 33 posters and a lively crowd.

And in the opening keynote speech of the 62nd International Electron Devices Meeting, Seok-hee Lee, executive vice president at SK Hynix (Seoul), set the stage by saying that the race is on between DRAM and emerging memories such as MRAM. “Originally, people thought that DRAM scaling would stop. Then engineers in the DRAM and NAND worlds worked hard and pushed out the end further in the future,” he said.

While cautioning that MRAM bit cells are larger than in DRAM and thus more more costly, Lee said MRAM has “very strong potential in embedded memory.”

SK Hynix is not the only company with a full-blown MRAM development effort underway. Samsung, which earlier bought MRAM startup Grandis and which has a materials-related research relationship with IBM, attracted a standing-room-only crowd to its MRAM paper at IEDM. TSMC is working with TDK on its program, and Sony is using 300mm wafers to build high-performance MRAMs for startup Avalanche Technology.

And one knowledgeable source said “the biggest processor company also has purchased a lot of equipment” for its MRAM development effort.

Dave Eggleston, vice president of emerging memory at GlobalFoundries, said he believes GlobalFoundries is the furthest along on the MRAM optimization curve, partly due to its technology and manufacturing partnership with Everspin Technologies (Chandler, Ariz.). Everspin has been working on MRAM for more than 20 years, and has shipped nearly 60 million discrete MRAMs, largely to the cache buffering and industrial markets.

GlobalFoundries has announced plans to use embedded STT-MRAM in its 22FDX platform, which uses fully-depleted SOI technology, as early as 2018.

Future versions of MRAM– such as spin orbit torque (SOT) MRAM and Voltage Controlled MRAM — could compete with SRAM and DRAM. Analysts said today’s spin-transfer torque STT-MRAM – referring to the torque that arises from the transfer of electron spins to the free magnetic layer — is vying for commercial adoption as ever-faster processors need higher performance memory subsystems.

STT-MRAM is fast enough to fit in as a new memory layer below the processor and the SRAM-based L1/L2 cache layers, and above DRAM and storage-level NAND flash layers, said Gary Bronner, vice president of research at Rambus Inc.

With good data retention and speed, and medium density, MRAM “may have advantages in the lower-level caches” of systems which have large amounts of on-chip SRAM, Bronner said, due in part to MRAM’s smaller cell size than six-transistor SRAM. While DRAM in the sub-20nm nodes faces cost issues as its moves to more complex capacitor structures, Bronner said that “thus far STT-MRAM) is not cheaper than DRAM.”

IBM researchers, which pioneered the spin-transfer torque approach to MRAM, are working on a high-performance MRAM technology which could be used in servers.

As of now, MRAM density is limited largely by the size of the transistors required to drive sufficient current to the magnetic tunnel junction (MTJ) to flip its magnetic orientation. Dan Edelstein, an IBM fellow working on MRAM development at IBM Research, said “it is a tall order for MRAM to replace DRAM. But MRAM could be used in system-level memory architectures and as an embedded memory technology.”

PVD and etch challenges

Edelstein, who was a key figure in developing copper interconnects at IBM some twenty years ago, said MRAM only requires a few extra mask layers to be integrated into the BEOL in logic. But there remain major challenges in improving the throughput of the PVD deposition steps required to deposit the complex material stack and to control the interfacial layers.

The PVD steps must deposit approximately 30 layers and control them to Angstrom-level precision. Deposition must occur under very low base pressure, and in oxygen- and water-vapor free environments. While tool vendors are working on productization of 300mm MRAM deposition tools, Edelstein said keeping particles under control and minimizing the maintenance and chamber cleaning are all challenging.

Etching the complex materials stack is even harder. Chemical RIE is not practical for MRAMs at this point, and using ion beam etching (IBE) presents challenges in terms of avoiding re-deposition of material sputtered off during the IBE etch steps for the high-aspect-ratio MTJs.

For the tool vendors, MRAMs present challenges as companies go from R&D to high-volume manufacturing, Edelstein said.

A Samsung MRAM researcher, Y.J. Song, briefly described IBE challenges during an IEDM presentation describing an embedded STT-MRAM with a respectable 8-Mbit density and a cell size of .0364 sq. micron. “We worked to optimize the contact etching,” using IBE etch during the patterning steps, he said. The short fail rate was reduced, while keeping the processing temperature at less than 350°C, Song said.

Samsung embedded an STT-MRAM module in the copper back end of the line (BEOL) of a 28nm logic process. (Source: Samsung presentation at IEDM 2016).

Many of the presentations at IEDM described improvements in key parameters, such as the tunnel magnetic resistance (TMR), cell size, data retention, and read error rates at high temperatures or low operating voltages.

An SK Hynix presentation described a 4-Gbit STT-MRAM optimized as a stand-alone, high-density memory. “There still are reliability issues for high-density MRAM memory,” said SK Hynix’s S.-W. Chung. The industry needs to boost the TMR “as high as possible” and work on improving the “not sufficiently long” retention times.

At high temperatures, error rates tend to rise, a concern in certain applications. And since devices are subjected to brief periods of high temperatures during reflow soldering, that issue must be dealt with as well, detailed by a Bosch presentation at IEDM.

Cleans and encapsulation important

Gouri Sankar Kar, who is coordinating the MRAM research program at the Imec consortium (Leuven, Belgium), said one challenge is to reduce the cell size and pitch without damaging the magnetic properties of the magnetic tunnel junction. For the 28nm logic node, embedded MRAM would be in the range of a 200nm pitch and 45nm critical dimensions (CDs). At the IEDM poster session, Imec presented an 8nm cell size STT-MRAM that could intersect the 10nm logic node, with the MRAM pitch in the 100nm range. GlobalFoundries, Micron, Qualcomm, Sony and TSMC are among the participants in the Imec MRAM effort.

Kar said in addition to the etch challenges, post-patterning treatment and the encapsulation liner can have a major impact on MTJ materials selection. “Some metals can be cleaned immediately, and some not. For the materials stack, patterning (litho and etch) and clean optimization are crucial.”

“Chemical etch (RIE) is not really possible at this stage. All the tool vendors are working on physical sputter etch (IBE) where they can limit damage. But I would say all the major tool vendors at this point have good tools,” Kar said.

To reach volume manufacturing, tool vendors need to improve the tool up-time and reduce the maintenance cycles. There is a “tail bits” relationship between the rate of bit failures and the health of the chambers that still needs improvement. “The cleanup steps after etching are very, very critical” to the overall effort to improving the cost effectiveness of MRAM, Kar said, adding that he is “very positive” about the future of MRAM technology.

A complete flow at AMAT

Applied Materials is among the equipment companies participating in the Imec program, with TEL and Canon-Anelva also heavily involved. Beyond that, Applied has developed a complete MRAM manufacturing flow at the company’s Dan Maydan Center in Santa Clara, and presented its cooperative work with Qualcomm on MRAM development at IEDM.

In an interview, Er-Xuan Ping, the Applied Materials managing director in charge of memory and materials technologies, said about 20 different layers, including about ten different materials, must be deposited to create the magnetic tunnel junctions. As recently as a few years ago, throughput of this materials stack was “extremely slow,” he said. But now Applied’s multi-cathode PVD tool, specially developed for MRAM deposition, can deposit 5 Angstrom films in just a few seconds. Throughput is approaching 20 wafers per hour.

Applied Materials “basically created a brand-new PVD chamber” for STT-MRAM, and he said the tool has a new e-chuck, optimized chamber walls and a multi-cathode design.

The MRAM-optimized PVD tool does not have an official name yet, and Ping said he refers to it as multi-cathode PVD. With MRAM requiring deposition of so many different metals and other materials, the Applied tool does not require the wafer to be moved in and out, increasing efficiency. The shape and structure of the chamber wall, Ping said, allow absorption of downstream plasma material so that it doesn’t come back as particles.

For etch, Applied has worked to create etching processes that result in very low bit failure rates, but at relatively relaxed pitches in the 130-200nm range. “We have developed new etch technologies so we don’t think etch will be a limiting factor. But etch is still challenging, especially for cells with 50nm and smaller cell sizes. We are still in unknown territory there,” said Ping.

Jürgen Langer, R&D manager at Singulus Technology (Frankfurt, Germany), said Singulus has developed a production-optimized PVD tool which can deposit “30 material layers in the Angstrom range. We can get 20 wafers per hour throughputs, so I would say this is not a beta tool, it is for production.”

Jürgen Langer, R&D manager, presented a poster on MRAM deposition from Singulus Technology (Frankfurt, Germany).

Where does it fit?

Once the production challenges of making MRAM are ironed out, the question remains: Where will MRAM fit in the systems of tomorrow?

Tom Coughlin, a data storage consultant based in Atascadero, Calif., said embedded MRAM “could have a very important effect for industrial and consumer devices. MRAM could be part of the memory cache layers, providing power advantages over other non-volatile devices.” And with its ability to power on and power off without expending energy, MRAM could reduce overall power consumption in smart phones, cutting in to the SRAM and NOR sectors.

“MRAM definitely has a niche, replacing some DRAM and SRAM. It may replace NOR. Flash will continue for mass storage, and then there is the 3D Crosspoint from Intel. I do believe MRAM has a solid basis for being part of that menagerie. We are almost in a Cambrian explosion in memory these days,” Coughlin said.

Has SOI’s Turn Come Around Again?

Monday, October 10th, 2016

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By David Lammers, Contributing Editor

When analyst Linley Gwennap is asked about the chances that fully-depleted silicon-on-insulator (FD-SOI) technology will make it in the marketplace, he gives a short history lesson.

First, he makes clear that the discussion is not about “the older SOI,” – the partially depleted SOI that required designers to deal with the so-called “kink effect.” The FD-SOI being offered by STMicroelectronics and Samsung at 28nm design rules, and by GlobalFoundries at 22nm and 12nm, is a different animal: a fully depleted channel, new IP libraries, and no kink effect.

Bulk planar CMOS transistor scaling came to an end at 28nm, and leading-edge companies such as Intel, TSMC, Samsung, and GlobalFoundries moved into the finFET realm for performance-driven products, said Gwennap, founder of The Linley Group (Mountain View, Calif.) and publisher of The Microprocessor Report, said,

While FD-SOI at the 28nm node was offered by STMicrelectronics, with Samsung coming in as a second source, Gwennap said 28nm FD-SOI was not differentiated enough from 28nm bulk CMOS to justify the extra design and wafer costs. “When STMicro came out with 28 FD, it was more expensive than bulk CMOS, so the value proposition was not that great.”

NXP uses 28nm FD-SOI for its iMX 7 and iMX 8 processors, but relatively few other companies did 28nm FD-SOI designs. That may change as 22nm FD-SOI offers a boost in transistor density, and a roadmap to tighter design rules.

“For planar CMOS, Moore’s Law came to a dead end at 28nm. Some companies have looked at finFETs and decided that the cost barrier is just too high. They don’t have anywhere to go; for a few years now those companies have been at 28nm, they can’t justify the move on to finFETs, and they need to figure out how they can offer something new to their customers. For those companies, taking a risk on FD-SOI is starting to look like a good idea,” he said.

A cautious view

Joanne Itow, foundry analyst at Semico Research (Phoenix), also has been observing the ups and downs of SOI technology over the last two decades. The end of the early heyday, marked by PD-SOI-based products from IBM, Advanced Micro Devices, Freescale Semiconductor, and several game system vendors, has led Itow to take a cautious, Show-Me attitude.

“The SOI proponents always said, ‘this is the breakout node,’ but then it didn’t happen. Now, they are saying the Fmax has better results than finFETs, and while we do see some promising results, I’m not sure everybody knows what to do with it. And there may be bottlenecks,” such as the design tools and IP cores.

Itow said she has talked to more companies that are looking at FD-SOI, and some of them have teams designing products. “So we are seeing more serious activity than before,” Itow said. “I don’t see it being the main Qualcomm process for high-volume products like the applications processors in smartphones. But I do see it being looked at for IoT applications that will come on line in a couple of years. And these things always seem to take longer than you think,” she said.

Sony Corp. has publicly discussed a GPS IC based on 28nm FD-SOI that is being deployed in a smartwatch sold by Huami, a Chinese brand, which is touting the long battery life of the watch when the GPS function is turned on.

GlobalFoundries claims it has more than 50 companies in various stages of development on its 22FDX process, which enters risk production early next year, and the company plans a 12nm FDX offering in several years.

IP libraries put together

The availability of design libraries – both foundation IP and complex cores – is an issue facing FD-SOI. Gwennap said GlobalFoundries has worked with EDA partners, and invested in an IP development company, Invecas, to develop an IP library for its FDX technology. “Even though GlobalFoundries is basically starting from scratch in terms of putting together an IP library, it doesn’t take that long to put together the basic IP, such as the interface cells, that their customers need.

“There is definitely going to be an unusual thing that probably will not be in the existing library, something that either GlobalFoundries or the customers will have to put together. Over time, I believe that the IP portfolio will get built out,” Gwennap said.

The salaries paid to design engineers in Asia tend to be less than half of what U.S.-based designers are paid, he noted. That may open up companies “with a lower cost engineering team” in India, China, Taiwan, and elsewhere to “go off in a different direction” and experiment with FD-SOI, Gwennap said.

Philippe Flatresses, a design architect at STMicro, said with the existing FDSOI ecosystem it is possible to design a complete SoC, including processor cores from ARM Ltd., high speed interfaces, USB, MIPI, memory controllers, and other IP from third-party providers including Synopsys and Cadence. Looking at the FD-SOI roadmap, several technology derivatives are under development to address the RF, ultra-low voltage, and other markets. Flatresses said there is a need to extend the IP ecosystem in those areas.

Wafer costs not a big factor

There was a time when the approximately $500 cost for an SOI wafer from Soitec (Grenoble, France) tipped the scales away from SOI technology for some cost-sensitive applications. Gwennap said when a fully processed 28nm planar CMOS wafer cost about $3,000 from a major foundry, that $500 SOI wafer cost presented a stumbling block to some companies considering FD-SOI.

Now, however, a fully-processed finFET wafer costs $7,000 or more from the major foundries, Gwennap said, and the cost of the SOI wafer is a much smaller fraction of the total cost equation. When companies compare planar FD-SOI to finFETs, that $500 wafer cost, Gwennap said, “just isn’t as important as it used to be. And some of the other advantages in terms of cost savings or power savings are pretty attractive in markets where cost is important, such as consumer and IoT products. They present a good chance to get some key design wins.”

Soitec claims it can ramp up to 1.5 million FD-SOI wafers a year with its existing facility in 18 months, and has the ability to expand to 3 million wafers if market demand expands.

Jamie Schaeffer, the FDX program manager at GlobalFoundries, acknowledges that the SOI wafers are three to four times more expensive than bulk silicon wafers. Schaeffer said a more important cost factor is in the mask set. A 22FDX chip with eight metal layers can be constructed with “just 39 mask layers, compared with 60 for a finFET design at comparable performance levels.” And no double patterning is required for the 22FDX transistors.

Technology advantages claimed

Soitec senior fellow Bich-Yen Nguyen, who spent much of her career at Freescale Semiconductor in technology development, claims several technical advantages for FD-SOI.

FD-SOI has a high transconductance-to-drain current ratio, is superior in terms of the short channel effect, and has a lower fringing and effective capacitance and lower gate resistance, due partly to a gate-first process approach to the high-k/metal gate steps, Nguyen said.

Back and forward biasing is another unique feature of FD-SOI. “When you apply body-bias, the fT and fmax curves shift to a lower Vt.  This is an additional benefit allowing the RF designer to achieve higher fT and fmax at much lower gate voltage (Vg) over a wider Vg range.  That is a huge benefit for the RF designer,” she said. Figure 1 illustrates the unique benefit of back-bias.

Figure 1. The unique benefit of back-bias is illustrated. Source: GlobalFoundries.

“To get the full benefit of body bias for power savings or performance improvement, the design teams must consider this feature from the very beginning of product development,” she said. While biasing does not require specific EDA tools, and can be achieve with an extended library characterization, design architects must define the best corners for body bias in order to gain in performance and power. And design teams must implement “the right set of IPs to manage body biasing,” such as a BB generator, BB monitors, and during testing, a trimming methodology.

Nguyen acknowledged that finFETs have drive-current advantages. But compared with bulk CMOS, FD-SOI has superior electrostatics, which enables scaling of analog/RF devices while maintaining a high transistor gain. And drive current increases as gate length is scaled, she said.

For 14/16 nm finFETs, Nguyen said the gate length is in the 25-30 nm range. The 22FDX transistors have a gate length in the 20nm range. “The very short gate length results in a small gate capacitance, and total lower gate resistance,” she said.

For fringing capacitance, the most conservative number is that 22nm FD-SOI is 30 percent lower than leading finFETs, though she said “finFETs have made a lot of progress in this area.”

Analog advantages

It is in the analog and RF areas that FD-SOI offers the most significant advantages, Nguyen said. The fT and fMAX of 350 and 300 GHz, respectively, have been demonstrated by GlobalFoundries for its 22nm FD-SOI technology. For analog devices, she claimed that FD-SOI offers better transistor mismatch, high intrinsic device gain (Gm/Gds ratio), low noise, and flexibility in Vt tuning. Figure 2 shows how 22FDX outperforms finFETs for fT/fMax.

Figure 2. 22FDX outperforms finFETs for fT/fMax. Source: GlobalFoundries.

“FDSOI is the only device architecture that meets all those requirements. Bulk planar CMOS suffers from large transistor mismatch due to random dopant fluctuation and low device gain due to poor electrostatics. FinFET technology improves on electrostatics but it lacks the back bias capability.”

The undoped channel takes away the random doping effect of a partially depleted (doped) channel, reducing variation by 50-60 percent.

Analog designers using FD-SOI, she said, have “the ability to tune the Vt by back-bias to compensate for process mismatch or drift, and to offer virtually any Vt desired. Near-zero Vt can also be achieved in FD-SOI, which enables low voltage analog design for low power consumption applications.”

“If you believe the future is about mobility, about more communications and low power consumption and cost sensitive IoT chips where analog and RF is about 50 percent of the chip, then FD-SOI has a good future.

“No single solution can fit all. The key is to build up the ecosystem, and with time, we are pushing that,” she said.

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