Posts Tagged ‘GlobalFoundries’
By Ed Korczynski, Sr. Technical Editor
At IEDM 2014 last month in San Francisco, Applied Materials sponsored an evening panel discussion on the theme of “How do we continue past 7nm?” Given that leading fabs are now ramping 14nm node processes, and exploring manufacturing options for the 10nm node, “past 7nm” means 5nm node processing. There are many device options possible, but cost-effective manufacturing at this scale will require Extreme Ultra-Violet (EUV) lithography to avoid the costs of quadruple-patterning.
Figure 1 shows the panel being moderated by Professor Mark Rodwell of the University of California Santa Barbara, composed of the following industry experts:
- Karim Arabi, Ph.D. – vice president, engineering, Qualcomm,
- Michael Guillorn, Ph.D. – research staff member, IBM,
- Witek Maszara, Ph.D. – distinguished member of technical staff, GLOBALFOUNDRIES,
- Aaron Thean, Ph.D. – vice president, logic process technologies, imec, and
- Satheesh Kuppurao, Ph.D. – vice president, front end products group, Applied Materials.
Arabi said that from the design perspective the overarching concern is to keep “innovating at the edge” of instantaneous and mobile processing. At the transistor level, the 10nm node process will be similar to that at the 14nm node, though perhaps with alternate channels. The 7nm node will be an inflection point with more innovation needed such as gate-all-around (GAA) nanowires in a horizontal array. By the 5nm node there’s no way to avoid tunnel FETs and III-V channels and possibly vertical nanowires, though self-heating issues could become very challenging. There’s no shortage of good ideas in the front end and lots of optimism that we’ll be able to make the transistors somehow, but the situation in the backend of on-chip metal interconnect is looking like it could become a bottleneck.
Guillorn extolled the virtues of embedded-memory to accelerate logic functions, as a great example of co-optimization at the chip level providing a real boost in performance at the system level. The infection at 7nm and beyond could lead to GAA Carbon Nano-Tube (CNT) as the minimum functional device. It’s limited to think about future devices only in terms of dimensional shrinks, since much of the performance improvement will come from new materials and new device and technology integration. In addition to concerns with interconnects, maintaining acceptable resistance in transistor contacts will be very difficult with reduced contact areas.
Maszara provided target numbers for a 5nm node technology to provide a 50% area shrink over 7nm: gate pitch of 30nm, and interconnect level Metal 1 (M1) pitch of 20nm. To reach those targets, GLOBALFOUNDRIES’ cost models show that EUV with ~0.5 N.A. would be needed. Even if much of the lithography could use some manner of Directed Self-Assembly (DSA), EUV would still be needed for cut-masks and contacts. In terms of device performance, either finFET or nanowires could provide desired off current but the challenge then becomes how to get the on current for intended mobile applications? Alternative channels with high mobility materials could work but it remains to be seen how they will be integrated. A rough calculation of cost is the number of mask layers, and for 5nm node processing the cost/transistor could still go down if the industry has ideal EUV. Otherwise, the only affordable way to go may be stay at 7nm node specs but do transistor stacking.
Thein detailed why electrostatic scaling is a key factor. Parasitics will be extraordinary for any 5nm node devices due to the intrinsically higher number of surfaces and junctions within the same volume. Just the parasitic capacitances at 7nm are modeled as being 75% of the total capacitance of the chip. The device trend from planar to finFET to nanowires means proportionally increasing relative surface areas, which results in inherently greater sensitivity to surface-defects and interface-traps. Scaling to smaller structures may not help you if you loose most of the current and voltage in non-useful traps and defects, and that has already been seen in comparisons of III-V finFETs and nanowires. Also, 2D scaling of CMOS gates is not sustainable, and so one motivation for considering vertical transistors for logic at 5nm would be to allow for 20nm gates at 30nm pitch.
Kappurao reminded attendees that while there is still uncertainty regarding the device structures beyond 7nm, there is certainty in 4 trends for equipment processes the industry will need:
- everything is an interface requiring precision materials engineering,
- film depositions are either atomic-layer or selective films or even lattice-matched,
- pattern definition using dry selective-removal and directed self-assembly, and
- architecture in 3D means high aspect-ratio processing and non-equilibrium processing.
An example of non-equilibrium processing is single-wafer rapid-thermal-annealers (RTA) that today run for nanoseconds—providing the same or even better performance than equilibrium. Figure 2 shows that a cobalt-liner for copper lines along with a selective-cobalt cap provides a 10x improvement in electromigration compared to the previous process-of-record, which is an example of precision materials engineering solving scaling performance issues.
“We have to figure out how to control these materials,” reminded Kappurao. “At 5nm we’re talking about atomic precision, and we have to invent technologies that can control these things reliably in a manufacturable manner.” Whether it’s channel or contact or gate or interconnect, all the materials are going to change as we keep adding more functionality at smaller device sizes.
There is tremendous momentum in the industry behind density scaling, but when economic limits of 2D scaling are reached then designers will have to start working on 3D monolithic. It is likely that the industry will need even more integration of design and manufacturing, because it will be very challenging to keep the cost-per-function decreasing. After CMOS there are still many options for new devices to arrive in the form of spintronics or tunnel-FETs or quantum-dots.
However, Arabi reminded attendees as to why the industry has stayed with CMOS digital synchronous technology leading to design tools and a manufacturing roadmap in an ecosystem. “The industry hit a jackpot with CMOS digital. Let’s face it, we have not even been able to do asynchronous logic…even though people tried it for many years. My prediction is we’ll go as far as we can until we hit atomic limits.”
IBM and GLOBALFOUNDRIES this week announced that GLOBALFOUNDRIES will acquire IBM’s global commercial semiconductor technology business, including IBM’s intellectual property, technologists and technologies. IBM will pay GLOBALFOUNDRIES $1.5 billion in cash over the next three years to take the chip operations off its hands. The cash consideration will be adjusted by the amount of working capital which is estimated to be $200 million.
Capped by last week’s announcement that Qualcomm Inc. would buy CSR PLC, the automotive semiconductor industry recently has been undergoing a wave of merger and acquisition activity that has shaken up the competitive order of the market, according to IHS Technology.
Adlyte Inc., a developer of high-brightness extreme light sources for advanced semiconductor inspection and metrology applications, announced it has reached a key performance benchmark for its extreme ultraviolet (EUV) light source for high-volume manufacturing (HVM)-readiness.
Gigaphoton Inc., a lithography light source manufacturer, announced that it has succeeded in achieving 3-hour continuous operation of its prototype LPP EUV light source at 50 percent duty cycle and 42-W output, equivalent to usage in a high-volume-manufacturing (HVM) environment.
North America-based manufacturers of semiconductor equipment posted $1.17 billion in orders worldwide in September 2014 (three-month average basis) and a book-to-bill ratio of 0.94, according to the September EMDS Book-to-Bill Report published today by SEMI. A book-to-bill of 0.94 means that $94 worth of orders were received for every $100 of product billed for the month.
Matthew Hogan of Mentor Graphics blogs about how automotive opportunities are presenting new challenges for IC verification. A common theme for safety systems involves increasingly complex ICs and the need for exceptional reliability.
Anish Tolia of Linde blogs that technology changes in semiconductor processing and demands for higher-purity and better-characterized electronic materials have driven the need for advanced analytical metrology. Apart from focusing on major assay components, which are the impurities detailed in a Certificate of Analysis (CoA), some customers are also asking that minor assay components or other trace impurities must be controlled for critical materials used in advanced device manufacturing.
Karey Holland of Techcet provides an excellent review of SEMI’s Strategic Materials Conference. The keynote presentation, “Materials Innovation for the Digital 6th Sense Era,” was by Matt Nowak of Qualcomm. He discussed both the vision of the Internet of Things (IoT), the required IC devices (including analog & sensors) and implications to materials (and cost to manufacture) from these new IC devices.
The age of the Internet of Things is upon us, blogs Pete Singer. There are, of course, two aspects of IoT. One is at what you might call the sensor level, where small, low power devices are gathering data and communicating with one another and the “cloud.” The other is the cloud itself. One key aspect will be security, even for low-level devices such as the web-connected light bulb. Don’t hack my light bulb, bro!
Linde Electronics has developed the TLIMS/SQC System. Anish Tolia writes that this system includes an information management database plus SQC/SPC software and delivers connectivity with SAP, electronically pulling order information from SAP to TLIMS and pushing CoA data from TLIMS to SAP.
Ed Korczynski blogs about how IBM researchers showed the ability to grow sheets of graphene on the surface of 100mm-diameter SiC wafers, the further abilitity to grow epitaxial single-crystalline films such as 2.5-μm-thick GaN on the graphene, the even greater ability to then transfer the grown GaN film to any arbitrary substrate, and the complete proof-of-manufacturing-concept of using this to make blue LEDs.
Phil Garrou says it’s been awhile since we looked at what is new in the polymer dielectric market so he checked with a number of dielectric suppliers – specifically Dow Corning, HD Micro and Zeon — and asked what was new in their product lines.
Karen Lightman, Executive Director, MEMS Industry Group, had the pleasure to learn more about the challenges and opportunities affecting MEMS packaging at a recent International Microelectronics Assembly and Packaging Society (IMAPS) workshop held in her hometown of Pittsburgh and at her alma mater, Carnegie Mellon University (CMU).
Ed Korczynski blogs that The Nobel Prize in Physics 2014 was awarded jointly to Isamu Akasaki, Hiroshi Amano, and Shuji Nakamura “for the invention of efficient blue light-emitting diodes which has enabled bright and energy-saving white light sources.”
Yes, GlobalFoundries is hot on FD-SOI. Yes, Qualcomm’s interested in it for IoT. Yes, ST’s got more amazing low-power FD-SOI results. These are just some of the highlights that came out of the Low Power Conference during Semicon Europa in Grenoble, France (7-9 October 2014) blogs Adele Hars.
By Ed Korczynski, Sr. Technical Editor
Virtual Roundtable provides perspective on the need for greater integration within the “fabless-foundry” ecosystem
Q1: The fabless-foundry relationship in commercial IC manufacturing was established during an era of fab technology predictability—clear litho roadmaps for smaller and cheaper devices—but the future of fab technology seems unpredictable. The complexity which must be managed by a fabless company has already increased to justify leaders such as Apple or Qualcomm investing in technology R&D with foundries and with EDA- and OEM-companies. With manufacturing process technology integrating more materials with ever smaller nodes, how do we manage such complexity?
ANSWER: Gregg Bartlett, Senior Vice President, Product Management, GLOBALFOUNDRIES
The vast majority of Integrated Device Manufacturers (IDMs) have either gone completely fabless or partnered with foundries for their leading-edge technology needs instead of making the huge investments necessary to keep pace with technology. The foundry opportunity is increasingly concentrated at the leading edge; this segment is expected to drive 60 percent of the total foundry market by 2016, representing a total of $27.5 billion. Yet there are fewer high-volume manufacturers that have the capabilities to offer leading-edge technologies beyond 28nm, even as the major companies have accelerated their technology roadmaps at 20nm and 14nm and added new device architectures.
This has led to a global capacity challenge. Leading-edge fabs are more expensive and fewer than ever. At the 130nm node, the cost to build a fab was just over $1B. For a 28nm fab, the cost is about $6B and a 14nm fab is nearly $10B. Technology development costs are rising at a similar rate, growing from a few $10M’s at 130nm to several $100M’s at 28nm.
On top of these technology and manufacturing challenges, product life cycles are shrinking and end users are expecting more and more from their devices in terms of performance, power-efficiency, and features. Competing on manufacturing expertise alone is no longer a viable strategy in today’s semiconductor industry, and solutions developed in isolation are not adequate. The industry must work closer across all levels of the supply chain to understand these dynamics and how they put demands on the silicon chip.
Fortunately, the fabless/foundry model is evolving to accommodate these changing dynamics. We have been promoting this idea for years with what we like to call “Foundry 2.0.” In the 1970s/1980s, the industry was dominated by the IDM. Then the foundry model was invented and grew to prominence in the 1990s and early 2000s, but it was much more of a contract manufacturing model. A fabless company developed a design in isolation and then “threw it over the wall” to the foundry for manufacturing. There was not much need for interplay between the two companies. Of course, as technology complexity has increased in the past decade, this dynamic has changed dramatically. We have entered the era of collaborative device manufacturing. Collaboration is a buzz word that gets thrown around a lot, but today it really is critical and it needs to happen across all vectors, including design flow development, manufacturing supply chain, and customer engagement.
Q2: 3D in packaging started with wire-bonded-chip-stacks and now includes silicon-interposers (a.k.a. “2.5D”) and the memory-cube using through-silicon via (TSV). How about the complexity of 3D products using chip-package co-design, and many players in the ecosystem being needed hroughout design-ramp-HVM?
ANSWER: Sesh Ramaswami, Managing Director, TSV and Advanced Packaging, Silicon Systems Group of Applied Materials
Enabling 3D requires the participation of the extended ecosystem. These include contributions from CAD, design tools for die architecture, floor plan, and layout circuit design test structures, as well as methodology wafer level process equipment and materials, wafer-level test assembly and packaging stacked die and package level testing.
Q3: Due to challenges with lithographic scaling below 45nm half-pitch, how does the need to integrate new materials and device structures change the fabless-foundry relationship? How much of fully-depleted channels using SOI wafers and/or finFETs, followed by alternate channels can the industry afford without commited damand from IDMs and major fabless players for specific variants?
ANSWER: Adam Brand, Director of Transistor Technology, Silicon Systems Group of Applied Materials
New materials and device structures are going to play a key role in advancing the technology to the next several nodes.
With EUV delayed, multi-patterning is growing in use, and new materials are enabling the sophisticated and precise extension of multi-patterning to the 7nm node and beyond. The multi-patterning schemes however bring specific restrictions on layout which will affect the design process.
For device structures, Epi in particular is going to enable the next generation of complex device designs with improved mobility and by supporting very thin precisely defined channel structures to scale to smaller gate length and pitch. For these next generation devices, the R&D challenges will be high, but the industry cannot afford to skimp on R&D to find the winning solution to the low power transistor technology required for the 7nm and 5nm and beyond nodes.
Q4: Mobile consumer devices now seem to drive the leading edge of demand for many ICs. However, the Internet-of-Things (IoT) is often spoken of needing just 65nm node chips to keep costs as low as possible, and these designs are expected to run in high volume for many years. How will these different devices that will continue to evolve in different ways get integrated together?
ANSWER: Michael Buehler-Garcia, Senior Director of Marketing, Calibre Design Solutions of Mentor Graphics
IOT has become the new industry buzz word. What it has done is spotlight the multiple elements of a complete solution that do not require emerging process technologies for their chip design. Moreover, while a chip may use a well established process node, the actual design may be very complex. For example Mentor is participating in the German RESCAR program to increase the reliability of automotive electronics using our Calibre PERC solution. The initial reliability checks written are targeted for 180nm and older process nodes. Why? Because today’s 180nm and older node designs are much more complex than when these nodes were mainstream digital nodes and as such require more advanced verification solutions. Bottom line: as opposed to a strategy of only moving to the next process node, chip design companies today have multiple options. It is up to the ecosystem to provide solutions that allow the designers be able to make trade-offs without major changes in their design flows.
Front End fab equipment spending is projected to increase up to another 20 percent in 2015 to US$ 42 billion, according to most recent edition of the SEMI World Fab Forecast. In 2015, equipment spending could mark a historical record high, surpassing the previous peak years of 2007 ($39 billion) and 2011 ($40 billion). In 2014, the report predicts growth of approximately 21 percent for Front End fab equipment spending, for total spending of $34.9 billion.
GLOBALFOUNDRIES announced the “GLOBALFOUNDRIES Undergraduate Research Scholarship,” a new scholarship recognizing and rewarding aspiring, leadership-oriented engineering students interested in careers in the semiconductor industry.
SEMI announced that it has successfully appealed to the U.S. government to review the validity of current export controls on semiconductor etch equipment. On September 8, 2014, the U.S. Department of Commerce published a notice in the Federal Register announcing the launch of the first Foreign Availability Assessment in more than 20 years.
A new company, Epiluvac AB, has entered the scene with the ambition to supply the needed deposition equipment.
Spending on microwave RF power semiconductors continues to tick upward as the availability of new gallium nitride (GaN) devices for 4 to 18GHz becomes more pervasive. Point-to-point communications, SATCOM, radars of all types, and new industrial/medical applications will all benefit by the introduction of these high-power GaN devices. These findings are part of ABI Research’s High-Power RF Active Devices Market Research.
GLOBALFOUNDRIES and SRC announce new scholarship for undergraduate engineering students
GLOBALFOUNDRIES today announced the “GLOBALFOUNDRIES Undergraduate Research Scholarship,” a new scholarship recognizing and rewarding aspiring, leadership-oriented engineering students interested in careers in the semiconductor industry. The GLOBALFOUNDRIES Undergraduate Research Scholarship will fund undergraduate research opportunities (URO) and intern scholars through the Semiconductor Research Corporation’s (SRC) Education Alliance.
Presented at SRC’s annual TECHCON conference in Austin, Texas, the scholarship was created by GLOBALFOUNDRIES in partnership with SRC to recognize and reward science, technology and engineering students who demonstrate promise in their academic and professional efforts. The selected recipients of this scholarship will have the opportunity to interact with GLOBALFOUNDRIES researchers and access the professional resources of SRC and the SRC Education Alliance.
“Building a pipeline of highly skilled talent is essential to our business and to the competitiveness of the entire semiconductor industry,” said Suresh Venkatesan, senior vice president of technology development, GLOBALFOUNDRIES. “SRC connects companies with the top universities, which results in exciting research and educational opportunities for the best and the brightest students. The GLOBALFOUNDRIES Undergraduate Research Scholarship gives us the opportunity to support science, technology, engineering and mathematics education and help develop the technical leaders who will continue to drive innovation in the semiconductor industry in the future.”
Until recently, SRC focused exclusively on students seeking advanced degrees, providing fellowships for them to do university research that had practical applications for corporate members of its unique consortium. The URO is SRC’s innovative program providing undergraduates with valuable research experience and mentoring. The goal of the URO is to empower bright, well-educated, and experienced scientists and engineers for which U.S. high-tech companies are seeking.
“Recognizing the critical importance of a strong pipeline of new talent for the semiconductor industry, the SRC Education Alliance through the URO Program provides financial assistance to undergraduates, allowing students and universities to recognize the connections between the materials they are learning in the classroom and the technological innovations that transform the world,” said SRC President Larry Sumney. “We are thrilled to collaborate with GLOBALFOUNDRIES as we continue to develop our URO program.”
Layered graphene sandwich for next generation electronics
Sandwiching layers of graphene with white graphene could produce designer materials capable of creating high-frequency electronic devices, University of Manchester scientists have found. The researchers have demonstrated how combining the two-dimensional materials in a stack could create perfect crystals capable of being used in next generation transistors.
Hexagonal boron nitride (hBN), otherwise known as white graphene, is one of a family of two-dimension materials discovered in the wake of the isolation of graphene at the University in 2004. Manchester researchers have previously demonstrated how combining 2D materials, in stacks called heterostructures, could lead to materials capable of being designed to meet industrial demands.
Now, for the first time, the team has demonstrated that the electronic behaviour of the heterostructures can be changed enormously by precisely controlling the orientation of the crystalline layers within the stacks.
The researchers, led by University of Manchester Nobel laureate Sir Kostya Novoselov, carefully aligned two graphene electrodes separated by hBN and discovered there was a conservation of electron energy and momentum.
The findings could pave the way for devices with ultra-high frequencies, such as electronic or photovoltaic sensors.
The research was carried out with scientists from Lancaster and Nottingham Universities in the UK, and colleagues in Russia, Seoul and Japan.
Professor Laurence Eaves, a joint academic from the Universities of Manchester and Nottingham, said: “”This research arises from a beautiful combination of classical laws of motion and the quantum wave nature of electrons, which enables them to flow through barriers
“We are optimistic that further improvements to the device design will lead to applications in high-frequency electronics.”
Professor Vladimir Falko, from Lancaster University, added: “Our observation of tunnelling and negative differential conductance in devices made of multilayers of graphene and hexagonal boron nitride demonstrates potential that this system has for electronics applications.
“It is now up to material growers to find ways to produce such multilayer systems using growth techniques rather than mechanical transfer method used in this work.”
Doped graphene nanoribbons with potential
Graphene is a semiconductor when prepared as an ultra-narrow ribbon – although the material is actually a conductive material. Researchers from Empa and the Max Planck Institute for Polymer Research have now developed a new method to selectively dope graphene molecules with nitrogen atoms. By seamlessly stringing together doped and undoped graphene pieces, they were able to form ”heterojunctions” in the nanoribbons, thereby fulfilling a basic requirement for electronic current to flow in only one direction when voltage is applied – the first step towards a graphene transistor. Furthermore, the team has successfully managed to remove graphene nanoribbons from the gold substrate on which they were grown and to transfer them onto a non-conductive material.
Graphene possesses many outstanding properties: it conducts heat and electricity, it is transparent, harder than diamond and extremely strong. But in order to use it to construct electronic switches, a material must not only be an outstanding conductor, it should also be switchable between ”on” and ”off” states. This requires the presence of a so-called bandgap, which enables semiconductors to be in an insulating state. The problem, however, is that the bandgap in graphene is extremely small. Empa researchers from the ”nanotech@surfaces” laboratory thus developed a method some time ago to synthesise a form of graphene with larger bandgaps by allowing ultra-narrow graphene nanoribbons to ”grow” via molecular self-assembly.
The researchers, led by Roman Fasel, have now achieved a new milestone by allowing graphene nanoribbons consisting of differently doped subsegments to grow. Instead of always using the same ”pure” carbon molecules, they used additionally doped molecules – molecules provided with ”foreign atoms” in precisely defined positions, in this case nitrogen. By stringing together ”normal” segments with nitrogen-doped segments on a gold (Au (111)) surface, so-called heterojunctions are created between the individual segments. The researchers have shown that these display similar properties to those of a classic p-n-junction, i.e. a junction featuring both positive and negative charges across different regions of the semiconductor crystal, thereby creating the basic structure allowing the development of many components used in the semiconductor industry. A p-n junction causes current to flow in only one direction. Because of the sharp transition at the heterojunction interface, the new structure also allows electron/hole pairs to be efficiently separated when an external voltage is applied, as demonstrated theoretically by theorists at Empa and collaborators at Rensselaer Polytechnic Institute. The latter has a direct impact on the power yield of solar cells. The researchers describe the corresponding heterojunctions in segmented graphene nanoribbons in the recently published issue of “Nature Nanotechnology.”
In addition, the scientists have solved another key issue for the integration of graphene nanotechnology into conventional semiconductor industry: how to transfer the ultra-narrow graphene ribbons onto another surface? As long as the graphene nanoribbons remain on a metal substrate (such as gold used here) they cannot be used as electronic switches. Gold conducts and thus creates a short-circuit that “sabotages” the appealing semiconducting properties of the graphene ribbon. Fasel’s team and colleagues at the Max-Planck-Institute for Polymer Research in Mainz have succeeded in showing that graphene nanoribbons can be transferred efficiently and intact using a relatively simple etching and cleaning process onto (virtually) any substrate, for example onto sapphire, calcium fluoride or silicon oxide.
A new spin on spintronics; Novel solid-state nanomaterial platform enables terahertz photonics; Novel crumpling method takes flat graphene from 2-D to 3-D
Fabrication of patterns with linewidths down to 1.5nm; New method allows for greater variation in band gap tunability; New pathway to valleytronics
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.