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Silicon Photonics Technology Developments

Thursday, April 6th, 2017


By Ed Korczynski, Sr. Technical Editor

With rapidly increasing use of “Cloud” client:server computing there is motivation to find cost-savings in the Cloud hardware, which leads to R&D of improved photonics chips. Silicon photonics chips could reduce hardware costs compared to existing solutions based on indium-phosphide (InP) compound semiconductors, but only with improved devices and integration schemes. Now MIT researchers working within the US AIM Photonics program have shown important new silicon photonics properties. Meanwhile, GlobalFoundries has found a way to allow for automated passive alignment of optical fibers to silicon chips, and makes chips on 300mm silicon wafers for improved performance at lower cost.

In a recent issue of Nature Photonics, MIT researchers present “Electric field-induced second-order nonlinear optical effects in silicon waveguides.” They also report prototypes of two different silicon devices that exploit those nonlinearities: a modulator, which encodes data onto an optical beam, and a frequency doubler, a component vital to the development of lasers that can be precisely tuned to a range of different frequencies.

This work happened within the American Institute for Manufacturing Integrated Photonics (AIM Photonics) program, which brought government, industry, and academia together in R&D of photonics to better position the U.S. relative to global competition. Federal funding of $110 million was combined with some $500 million from AIM Photonics’ consortium of state and local governments, manufacturing firms, universities, community colleges, and nonprofit organizations across the country. Michael Watts, an associate professor of electrical engineering and computer science at MIT, has led the technological innovation in silicon photonics.

“Now you can build a phase modulator that is not dependent on the free-carrier effect in silicon,” says Michael Watts in an online interview. “The benefit there is that the free-carrier effect in silicon always has a phase and amplitude coupling. So whenever you change the carrier concentration, you’re changing both the phase and the amplitude of the wave that’s passing through it. With second-order nonlinearity, you break that coupling, so you can have a pure phase modulator. That’s important for a lot of applications.”

The first author on the new paper is Erman Timurdogan, who completed his PhD at MIT last year and is now at the silicon-photonics company Analog Photonics. The frequency doubler uses regions of p- and n-doped silicon arranged in regularly spaced bands perpendicular to an undoped silicon waveguide. The space between bands is tuned to a specific wavelength of light, such that a voltage across them doubles the frequency of the optical signal passing. Frequency doublers can be used as precise on-chip optical clocks and amplifiers, and as terahertz radiation sources for security applications.

GlobalFoundries’ Packaging Prowess

At the start of the AIM Photonics program in 2015, MIT researchers had demonstrated light detectors built from efficient ring resonators that they could reduce the energy cost of transmitting a bit of information down to about a picojoule, or one-tenth of what all-electronic chips require. Jagdeep Shah, a researcher at the U.S. Department of Defense’s Institute for Defense Analyses who initiated the program that sponsored the work said, “I think that the GlobalFoundries process was an industry-standard 45-nanometer design-rule process.”

The Figure shows that researchers at IBM developed an automated method to assemble twelve optical fibers to a
silicon chip while the fibers are dark, and GlobalFoundries chips can now be paired with this assembly technology. Because the micron-scale fibers must be aligned with nanometer precision, default industry standard has been to expensively align actively lit fibers. Leveraging the company’s work for Micro-Electro-Mechanical Sensors (MEMS) customers, GlobalFoundries uses an automated pick-and-place tool to push ribbons of multiple fibers into MEMS groves for the alignment. Ted Letavic, Global Foundries’ senior fellow, said the edge coupling process was in production for a telecommunications application. Silicon photonics may find first applications for very high bandwidth, mid- to long-distance transmission (30 meters to 80 kilometers), where spectral efficiency is the key driver according to Letavic.

FIGURE: GlobalFoundries chips can be combined with IBM’s automated method to assemble 12 optical fibers to a silicon photonics chip. (Source: IBM, Tymon Barwicz et al.)

GobalFoundries has now transferred its monolithic process from 200mm to 300mm-diameter silicon wafers, to achieve both cost-reduction and improved device performance. The 300mm fab lines feature higher-N.A. immersion lithography tools which provide better overlay and line width roughness (LWR). Because the of the extreme sensitivity of optical coupling to the physical geometry of light-guides, improving the patterning fidelity by nanometers can reduce transmission losses by 3X.


Innovations at 7nm to Keep Moore’s Law Alive

Thursday, January 19th, 2017


By Dave Lammers, Contributing Editor

Despite fears that Moore’s Law improvements are imperiled, the innovations set to come in at the 7nm node this year and next may disprove the naysayers. EUV lithography is likely to gain a toehold at the 7nm node, competing with multi-patterning and, if all goes well, shortening manufacturing cycles. Cobalt may replace tungsten in an effort to reduce resistance-induced delays at the contacts, a major challenge with finFET transistors, experts said.

While the industry did see a slowdown in Moore’s Law cost reductions when double patterning became necessary several years ago, Scotten Jones, who runs a semiconductor consultancy focused on cost analysis, said Intel and the leading foundries are back on track in terms of node-to-node cost improvements.

Speaking at the recent SEMI Industry Strategy Symposium (ISS), Jones said his cost modeling backs up claims made by Intel, GlobalFoundries, and others that their leading-edge processes deliver on die costs. Cost improvements stalled at TSMC for the16nm node due to multi-patterning, Jones said. “That pause at TSMC fooled a lot of people. The reality now may surprise those people who said Moore’s Law was dead. I don’t believe that, and many technologists don’t believe that either,” he said.

As Intel has adopted a roughly 2.5-year cadence for its more-aggressive node scaling, Jones said “the foundries are now neck and neck with Intel on density.” Intel has reached best-ever yield levels with its finFET-based process nodes, and the foundries also report reaching similar yield levels for their FinFET processes. “It is hard, working up the learning curve, but these companies have shown we can get there,” he said.

IC Knowledge cost models show the chip industry is succeeding in scaling density and costs. (Source: Scotten Jones presentation at 2017 SEMI ISS)

TSMC, spurred by its contract with Apple to supply the main iPhone processors, is expected to be first to ship its 7nm products late this year, though its design rules (contacted poly pitch and minimum metal pitch) are somewhat close to Intel’s 10nm node.

While TSMC and GlobalFoundries are expected to start 7nm production using double and quadruple patterning, they may bring in EUV lithography later. TSMC has said publicly it plans to exercise EUV in parallel with 193i manufacturing for the 7nm node. Samsung has put its stake in the ground to use EUV rather than quadruple patterning in 2018 for critical layers of its 7nm process. Jones, president of IC Knowledge LLC, said Intel will have the most aggressive CPP and MPP pitches for its 7nm technology, and is likely to use EUV in 2019-2020 to push its metal pitches to the minimum possible with EUV scanners.

EUV progress at imec

In an interview at the 62nd International Electron Devices Meeting (IEDM) in San Francisco in early December, An Steegen, the senior vice president of process technology at Imec (Leuven, Belgium), said Imec researchers are using an ASML NXE 3300B scanner with 0.3 NA optics and an 80-Watt power supply to pattern about 50 wafers per hour.

“The stability on the tool, the up time, has improved quite a lot, to 55 percent. In the best weeks we go well above 70 percent. That is where we are at today. The next step is a 125-Watt power supply, which should start rolling out in the field, and then 250 Watts.”

Steegen said progress is being made in metal-containing EUV resists, and in development of pellicles “which can withstand hydrogen in the chamber.”

If those challenges can be met, EUV would enable single patterning for vias and several metal layers in the middle of the line (MOL), using cut masks to print the metal line ends. “For six or seven thin wires and vias, at the full (7nm node) 32nm pitch, you can do it with a single exposure by going to EUV. The capability is there,” Steegen said.

TSMC’s 7nm development manager, S.Y. Wu, speaking at IEDM, said quadruple patterning and etch (4P4E) will be required for critical layers until EUV reaches sufficient maturity. “EUV is under development (at TSMC), and we will use 7nm as the test vehicle.”

Huiming Bu was peppered with questions following a presentation of the IBM Alliance 7nm technology at IEDM.

Huiming Bu, who presented the IBM Alliance 7nm paper at IEDM, said “EUV delivers significant depth of field (DoF) improvement” compared with the self-aligned quadruple (SAQP) required for the metal lines with immersion scanners.

A main advantage for EUV compared with multi-patterning is that designs would spend fewer days in the fabs. Speaking at ISS, Gary Patton, the chief technology officer at GlobalFoundries, said EUV could result in 30-day reductions in fab cycle times, compared with multiple patterning with 193nm immersion scanners, based on 1.5 days of cycle time per mask layer.

Moreover, EUV patterns would produce less variation in electrical performance and enable tighter process parameters, Patton said.

Since designers have become accustomed to using several colors to identify multi-patterning layers for the 14nm node, the use of double and quadruple patterning at the 7nm node would not present extraordinary design challenges. Moving from multi-patterning to EUV will be largely transparent to design teams as foundries move from multi-patterning to EUV for critical layers.

Interconnect resistance challenges

As interconnects scale and become more narrow, signals can slow down as electrons get caught up in the metal grain boundaries. Jones estimates that as much as 85 percent of parasitic capacitance is in the contacts.

For the main interconnects, nearly two decades ago, the industry began a switch from aluminum to copper. Tungsten has been used for the contacts, vias, and other metal lines near the transistor, partly out of concerns that copper atoms would “poison” the nearby transistors.

Tungsten worked well, partly because the bi-level liner – tantalum nitride at the interface with the inter-level dielectric (ILD) and tantalum at the metal lines – was successful at protecting against electromigration. The TaN-Ta liner is needed because the fluorine-based CVD processes can attack the silicon. For tungsten contacts, Ti serves to getter oxygen, and TiN – which has high resistance — serves as an oxygen and fluorine barrier.

However, as contacts and MOL lines shrunk, the thickness of the liner began to equal the tungsten metal thicknesses.

Dan Edelstein, an IBM fellow who led development of IBM’s industry-leading copper interconnect process, said a “pinch point” has developed for FinFETs at the point where contacts meet the middle-of-the-line (MOL) interconnects.

“With cobalt, there is no fluorine in the deposition process. There is a little bit of barrier, which can be either electroplated or deposited by CVD, and which can be polished by CMP. Cobalt is fairly inert; it is a known fab-friendly metal,” Edelstein said, due to its longstanding use as a silicide material.

As the industry evaluated cobalt, Edelstein said researchers have found that cobalt “doesn’t present a risk to the device. People have been dropping it in, and while there are still some bugs that need to be worked out, it is not that hard to do. And it gives a big change in performance,” he said.

Annealing advantages to Cobalt

Contacts are a “pinch point” and the industry may switch to cobalt (Source: Applied Materials)

An Applied Materials senior director, Mike Chudzik, writing on the company’s blog, said the annealing step during contact formation also favors cobalt: “It’s not just the deposition step for the bulk fill involved – there is annealing as well. Co has a higher thermal budget making it possible to anneal, which provides a superior, less granular fill with no seams and thus lowers overall resistance and improves yield,” Chudzik explained.

Increasing the volume of material in the contact and getting more current through is critical at the 7nm node. “Pretty much every chipmaker is working aggressively to alleviate this issue. They understand if it’s not resolved then it won’t matter what else is done with the device to try and boost performance,” Chudzik said.

Prof. Koike strikes again

Innovations underway at a Japanese university aim to provide a liner between the cobalt contact fill material and the adjacent materials. At a Sunday short course preceding the IEDM, Reza Arghavani of Lam Research said that by creating an alloy of cobalt and approximately 10 percent titanium, “magical things happen” at the interfaces for the contact, M0 and M1 layers.

The idea for adding titanium arose from Prof. Junichi Koike at Tohoku University, the materials scientist who earlier developed a manganese-copper solution for improved copper interconnects. For contacts and MOL, the Co-Ti liner prevents diffusion into the spacer oxide, Arghavani said. “There is no (resistance) penalty for the liner, and it is thermally stable, up to 400 to 500 degrees C. It is a very promising material, and we are working on it. W (tungsten) is being pushed as far as it can go, but cobalt is being actively pursued,” he said.

Stressor changes ahead

Presentations at the 2016 IEDM by the IBM Alliance (IBM, GlobalFoundries, and Samsung) described the use of a stress relaxed buffer (SRB) layer to induce stress, but that technique requires solutions for the defects introduced in the silicon layer above it. As a result of that learning process, SRB stress techniques may not come into the industry until the 5 nm node, or a second-generation 7nm node.

Technology analyst Dick James, based in Ottawa, said over the past decade companies have pushed silicon-germanium stressors for the PFET transistors about as far as practical.

“The stress mechanisms have changed since Intel started using SiGe at the 90nm node. Now, companies are a bit mysterious, and nobody is saying what they are doing. They can’t do tensile nitride anymore at the NFET; there is precious little room to put linear stress into the channel,” he said.

The SRB technique, James said, is “viable, but it depends on controlling the defects.” He noted that Samsung researchers presented work on defects at the IEDM in December. “That was clearly a research paper, and adding an SRB in production volumes is different than doing it in an R&D lab.”

James noted that scaling by itself helps maintain stress levels, even as the space for the stressor atoms becomes smaller. “If companies shorten the gate length and keep the same stress as before, the stress per nanometer at least maintains itself.”

Huiming Bu, the IBM researcher, was optimistic, saying that the IBM Alliance work succeeded at adding both compressive and tensile strain. The SRB/SSRW approach used by the IBM Alliance was “able to preserve a majority – 75 percent – of the stress on the substrate.”

Jones, the IC Knowledge analyst, said another area of intense interest in research is high-mobility channels, including the use of SiGe channel materials in the PMOS FinFETS.

He also noted that for the NMOS finFETs, “introducing tensile stress in fins is very challenging, with lots of integration issues.” Jones said using an SRB layer is a promising path, but added: “My point here is: Will it be implemented at 7 nm? My guess is no.”

Putting it in a package

Steegen said innovation is increasingly being done by the system vendors, as they figure out how to combine different ICs in new types of packages that improve overall performance.

System companies, faced with rising costs for leading-edge silicon, are figuring out “how to add functionality, by using packaging, SOC partitioning and then putting them together in the package to deliver the logic, cache, and IOs with the right tradeoffs,” she said.

Mentor Graphics Joins GLOBALFOUNDRIES FDXcelerator Partner Program

Thursday, December 22nd, 2016

Mentor Graphics Corp. (NASDAQ: MENT) today announced that it has joined GLOBALFOUNDRIES’ FDXcelerator Partner Program. FDXcelerator program partners support customers of GLOBALFOUNDRIES FDX™ technologies by providing a variety of design solutions, including approved design methodology, IP development expertise, hardware/software system integration expertise, and other critical software, services, and support. They participate in FDXcelerator Partner Program events, and receive early access to the GLOBALFOUNDRIES FDX roadmap and associated technology offerings.

“Mentor Graphics is proud to have expanded our long-term relationship with GLOBALFOUNDRIES to include the FDXcelerator Partner Program,” said Joe Sawicki, vice-president and general manager of the Design-to-Silicon division at Mentor Graphics. “We look forward to delivering an enhanced set of solutions to mutual customers in support of GLOBALFOUNDRIES FDX offerings that will enable the development of high quality low-power designs based upon FD-SOI technology.”

Mentor Graphics offerings participating in the FDXcelerator program include:

  • Multiple design implementation solutions from Digital IC Design, including the Oasys-RTL™ floorplanning and synthesis platform and Nitro-SoC™ next-generation place and route platform.
  • The Calibre® platform, including the Calibre DFM tool suite, the most comprehensive set of IC design verification tools in the EDA industry. Calibre tools will be designated as the sign-off tools for FDX across all GLOBALFOUNDRIES design creation flows.
  • The Analog FastSPICE (AFS)™ Platform, the fastest, most accurate, and highest capacity simulation for nanometer-scale circuits, and the Eldo® Platform, the most advanced circuit verification for analog-centric circuits. Collaboration with GLOBALFOUNDRIES includes device and circuit level certification for 22FDX, and support of reference flows for 22FDX.
  • The Tessent® product suite of comprehensive silicon test and yield analysis solutions includes a full design for test reference flow for 22FDX designs, and provides the industry’s highest test quality, lowest test cost, and fastest time to root cause of test failures.

“We are very pleased that Mentor Graphics has joined our FDXcelerator Partner Program,” said Alain Mutricy, senior vice president of product management at GLOBALFOUNDRIES. “The combination of Mentor’s EDA offerings and our FDX technologies provide customers with the solutions that will enable success in delivering products for today’s highly competitive IC markets.”

MRAM Takes Center Stage at IEDM 2016

Monday, December 12th, 2016


By Dave Lammers, Contributing Editor

The IEDM 2016 conference, held in early December in San Francisco, was somewhat of a coming-out party for magneto-resistive memory (MRAM). The MRAM presentations at IEDM were complemented by a special MRAM-focused poster session – organized by the IEEE Magnetics Society in cooperation with the IEEE Electron Devices Society (EDS) – with 33 posters and a lively crowd.

And in the opening keynote speech of the 62nd International Electron Devices Meeting, Seok-hee Lee, executive vice president at SK Hynix (Seoul), set the stage by saying that the race is on between DRAM and emerging memories such as MRAM. “Originally, people thought that DRAM scaling would stop. Then engineers in the DRAM and NAND worlds worked hard and pushed out the end further in the future,” he said.

While cautioning that MRAM bit cells are larger than in DRAM and thus more more costly, Lee said MRAM has “very strong potential in embedded memory.”

SK Hynix is not the only company with a full-blown MRAM development effort underway. Samsung, which earlier bought MRAM startup Grandis and which has a materials-related research relationship with IBM, attracted a standing-room-only crowd to its MRAM paper at IEDM. TSMC is working with TDK on its program, and Sony is using 300mm wafers to build high-performance MRAMs for startup Avalanche Technology.

And one knowledgeable source said “the biggest processor company also has purchased a lot of equipment” for its MRAM development effort.

Dave Eggleston, vice president of emerging memory at GlobalFoundries, said he believes GlobalFoundries is the furthest along on the MRAM optimization curve, partly due to its technology and manufacturing partnership with Everspin Technologies (Chandler, Ariz.). Everspin has been working on MRAM for more than 20 years, and has shipped nearly 60 million discrete MRAMs, largely to the cache buffering and industrial markets.

GlobalFoundries has announced plans to use embedded STT-MRAM in its 22FDX platform, which uses fully-depleted SOI technology, as early as 2018.

Future versions of MRAM– such as spin orbit torque (SOT) MRAM and Voltage Controlled MRAM — could compete with SRAM and DRAM. Analysts said today’s spin-transfer torque STT-MRAM – referring to the torque that arises from the transfer of electron spins to the free magnetic layer — is vying for commercial adoption as ever-faster processors need higher performance memory subsystems.

STT-MRAM is fast enough to fit in as a new memory layer below the processor and the SRAM-based L1/L2 cache layers, and above DRAM and storage-level NAND flash layers, said Gary Bronner, vice president of research at Rambus Inc.

With good data retention and speed, and medium density, MRAM “may have advantages in the lower-level caches” of systems which have large amounts of on-chip SRAM, Bronner said, due in part to MRAM’s smaller cell size than six-transistor SRAM. While DRAM in the sub-20nm nodes faces cost issues as its moves to more complex capacitor structures, Bronner said that “thus far STT-MRAM) is not cheaper than DRAM.”

IBM researchers, which pioneered the spin-transfer torque approach to MRAM, are working on a high-performance MRAM technology which could be used in servers.

As of now, MRAM density is limited largely by the size of the transistors required to drive sufficient current to the magnetic tunnel junction (MTJ) to flip its magnetic orientation. Dan Edelstein, an IBM fellow working on MRAM development at IBM Research, said “it is a tall order for MRAM to replace DRAM. But MRAM could be used in system-level memory architectures and as an embedded memory technology.”

PVD and etch challenges

Edelstein, who was a key figure in developing copper interconnects at IBM some twenty years ago, said MRAM only requires a few extra mask layers to be integrated into the BEOL in logic. But there remain major challenges in improving the throughput of the PVD deposition steps required to deposit the complex material stack and to control the interfacial layers.

The PVD steps must deposit approximately 30 layers and control them to Angstrom-level precision. Deposition must occur under very low base pressure, and in oxygen- and water-vapor free environments. While tool vendors are working on productization of 300mm MRAM deposition tools, Edelstein said keeping particles under control and minimizing the maintenance and chamber cleaning are all challenging.

Etching the complex materials stack is even harder. Chemical RIE is not practical for MRAMs at this point, and using ion beam etching (IBE) presents challenges in terms of avoiding re-deposition of material sputtered off during the IBE etch steps for the high-aspect-ratio MTJs.

For the tool vendors, MRAMs present challenges as companies go from R&D to high-volume manufacturing, Edelstein said.

A Samsung MRAM researcher, Y.J. Song, briefly described IBE challenges during an IEDM presentation describing an embedded STT-MRAM with a respectable 8-Mbit density and a cell size of .0364 sq. micron. “We worked to optimize the contact etching,” using IBE etch during the patterning steps, he said. The short fail rate was reduced, while keeping the processing temperature at less than 350°C, Song said.

Samsung embedded an STT-MRAM module in the copper back end of the line (BEOL) of a 28nm logic process. (Source: Samsung presentation at IEDM 2016).

Many of the presentations at IEDM described improvements in key parameters, such as the tunnel magnetic resistance (TMR), cell size, data retention, and read error rates at high temperatures or low operating voltages.

An SK Hynix presentation described a 4-Gbit STT-MRAM optimized as a stand-alone, high-density memory. “There still are reliability issues for high-density MRAM memory,” said SK Hynix’s S.-W. Chung. The industry needs to boost the TMR “as high as possible” and work on improving the “not sufficiently long” retention times.

At high temperatures, error rates tend to rise, a concern in certain applications. And since devices are subjected to brief periods of high temperatures during reflow soldering, that issue must be dealt with as well, detailed by a Bosch presentation at IEDM.

Cleans and encapsulation important

Gouri Sankar Kar, who is coordinating the MRAM research program at the Imec consortium (Leuven, Belgium), said one challenge is to reduce the cell size and pitch without damaging the magnetic properties of the magnetic tunnel junction. For the 28nm logic node, embedded MRAM would be in the range of a 200nm pitch and 45nm critical dimensions (CDs). At the IEDM poster session, Imec presented an 8nm cell size STT-MRAM that could intersect the 10nm logic node, with the MRAM pitch in the 100nm range. GlobalFoundries, Micron, Qualcomm, Sony and TSMC are among the participants in the Imec MRAM effort.

Kar said in addition to the etch challenges, post-patterning treatment and the encapsulation liner can have a major impact on MTJ materials selection. “Some metals can be cleaned immediately, and some not. For the materials stack, patterning (litho and etch) and clean optimization are crucial.”

“Chemical etch (RIE) is not really possible at this stage. All the tool vendors are working on physical sputter etch (IBE) where they can limit damage. But I would say all the major tool vendors at this point have good tools,” Kar said.

To reach volume manufacturing, tool vendors need to improve the tool up-time and reduce the maintenance cycles. There is a “tail bits” relationship between the rate of bit failures and the health of the chambers that still needs improvement. “The cleanup steps after etching are very, very critical” to the overall effort to improving the cost effectiveness of MRAM, Kar said, adding that he is “very positive” about the future of MRAM technology.

A complete flow at AMAT

Applied Materials is among the equipment companies participating in the Imec program, with TEL and Canon-Anelva also heavily involved. Beyond that, Applied has developed a complete MRAM manufacturing flow at the company’s Dan Maydan Center in Santa Clara, and presented its cooperative work with Qualcomm on MRAM development at IEDM.

In an interview, Er-Xuan Ping, the Applied Materials managing director in charge of memory and materials technologies, said about 20 different layers, including about ten different materials, must be deposited to create the magnetic tunnel junctions. As recently as a few years ago, throughput of this materials stack was “extremely slow,” he said. But now Applied’s multi-cathode PVD tool, specially developed for MRAM deposition, can deposit 5 Angstrom films in just a few seconds. Throughput is approaching 20 wafers per hour.

Applied Materials “basically created a brand-new PVD chamber” for STT-MRAM, and he said the tool has a new e-chuck, optimized chamber walls and a multi-cathode design.

The MRAM-optimized PVD tool does not have an official name yet, and Ping said he refers to it as multi-cathode PVD. With MRAM requiring deposition of so many different metals and other materials, the Applied tool does not require the wafer to be moved in and out, increasing efficiency. The shape and structure of the chamber wall, Ping said, allow absorption of downstream plasma material so that it doesn’t come back as particles.

For etch, Applied has worked to create etching processes that result in very low bit failure rates, but at relatively relaxed pitches in the 130-200nm range. “We have developed new etch technologies so we don’t think etch will be a limiting factor. But etch is still challenging, especially for cells with 50nm and smaller cell sizes. We are still in unknown territory there,” said Ping.

Jürgen Langer, R&D manager at Singulus Technology (Frankfurt, Germany), said Singulus has developed a production-optimized PVD tool which can deposit “30 material layers in the Angstrom range. We can get 20 wafers per hour throughputs, so I would say this is not a beta tool, it is for production.”

Jürgen Langer, R&D manager, presented a poster on MRAM deposition from Singulus Technology (Frankfurt, Germany).

Where does it fit?

Once the production challenges of making MRAM are ironed out, the question remains: Where will MRAM fit in the systems of tomorrow?

Tom Coughlin, a data storage consultant based in Atascadero, Calif., said embedded MRAM “could have a very important effect for industrial and consumer devices. MRAM could be part of the memory cache layers, providing power advantages over other non-volatile devices.” And with its ability to power on and power off without expending energy, MRAM could reduce overall power consumption in smart phones, cutting in to the SRAM and NOR sectors.

“MRAM definitely has a niche, replacing some DRAM and SRAM. It may replace NOR. Flash will continue for mass storage, and then there is the 3D Crosspoint from Intel. I do believe MRAM has a solid basis for being part of that menagerie. We are almost in a Cambrian explosion in memory these days,” Coughlin said.

Has SOI’s Turn Come Around Again?

Monday, October 10th, 2016


By David Lammers, Contributing Editor

When analyst Linley Gwennap is asked about the chances that fully-depleted silicon-on-insulator (FD-SOI) technology will make it in the marketplace, he gives a short history lesson.

First, he makes clear that the discussion is not about “the older SOI,” – the partially depleted SOI that required designers to deal with the so-called “kink effect.” The FD-SOI being offered by STMicroelectronics and Samsung at 28nm design rules, and by GlobalFoundries at 22nm and 12nm, is a different animal: a fully depleted channel, new IP libraries, and no kink effect.

Bulk planar CMOS transistor scaling came to an end at 28nm, and leading-edge companies such as Intel, TSMC, Samsung, and GlobalFoundries moved into the finFET realm for performance-driven products, said Gwennap, founder of The Linley Group (Mountain View, Calif.) and publisher of The Microprocessor Report, said,

While FD-SOI at the 28nm node was offered by STMicrelectronics, with Samsung coming in as a second source, Gwennap said 28nm FD-SOI was not differentiated enough from 28nm bulk CMOS to justify the extra design and wafer costs. “When STMicro came out with 28 FD, it was more expensive than bulk CMOS, so the value proposition was not that great.”

NXP uses 28nm FD-SOI for its iMX 7 and iMX 8 processors, but relatively few other companies did 28nm FD-SOI designs. That may change as 22nm FD-SOI offers a boost in transistor density, and a roadmap to tighter design rules.

“For planar CMOS, Moore’s Law came to a dead end at 28nm. Some companies have looked at finFETs and decided that the cost barrier is just too high. They don’t have anywhere to go; for a few years now those companies have been at 28nm, they can’t justify the move on to finFETs, and they need to figure out how they can offer something new to their customers. For those companies, taking a risk on FD-SOI is starting to look like a good idea,” he said.

A cautious view

Joanne Itow, foundry analyst at Semico Research (Phoenix), also has been observing the ups and downs of SOI technology over the last two decades. The end of the early heyday, marked by PD-SOI-based products from IBM, Advanced Micro Devices, Freescale Semiconductor, and several game system vendors, has led Itow to take a cautious, Show-Me attitude.

“The SOI proponents always said, ‘this is the breakout node,’ but then it didn’t happen. Now, they are saying the Fmax has better results than finFETs, and while we do see some promising results, I’m not sure everybody knows what to do with it. And there may be bottlenecks,” such as the design tools and IP cores.

Itow said she has talked to more companies that are looking at FD-SOI, and some of them have teams designing products. “So we are seeing more serious activity than before,” Itow said. “I don’t see it being the main Qualcomm process for high-volume products like the applications processors in smartphones. But I do see it being looked at for IoT applications that will come on line in a couple of years. And these things always seem to take longer than you think,” she said.

Sony Corp. has publicly discussed a GPS IC based on 28nm FD-SOI that is being deployed in a smartwatch sold by Huami, a Chinese brand, which is touting the long battery life of the watch when the GPS function is turned on.

GlobalFoundries claims it has more than 50 companies in various stages of development on its 22FDX process, which enters risk production early next year, and the company plans a 12nm FDX offering in several years.

IP libraries put together

The availability of design libraries – both foundation IP and complex cores – is an issue facing FD-SOI. Gwennap said GlobalFoundries has worked with EDA partners, and invested in an IP development company, Invecas, to develop an IP library for its FDX technology. “Even though GlobalFoundries is basically starting from scratch in terms of putting together an IP library, it doesn’t take that long to put together the basic IP, such as the interface cells, that their customers need.

“There is definitely going to be an unusual thing that probably will not be in the existing library, something that either GlobalFoundries or the customers will have to put together. Over time, I believe that the IP portfolio will get built out,” Gwennap said.

The salaries paid to design engineers in Asia tend to be less than half of what U.S.-based designers are paid, he noted. That may open up companies “with a lower cost engineering team” in India, China, Taiwan, and elsewhere to “go off in a different direction” and experiment with FD-SOI, Gwennap said.

Philippe Flatresses, a design architect at STMicro, said with the existing FDSOI ecosystem it is possible to design a complete SoC, including processor cores from ARM Ltd., high speed interfaces, USB, MIPI, memory controllers, and other IP from third-party providers including Synopsys and Cadence. Looking at the FD-SOI roadmap, several technology derivatives are under development to address the RF, ultra-low voltage, and other markets. Flatresses said there is a need to extend the IP ecosystem in those areas.

Wafer costs not a big factor

There was a time when the approximately $500 cost for an SOI wafer from Soitec (Grenoble, France) tipped the scales away from SOI technology for some cost-sensitive applications. Gwennap said when a fully processed 28nm planar CMOS wafer cost about $3,000 from a major foundry, that $500 SOI wafer cost presented a stumbling block to some companies considering FD-SOI.

Now, however, a fully-processed finFET wafer costs $7,000 or more from the major foundries, Gwennap said, and the cost of the SOI wafer is a much smaller fraction of the total cost equation. When companies compare planar FD-SOI to finFETs, that $500 wafer cost, Gwennap said, “just isn’t as important as it used to be. And some of the other advantages in terms of cost savings or power savings are pretty attractive in markets where cost is important, such as consumer and IoT products. They present a good chance to get some key design wins.”

Soitec claims it can ramp up to 1.5 million FD-SOI wafers a year with its existing facility in 18 months, and has the ability to expand to 3 million wafers if market demand expands.

Jamie Schaeffer, the FDX program manager at GlobalFoundries, acknowledges that the SOI wafers are three to four times more expensive than bulk silicon wafers. Schaeffer said a more important cost factor is in the mask set. A 22FDX chip with eight metal layers can be constructed with “just 39 mask layers, compared with 60 for a finFET design at comparable performance levels.” And no double patterning is required for the 22FDX transistors.

Technology advantages claimed

Soitec senior fellow Bich-Yen Nguyen, who spent much of her career at Freescale Semiconductor in technology development, claims several technical advantages for FD-SOI.

FD-SOI has a high transconductance-to-drain current ratio, is superior in terms of the short channel effect, and has a lower fringing and effective capacitance and lower gate resistance, due partly to a gate-first process approach to the high-k/metal gate steps, Nguyen said.

Back and forward biasing is another unique feature of FD-SOI. “When you apply body-bias, the fT and fmax curves shift to a lower Vt.  This is an additional benefit allowing the RF designer to achieve higher fT and fmax at much lower gate voltage (Vg) over a wider Vg range.  That is a huge benefit for the RF designer,” she said. Figure 1 illustrates the unique benefit of back-bias.

Figure 1. The unique benefit of back-bias is illustrated. Source: GlobalFoundries.

“To get the full benefit of body bias for power savings or performance improvement, the design teams must consider this feature from the very beginning of product development,” she said. While biasing does not require specific EDA tools, and can be achieve with an extended library characterization, design architects must define the best corners for body bias in order to gain in performance and power. And design teams must implement “the right set of IPs to manage body biasing,” such as a BB generator, BB monitors, and during testing, a trimming methodology.

Nguyen acknowledged that finFETs have drive-current advantages. But compared with bulk CMOS, FD-SOI has superior electrostatics, which enables scaling of analog/RF devices while maintaining a high transistor gain. And drive current increases as gate length is scaled, she said.

For 14/16 nm finFETs, Nguyen said the gate length is in the 25-30 nm range. The 22FDX transistors have a gate length in the 20nm range. “The very short gate length results in a small gate capacitance, and total lower gate resistance,” she said.

For fringing capacitance, the most conservative number is that 22nm FD-SOI is 30 percent lower than leading finFETs, though she said “finFETs have made a lot of progress in this area.”

Analog advantages

It is in the analog and RF areas that FD-SOI offers the most significant advantages, Nguyen said. The fT and fMAX of 350 and 300 GHz, respectively, have been demonstrated by GlobalFoundries for its 22nm FD-SOI technology. For analog devices, she claimed that FD-SOI offers better transistor mismatch, high intrinsic device gain (Gm/Gds ratio), low noise, and flexibility in Vt tuning. Figure 2 shows how 22FDX outperforms finFETs for fT/fMax.

Figure 2. 22FDX outperforms finFETs for fT/fMax. Source: GlobalFoundries.

“FDSOI is the only device architecture that meets all those requirements. Bulk planar CMOS suffers from large transistor mismatch due to random dopant fluctuation and low device gain due to poor electrostatics. FinFET technology improves on electrostatics but it lacks the back bias capability.”

The undoped channel takes away the random doping effect of a partially depleted (doped) channel, reducing variation by 50-60 percent.

Analog designers using FD-SOI, she said, have “the ability to tune the Vt by back-bias to compensate for process mismatch or drift, and to offer virtually any Vt desired. Near-zero Vt can also be achieved in FD-SOI, which enables low voltage analog design for low power consumption applications.”

“If you believe the future is about mobility, about more communications and low power consumption and cost sensitive IoT chips where analog and RF is about 50 percent of the chip, then FD-SOI has a good future.

“No single solution can fit all. The key is to build up the ecosystem, and with time, we are pushing that,” she said.

IoT Demands Part 2: Test and Packaging

Friday, April 15th, 2016

By Ed Korczynski, Senior Technical Editor, Solid State Technology, SemiMD

The Internet-of-Things (IoT) adds new sensing and communications to improve the functionality of all manner of things in the world. Solid-state and semiconducting materials for new integrated circuits (IC) intended for ubiquitous IoT applications will have to be extremely small and low-cost. To understand the state of technology preparedness to meet the anticipated needs of the different application spaces, experts from GLOBALFOUNDRIES, Cadence, Mentor Graphics and Presto Engineering gave detailed answers to questions about IoT chip needs in EDA and fab nodes, as published in “IoT Demands:  EDA and Fab Nodes.” We continue with the conversation below.

Korczynski: For test of IoT devices which may use ultra-low threshold voltage transistors, what changes are needed compared to logic test of a typical “low-power” chip?

Steve Carlson, product management group director, Cadence

Susceptibility to process corners and operating conditions becomes heightened at near-threshold voltage levels. This translates into either more conservative design sign-off criteria, or the need for higher levels of manufacturing screening/tests. Either way, it has an impact on cost, be it hidden by over-design, or overtly through more costly qualification and test processes.

Jon Lanson, vice president worldwide sales & marketing, Presto Engineering

We need to make sure that the testability has also been designed to be functional structurally in this mode. In addition, sub-threshold voltage operation must account for non-linear transistor characteristics and the strong impact of local process variation, for which the conventional testability arsenal is still very poor. Automotive screening used low voltage operation (VLV) to detect latent defects, but at very low voltage close to the transistor threshold, digital becomes analog, and therefore if the usual concept still works for defect detection, functional test and @speed tests require additional expertise to be both meaningful and efficient from a test coverage perspective.

Korczynski:  Do we have sufficient specifications within “5G” to handle IoT device interoperability for all market segments?

Rajeev Rajan, Vice President of Internet of Things (IoT) at GLOBALFOUNDRIES

The estimated timeline for standardization availability of 5G is around 2020. 5G is being designed keeping three classes of applications in mind:  Enhanced Mobile Broadband, Massive IoT, and Mission-Critical Control. Specifically for IoT, the focus is on efficient, low-cost communication with deep coverage. We will start to see early 5G technologies start to appear around 2018, and device connectivity,

interoperability and marshaling the data they generate that can apply to multiple IoT sub-segments and markets is still very much in development.

Korczynski:  Will the 1st-generation of IoT devices likely include wide varieties of solution for different market-segments such as industrial vs. retail vs. consumer, or will most device use similar form-factors and underlying technologies?

Rajeev Rajan, Vice President of Internet of Things (IoT) at GLOBALFOUNDRIES

If we use CES 2016 as a showcase, we are seeing IoT “Things” that are becoming use-case or application-centric as they apply to specific sub-segments such as Connected Home, Automotive, Medical, Security, etc. There is definitely more variety on the consumer front vs. industrial. Vendors / OEMs / System houses are differentiating at the user-interface design and form-factor levels while the “under-the-hood” IC capabilities and component technologies that provide the atomic intelligence are fairly common. ​

Steve Carlson, product management group director, Cadence

Right now it seems like everyone is swinging for the fence. Everyone wants the home-run product that will reach a billion devices sold. Generality generally leads to sub-optimality, so a single device usually fails to meet the needs and expectations of many. Devices that are optimized for more specific use cases and elements of purchasing criteria will win out. The question of interface is an interesting one.

Korczynski:  Will there be different product life-cycles for different IoT market-segments, such as 1-3 years for consumer but 5-10 years for industrial?

Rajeev Rajan, Vice President of Internet of Things (IoT) at GLOBALFOUNDRIES

That certainly seems to be the case. According to Gartner’s market analysis for IoT, Consumer is expected to grow at a faster pace in terms of units compared to Enterprise, while Enterprise is expected to lead in revenue. Also the churn-cycle in Consumer is higher / faster compared to Enterprise. Today’s wearables or smart-phones are good reference examples. This will however vary by the type of “Thing” and sub-segment. For example, you expect to have your smart refrigerator for a longer time period compared to smart clothing or eyewear. As ASPs of the “Things”come down over time and new classes of products such as disposables hit the market, we can expect even larger volumes.​

Jon Lanson, vice president worldwide sales & marketing, Presto Engineering

The market segments continue to be driven by the same use cases. In consumer wearables, short cycles are linked to fashion trends and rapid obsolescence, where consumer home use has longer cycles closer to industrial market requirements. We believe that the lifecycle norms will hold true for IoT devices.

Korczynski:  For the IoT application of infrastructure monitoring (e.g. bridges, pipelines, etc.) long-term (10-20 year) reliability will be essential, while consumer applications may be best served by 3-5 year reliability devices which cost less; how well can we quantify the trade-off between cost and chip reliability?

Steve Carlson, product management group director, Cadence

Conceptually we know very well how to make devices more reliable. We can lower current densities with bigger wires, we can run at cooler temperatures, and so on.  The difficulty is always in finding optimality for a given criterion across the, for practical purposes, infinite tradeoffs to be made.

Korczynski:  Why is the talk of IoT not just another “Dot Com” hype cycle?

Rajeev Rajan, Vice President of Internet of Things (IoT) at GLOBALFOUNDRIES

​​I participated in a panel at SEMICON China in Shanghai last month that discussed a similar question. If we think of IoT as a “brand new thing” (no pun intended), then we can think of it as hype. However if we look at the IoT as as set of use-cases that can take advantage of an evolution of Machine-to-Machine (M2M) going towards broader connectivity, huge amounts of data generated and exchanged, and a generational increase in internet and communication network bandwidths (i.e. 5G), then it seems a more down-to-earth technological progression.

Nicolas Williams, product marketing manager, Mentor Graphics

Unlike the Dot Com hype, which was built upon hope and dreams of future solutions that may or may not have been based in reality, IoT is real business. For example, in a 2016 IC Insights report, we see that last year $63.4 billion in revenue was generated for IoT systems and the market is growing at about 20% CAGR. This same report also shows IoT semiconductor sales of over $15 billion in 2015 with a CAGR of 21.1%.

Jon Lanson, vice president worldwide sales & marketing, Presto Engineering

It is the investment needed up front to create sensing agents and an infrastructure for the hardware foundation of the IoT that will lead to big data and ultimately value creation.

Steve Carlson, product management group director, Cadence

There will be plenty of hype cycles for products and product categories along the way. However, the foundational shift of the connection of things is a diode through which civilization will only pass through in one direction.

IoT Demands Part 1: EDA and Fab Nodes

Thursday, April 14th, 2016

The Internet-of-Things (IoT) is expected to add new sensing and communications to improve the functionality of all manner of things in the world:  bridges sensing and reporting when repairs are needed, parts automatically informing where they are in storage and transport, human health monitoring, etc. Solid-state and semiconducting materials for new integrated circuits (IC) intended for ubiquitous IoT applications will have to be assembled at low-cost and small-size in High Volume Manufacturing (HVM). Micro-Electro-Mechanical Systems (MEMS) and other sensors are being combined with Radio-Frequency (RF) ICs in miniaturized packages for the first wave of growth in major sub-markets.

To meet the anticipated needs of the different IoT application spaces, SemiMD asked leading companies within critical industry segments about the state of technology preparedness:


*  Electronic Design Automation (EDA) – Cadence and Mentor Graphics,

*  IC and complex system test – Presto Engineering.

Korczynski:  Today, ICs for IoT applications typically use 45nm/65nm-node which are “Node -3″ (N-3) compared to sub-20nm-node chips in HVM. Five years from now, when the bleeding-edge will use 10nm node technology, will IoT chips still use N-3 of 28nm-node (considered a “long-lived node”) or will 45nm-node remain the likely sweet-spot of price:performance?

Timothy Dry, product marketing manager, GLOBALFOUNDRIES

In 5 years time, there will be a spread of technology solutions addressing low, middle, and high ends of IoT applications. At the low end, IoT end nodes for applications like connected smoke

detectors, security sensors will be at 55, 40nm ULP and ULL for lowest system power, and low cost. These applications will be typically served by MCUs <50DMIPs. Integrated radios (BLE, 802.15.4), security, Power Management Unit (PMU), and eFlash or MRAM will be common features. Connected LED lighting is forecasted to be a high volume IoT application. The LED drivers will use BCD extensions of 130nm—40nm—that can also support the radio and protocol-MCU with Flash.

In the mid-range, applications like smart-meters and fitness/medical monitoring will need systems that have more processing power <300DMIPS. These products will be implemented in 40nm, 28nm and GLOBALFOUNDRIES’ new 22nm FDSOI technology that uses software-controlled body-biasing to tune SoC operation for lowest dynamic power. Multiple wireless (BLE/802.15.4, WiFi, LPWAN) and wired connectivity (Ethernet, PLC) protocols with security will be integrated for gateway products.

High-end products like smart-watches, learning thermostats, home security/monitoring cameras, and drones will require MPU-class IC products (~2000DMIPs) and run high-order operating systems (e.g. Linux, Android). These products will be made in leading-edge nodes starting at 22FDX, 14FF and migrating to 7FF and beyond. Design for lowest dynamic power for longest battery life will be the key driver, and these products typically require human machine Interface (HMI) with animated graphics on a high resolution displays. Connectivity will include BLE, WiFi and cellular with strong security.

Steve Carlson, product management group director, Cadence

We have seen recent announcements of IoT targeted devices at 14nm. The value created by Moore’s Law integration should hold, and with that, there will be inherent advantages to those who leverage next generation process nodes. Still, other product categories may reach functionality saturation points where there is simply no more value obtained by adding more capability. We anticipate that there will be more “live” process nodes than ever in history.

Jon Lanson, vice president worldwide sales & marketing, Presto Engineering

It is fair to say that most IoT devices will be a heterogeneous aggregation of analog functions rather than high power digital processors. Therefore, and by similarity with Bluetooth and RFID devices, 90nm and 65nm will remain the mainstream nodes for many sub-vertical markets, enabling the integration of RF and analog front-end functions with digital gate density. By default, sensors will stay out of the monolithic path for both design and cost reasons. The best answer would be that the IoT ASIC will follow eventually the same scaling as the MCU products, with embedded non-volatile memories, which today is 55-40nm centric and will move to 28nm with industry maturity and volumes.

Korczynski:  If most IoT devices will include some manner of sensor which must be integrated with CMOS logic and memory, then do we need new capabilities in EDA-flows and burn-in/test protocols to ensure meeting time-to-market goals?

Nicolas Williams, product marketing manager, Mentor Graphics

If we define a typical IoT device as a product that contains a MEMS sensor, A/D, digital processing, and a RF-connection to the internet, we can see that the fundamental challenge of IoT design is that teams working on this product need to master the analog, digital, MEMS, and RF domains. Often, these four domains require different experience and knowledge and sometimes design in these domains is accomplished by separate teams. IoT design requires that all four domains are designed and work together, especially if they are going on the same die. Even if the components are targeting separate dice that will be bonded together, they still need to work together during the layout and verification process. Therefore, a unified design flow is required.

Stephen Pateras, product marketing director, Mentor Graphics

Being able to quickly debug and create test patterns for various embedded sensor IP can be addressed with the adoption of the new IEEE 1687 IP plug-and-play standard. If a sensor IP block’s digital interface adheres to the standard, then any vendor-provided data required to initialize or operate the embedded sensor can be easily and quickly mapped to chip pins. Data sequences for multiple sensor IP blocks can also be merged to create optimized sequences that will minimize debug and test times.

Jon Lanson, vice president worldwide sales & marketing, Presto Engineering

From a testing standpoint, widely used ATEs are generally focused on a few purposes, but don’t necessarily cover all elements in a system. We think that IoT devices are likely to require complex testing flows using multiple ATEs to assure adequate coverage. This is likely to prevail for some time as short run volumes characteristic of IoT demands are unlikely to drive ATE suppliers to invest R&D dollars in creating new purpose-built machines.

Korczynski:  For the EDA of IoT devices, can all sensors be modeled as analog inputs within established flows or do we need new modeling capability at the circuit level?

Steve Carlson, product management group director, Cadence

Typically, the interface to the physical world has been partitioned at the electrical boundary. But as more mechanical and electro-mechanical sensors are more deeply integrated, there has been growing value in co-design, co-analysis, and co-optimization. We should see more multi-domain analysis over time.

Nicolas Williams, product marketing manager, Mentor Graphics

Designers of IoT devices that contain MEMS sensors need quality models in order to simulate their behavior under physical conditions such as motion and temperature. Unlike CMOS IC design, there are few standardized MEMS models for system-level simulation. State of the art MEMS modeling requires automatic generation of behavioral models based on the results of Finite Element Analysis (FEA) using reduced-order modeling (ROM). ROM is a numerical methodology that reduces the analysis results to create Verilog-A models for use in AMS simulations for co-simulation of the MEMS device in the context of the IoT system.

What’s the Next-Gen Litho Tech? Maybe All of Them

Thursday, February 25th, 2016

By Jeff Dorsch, Contributing Editor

The annual SPIE Advanced Lithography symposium in San Jose, Calif., hasn’t offered a clear winner in the next-generation lithography race. It’s becoming clearer, however, that 193i immersion and extreme-ultraviolet lithography will co-exist in the future, while directed self-assembly, nanoimprint lithography, and maybe even electron-beam direct-write technology will fit into the picture, too.

At the same time, plasma deposition and etching processes are assuming a greater interdependence with 193i, especially when it comes to multiple patterning, such as self-aligned double patterning, self-aligned quadruple patterning, and self-aligned octuple patterning (yes, there is such a thing!).

“We’ve got to go down to the sub-nanometer level,” Richard Gottscho, Lam Research’s executive vice president of global products, said Monday morning in his plenary presentation at the conference. “We must reduce the variability in multiple patterning,” he added.

Gottscho touted the benefits of atomic level processing in continuing to shrink IC dimensions. Atomic level deposition has been in volume production for a decade or more, he noted, and atomic level etching is emerging as an increasingly useful technology.

When it comes to EUV, “it’s a matter of when, not if,” the Lam executive commented. “EUV will be complementary with 193i.”

Anthony Yen, director of nanopatterning technology in the Infrastructure Division of Taiwan Semiconductor Manufacturing, followed Gottscho in the plenary session. “The fat lady hasn’t sung yet, but she’s on the stage,” he said of EUV.

Harry Levinson, senior director of GlobalFoundries, gave the opening plenary presentation, with the topic of “Evolution in the Concentration of Activities in Lithography.” He was asked after his presentation, “When is the end?” Levinson replied, “We’re definitely not going to get sub-atomic.”

With that limit in mind, dozens of papers were presented this week on what may happen before the semiconductor industry hits the sub-atomic wall.

There were seven conferences within the symposium, on specific subjects, along with a day of classes, an interactive poster session, and a two-day exhibition.

The Alternative Lithographic Technologies conference was heavy on directed self-assembly and nanoimprint lithography papers, while also offering glimpses at patterning with tilted ion implantation and multiphoton laser ablation lithography.

“Patterning is the battleground,” said David Fried, Coventor’s chief technology officer, semiconductor, in an interview at the SPIE conference. He described directed self-assembly as “an enabler for optical lithography.”

Mattan Kamon of Coventor presented a paper on Wednesday afternoon on “Virtual fabrication using directed self-assembly for process optimization in a 14nm DRAM node.”

DSA could be used in conjunction with SAQP or LELELELE, according to Fried. While some lithography experts remain leery or skeptical about using DSA in high-volume manufacturing, the Coventor CTO is a proponent of the technology’s potential.

“Unit process models in DSA are not far-fetched,” he said. “I think they’re pretty close.  The challenges of EUV are well understood. DSA challenges are a little less clear. There’s no ‘one solution fits all’ with DSA.” Fried added, “There are places where DSA can still win.”

Franklin Kalk, executive vice president of technology for Toppan Photomasks, is open to the idea of DSA and imprint lithography joining EUV and immersion in the lithography mix. “It will be some combination,” he said in an interview, while adding, “It’s a dog’s breakfast of technologies. Don’t ever count anything out.”

Richard Wise, Lam’s technical managing director in the company’s Patterning, Global Products Groups CTO Office, said EUV, when ready, will likely be complementary with multipatterning for 7 nanometer.

Self-aligning quadruple patterning, for example, was once considered “insanity” in the industry, yet it is a proven production technology now, he said.

While EUV technology is “very focused on one company,” ASML Holding, there is a consensus at SPIE that EUV’s moment is at hand, Wise said. Intel’s endorsement of the technology and dedication to advancing it speaks volumes of EUV’s potential, he asserted.

“Lam’s always excelled in lot-to-lot control,” an area of significant concern, Wise said, especially with all of this week’s talk about process variability.

What will be the final verdict on the future of lithography technology? Stay tuned.

Optimism Reigns at SPIE Lithography Conference, Despite Challenges

Tuesday, February 23rd, 2016


By Jeff Dorsch, Contributing Editor

Semiconductor manufacturing and design is growing increasingly complicated and just plain hard. Everyone knows that. The bad news is it’s only going to get worse.

Relax, there are many smart people gathered in San Jose, Calif., this week for the SPIE Advanced Lithography Symposium to discuss the challenges and figure out how to surmount them.

The changes required in lithography and related technologies to continue IC scaling promise to be painful and costly. Mitigating the pain and the cost is a common theme at the SPIE conference.

The annual SPIE Advanced Lithography conference is often dominated by discussions on the state of extreme-ultraviolet lithography (EUVL). In presentations on Sunday and Monday, the theme was generally the same as 2015 – EUV is making progress, yet it’s still not ready for high-volume semiconductor manufacturing.

Intel Fellow Mark Phillips said the technology has seen “two years of solid progress,” speaking Sunday at Nikon’s LithoVision 2016 event. He added, “There’s no change in Intel’s position: We’ll use EUV only when it’s ready.”

Anthony Yen of Taiwan Semiconductor Manufacturing covered the 30-year history of EUV development in his Monday morning presentation at the SPIE conference. Asked during the question-and-answer session following the presentation on when the world’s largest silicon foundry will use EUV, Yen stuck to the official company line of implementing EUV in production for the 7-nanometer process node, after some involvement at 10nm.

Seong-Sam Kim of Samsung Electronics also sees EUV realizing its long-aborning potential at 7nm, a node at which “argon fluoride multipatterning will hit the wall.” He touted the 80-watt power source Samsung has achieved with its NXE-3300 scanner from ASML Holding, saying it had maintained that level over more than eight months.

Intel’s Britt Turkot reported 200W source power “has been achieved recently,” and said the tin droplet generator in its ASML scanner has been significantly improved, increasing its typical lifetime by three times. EUV has demonstrated “solid progress,” she said, including ASML’s development of a membrane pellicle for EUV reticles.

While work with the ASML scanner on Intel’s 14nm pilot fab line has been “encouraging,” Turkot said, she added, “We do need to keep the momentum going.” Intel sees EUV entering into volume production with 7nm chips, according to Turkot. “It will be used when it’s ready,” she said.

EUV technology has shown “good progress” in productivity, while its availability and cost considerations have “a long way to go,” Turkot concluded, adding, “We need an actinic solution for the long term.”

An industry consensus has emerged that EUV will be used with ArF 193i immersion lithography in the near future, and this trend is likely to continue for some time, according to executives at the SPIE conference. There may also be wider adoption of directed self-assembly (DSA) and nanoimprint lithography technology, among other alternative lithography technologies.

Mark Phillips of Intel pointed to complementary implementation of EUV and 193i. “We must use EUV carefully,” he said. “We need to replace three-plus 193i masks.” Phillips added, “EUV can’t be applied everywhere affordably. 193i will continue to be used whenever possible.”

Nikon executives touted the capabilities of their new NSR-S631E ArF immersion scanner, introduced just before the SPIE conference. The new scanner can turn out 250 wafers per hour, and can be pushed to 270 wph with certain options, according to Nikon’s Ryoichi Kawaguchi.

Yuichi Shibazaki of Nikon said the company will next year introduce the S63xE scanner, improving on S631E.

For all the challenges of transitioning to 7nm and beyond, executives at SPIE remain optimistic about solving the issues of 193i multipatterning, DSA, and EUV. Harry Levinson of GlobalFoundries said in response to a question, “The ultimate resource is the human mind.”

Cadence Debuts Product for Reducing Test Time, Costs

Tuesday, February 2nd, 2016

By Jeff Dorsch, Contributing Editor

Cadence Design Systems is introducing the Modus Test Solution, a product that it touts as capable of reducing IC testing time and test costs, while improving profit margins for chips.

Modus shares a Tcl scripting and debugging environment with Cadence’s Genus Synthesis Solution, Innovus Implementation Solution, and Tempus Timing Signoff Solution, according to the company.

Its other capabilities include 2D compression, elastic compression, and embedded memory bus support. Modus incorporates automatic test pattern generation, built-in self-test, and design-for-test technologies.

“We’re pretty excited about it,” Paul Cunningham, vice president of research and development at Cadence, says of Modus. The automatic test equipment market is worth about $4 billion a year, yet test technology hasn’t yielded any significant breakthroughs in the 21st century, he asserts.

“Test has been stagnant for the last 15 to 20 years,” he says.

Cadence is trying to work around the challenges of test time and test costs by addressing “actual physical test” and “test logic itself,” Cunningham notes. Just as chip designers are constantly aware of power/performance/area in their projects, Cadence addressed test coverage and chip size in developing Modus, he adds.

ATPG, BIST, and DFT technologies have been around for a long time, and they are regaining substantial interest in the semiconductor industry as system-on-a-chip device designs grow more complex.

“Chip CAGRs are not what they used to be,” Cunningham observes. “Cost and profit are very, very critical. Power/performance/area are really, really critical.”

Chipmakers are constantly looking to “squeeze profit margins out,” and reducing test costs can contribute to that imperative, the Cadence executive says. “There is “real pressure on margins, real pressure on complexity,” he adds.

Cunningham also focuses on the “concept of a single user interface” for Modus and its related design tools. With a common UI, different steps in the chip design, manufacturing, and testing processes can be like “different apps on an iPhone,” he says.

Cadence collected testimonials for Modus from three chip companies.

“Minimizing the cost of test is crucial in high-volume, price-sensitive markets like embedded processing. The Modus Test Solution is showing a 1.7x reduction in digital test time on one of our largest and most complex embedded processor chips without any impact on design closure,” said Roger Peters of Texas Instruments, who is involved in microcontroller silicon development.

Sue Bentlage, director of ASIC design and methodology at GlobalFoundries, said, “The Modus Test Solution demonstrated a 3.6x reduction in test time on a customer networking chip without impacting design routability or fault coverage. This technology definitely reduces production test costs. The evolution of the Modus Test Solution, as well as the Innovus Implementation System, the Tempus Timing Signoff Solution and the Voltus IC Power Integrity Solution, provides a leading edge end-to-end design flow in 14nm and beyond for our worldwide design centers and for our ASIC customers.”

Chris Malkin, baseband IC manager at Sequans Communications, said of Modus, “Test time has a significant impact on semiconductor product costs and production capacity, so reducing test time is important. We have seen the Modus Test Solution achieve a 2x reduction in test time without impacting fault coverage or die size.”

“With the Modus Test Solution, we achieved an impressive 2.6X reduction in compression wirelength and a 2X reduction in scan time. The reduction in compression logic wirelength enabled us to address a key challenge for design closure as we push to smaller process nodes and scale design size,” said Alan Nakamoto, vice president, engineering services at Microsemi Corp.

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