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Design and Manufacturing Technology Development in Future IC Foundries

Tuesday, September 16th, 2014

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By Ed Korczynski, Sr. Technical Editor

Virtual Roundtable provides perspective on the need for greater integration within the “fabless-foundry” ecosystem

Q1:  The fabless-foundry relationship in commercial IC manufacturing was established during an era of fab technology predictability—clear litho roadmaps for smaller and cheaper devices—but the future of fab technology seems unpredictable. The complexity which must be managed by a fabless company has already increased to justify leaders such as Apple or Qualcomm investing in technology R&D with foundries and with EDA- and OEM-companies. With manufacturing process technology integrating more materials with ever smaller nodes, how do we manage such complexity?

ANSWER:  Gregg Bartlett, Senior Vice President, Product Management, GLOBALFOUNDRIES

The vast majority of Integrated Device Manufacturers (IDMs) have either gone completely fabless or partnered with foundries for their leading-edge technology needs instead of making the huge investments necessary to keep pace with technology. The foundry opportunity is increasingly concentrated at the leading edge; this segment is expected to drive 60 percent of the total foundry market by 2016, representing a total of $27.5 billion. Yet there are fewer high-volume manufacturers that have the capabilities to offer leading-edge technologies beyond 28nm, even as the major companies have accelerated their technology roadmaps at 20nm and 14nm and added new device architectures.

This has led to a global capacity challenge. Leading-edge fabs are more expensive and fewer than ever. At the 130nm node, the cost to build a fab was just over $1B. For a 28nm fab, the cost is about $6B and a 14nm fab is nearly $10B. Technology development costs are rising at a similar rate, growing from a few $10M’s  at 130nm to several $100M’s at 28nm.

On top of these technology and manufacturing challenges, product life cycles are shrinking and end users are expecting more and more from their devices in terms of performance, power-efficiency, and features. Competing on manufacturing expertise alone is no longer a viable strategy in today’s semiconductor industry, and solutions developed in isolation are not adequate. The industry must work closer across all levels of the supply chain to understand these dynamics and how they put demands on the silicon chip.

Fortunately, the fabless/foundry model is evolving to accommodate these changing dynamics. We have been promoting this idea for years with what we like to call “Foundry 2.0.” In the 1970s/1980s, the industry was dominated by the IDM. Then the foundry model was invented and grew to prominence in the 1990s and early 2000s, but it was much more of a contract manufacturing model. A fabless company developed a design in isolation and then “threw it over the wall” to the foundry for manufacturing. There was not much need for interplay between the two companies. Of course, as technology complexity has increased in the past decade, this dynamic has changed dramatically. We have entered the era of collaborative device manufacturing. Collaboration is a buzz word that gets thrown around a lot, but today it really is critical and it needs to happen across all vectors, including design flow development, manufacturing supply chain, and customer engagement.

Q2:  3D in packaging started with wire-bonded-chip-stacks and now includes silicon-interposers (a.k.a. “2.5D”) and the memory-cube using through-silicon via (TSV). How about the complexity of 3D products using chip-package co-design, and many players in the ecosystem being needed hroughout design-ramp-HVM?

ANSWER:  Sesh Ramaswami, Managing Director, TSV and Advanced Packaging, Silicon Systems Group of Applied Materials

Enabling 3D requires the participation of the extended ecosystem. These include contributions from CAD, design tools for die architecture, floor plan, and layout circuit design test structures, as well as methodology wafer level process equipment and materials, wafer-level test assembly and packaging stacked die and package level testing.

Q3:  Due to challenges with lithographic scaling below 45nm half-pitch, how does the need to integrate new materials and device structures change the fabless-foundry relationship? How much of fully-depleted channels using SOI wafers and/or finFETs, followed by alternate channels can the industry afford without commited damand from IDMs and major fabless players for specific variants?

ANSWER:  Adam Brand, Director of Transistor Technology, Silicon Systems Group of Applied Materials

New materials and device structures are going to play a key role in advancing the technology to the next several nodes.

With EUV delayed, multi-patterning is growing in use, and new materials are enabling the sophisticated and precise extension of multi-patterning to the 7nm node and beyond.  The multi-patterning schemes however bring specific restrictions on layout which will affect the design process.

For device structures, Epi in particular is going to enable the next generation of complex device designs with improved mobility and by supporting very thin precisely defined channel structures to scale to smaller gate length and pitch. For these next generation devices, the R&D challenges will be high, but the industry cannot afford to skimp on R&D to find the winning solution to the low power transistor technology required for the 7nm and 5nm and beyond nodes.

Q4:  Mobile consumer devices now seem to drive the leading edge of demand for many ICs. However, the Internet-of-Things (IoT) is often spoken of needing just 65nm node chips to keep costs as low as possible, and these designs are expected to run in high volume for many years. How will these different devices that will continue to evolve in different ways get integrated together?

ANSWER: Michael Buehler-Garcia, Senior Director of Marketing, Calibre Design Solutions of Mentor Graphics

IOT has become the new industry buzz word.  What it has done is spotlight the multiple elements of a complete solution that do not require emerging process technologies for their chip design. Moreover, while a chip may use a well established process node, the actual design may be very complex. For example Mentor is participating in the German RESCAR program to increase the reliability of automotive electronics using our Calibre PERC solution. The initial reliability checks written are targeted for 180nm and older process nodes. Why? Because today’s 180nm and older node designs are much more complex than when these nodes were mainstream digital nodes and as such require more advanced verification solutions. Bottom line:  as opposed to a strategy of only moving to the next process node, chip design companies today have multiple options.  It is up to the ecosystem to provide solutions that allow the designers be able to make trade-offs without major changes in their design flows.

FIGURE: Reliability simulation as part of “RESCAR” program. (Source: Fraunhofer IZM)

The Week in Review: September 12, 2014

Friday, September 12th, 2014

Front End fab equipment spending is projected to increase up to another 20 percent in 2015 to US$ 42 billion, according to most recent edition of the SEMI World Fab Forecast.  In 2015, equipment spending could mark a historical record high, surpassing the previous peak years of 2007 ($39 billion) and 2011 ($40 billion). In 2014, the report predicts growth of approximately 21 percent for Front End fab equipment spending, for total spending of $34.9 billion.

GLOBALFOUNDRIES announced the “GLOBALFOUNDRIES Undergraduate Research Scholarship,” a new scholarship recognizing and rewarding aspiring, leadership-oriented engineering students interested in careers in the semiconductor industry.

SEMI announced that it has successfully appealed to the U.S. government to review the validity of current export controls on semiconductor etch equipment.  On September 8, 2014, the U.S. Department of Commerce published a notice in the Federal Register announcing the launch of the first Foreign Availability Assessment in more than 20 years.

A new company, Epiluvac AB, has entered the scene with the ambition to supply the needed deposition equipment.

Spending on microwave RF power semiconductors continues to tick upward as the availability of new gallium nitride (GaN) devices for 4 to 18GHz becomes more pervasive. Point-to-point communications, SATCOM, radars of all types, and new industrial/medical applications will all benefit by the introduction of these high-power GaN devices. These findings are part of ABI Research’s High-Power RF Active Devices Market Research.

Research Alert: September 9, 2014

Tuesday, September 9th, 2014

GLOBALFOUNDRIES and SRC announce new scholarship for undergraduate engineering students

GLOBALFOUNDRIES today announced the “GLOBALFOUNDRIES Undergraduate Research Scholarship,” a new scholarship recognizing and rewarding aspiring, leadership-oriented engineering students interested in careers in the semiconductor industry.  The GLOBALFOUNDRIES Undergraduate Research Scholarship will fund undergraduate research opportunities (URO) and intern scholars through the Semiconductor Research Corporation’s (SRC) Education Alliance.

Presented at SRC’s annual TECHCON conference in Austin, Texas, the scholarship was created by GLOBALFOUNDRIES in partnership with SRC to recognize and reward science, technology and engineering students who demonstrate promise in their academic and professional efforts. The selected recipients of this scholarship will have the opportunity to interact with GLOBALFOUNDRIES researchers and access the professional resources of SRC and the SRC Education Alliance.

“Building a pipeline of highly skilled talent is essential to our business and to the competitiveness of the entire semiconductor industry,” said Suresh Venkatesan, senior vice president of technology development, GLOBALFOUNDRIES.  “SRC connects companies with the top universities, which results in exciting research and educational opportunities for the best and the brightest students. The GLOBALFOUNDRIES Undergraduate Research Scholarship gives us the opportunity to support science, technology, engineering and mathematics education and help develop the technical leaders who will continue to drive innovation in the semiconductor industry in the future.”

Until recently, SRC focused exclusively on students seeking advanced degrees, providing fellowships for them to do university research that had practical applications for corporate members of its unique consortium. The URO is SRC’s innovative program providing undergraduates with valuable research experience and mentoring. The goal of the URO is to empower bright, well-educated, and experienced scientists and engineers for which U.S. high-tech companies are seeking.

“Recognizing the critical importance of a strong pipeline of new talent for the semiconductor industry, the SRC Education Alliance through the URO Program provides financial assistance to undergraduates, allowing students and universities to recognize the connections between the materials they are learning in the classroom and the technological innovations that transform the world,” said SRC President Larry Sumney. “We are thrilled to collaborate with GLOBALFOUNDRIES as we continue to develop our URO program.”

Layered graphene sandwich for next generation electronics

Sandwiching layers of graphene with white graphene could produce designer materials capable of creating high-frequency electronic devices, University of Manchester scientists have found. The researchers have demonstrated how combining the two-dimensional materials in a stack could create perfect crystals capable of being used in next generation transistors.

Hexagonal boron nitride (hBN), otherwise known as white graphene, is one of a family of two-dimension materials discovered in the wake of the isolation of graphene at the University in 2004. Manchester researchers have previously demonstrated how combining 2D materials, in stacks called heterostructures, could lead to materials capable of being designed to meet industrial demands.

Now, for the first time, the team has demonstrated that the electronic behaviour of the heterostructures can be changed enormously by precisely controlling the orientation of the crystalline layers within the stacks.

The researchers, led by University of Manchester Nobel laureate Sir Kostya Novoselov, carefully aligned two graphene electrodes separated by hBN and discovered there was a conservation of electron energy and momentum.

The findings could pave the way for devices with ultra-high frequencies, such as electronic or photovoltaic sensors.

The research was carried out with scientists from Lancaster and Nottingham Universities in the UK, and colleagues in Russia, Seoul and Japan.

Professor Laurence Eaves, a joint academic from the Universities of Manchester and Nottingham, said: “”This research arises from a beautiful combination of classical laws of motion and the quantum wave nature of electrons, which enables them to flow through barriers

“We are optimistic that further improvements to the device design will lead to applications in high-frequency electronics.”

Professor Vladimir Falko, from Lancaster University, added: “Our observation of tunnelling and negative differential conductance in devices made of multilayers of graphene and hexagonal boron nitride demonstrates potential that this system has for electronics applications.

“It is now up to material growers to find ways to produce such multilayer systems using growth techniques rather than mechanical transfer method used in this work.”

Doped graphene nanoribbons with potential

Graphene is a semiconductor when prepared as an ultra-narrow ribbon – although the material is actually a conductive material. Researchers from Empa and the Max Planck Institute for Polymer Research have now developed a new method to selectively dope graphene molecules with nitrogen atoms. By seamlessly stringing together doped and undoped graphene pieces, they were able to form ”heterojunctions” in the nanoribbons, thereby fulfilling a basic requirement for electronic current to flow in only one direction when voltage is applied – the first step towards a graphene transistor. Furthermore, the team has successfully managed to remove graphene nanoribbons from the gold substrate on which they were grown and to transfer them onto a non-conductive material.

Graphene possesses many outstanding properties: it conducts heat and electricity, it is transparent, harder than diamond and extremely strong. But in order to use it to construct electronic switches, a material must not only be an outstanding conductor, it should also be switchable between ”on” and ”off” states. This requires the presence of a so-called bandgap, which enables semiconductors to be in an insulating state. The problem, however, is that the bandgap in graphene is extremely small. Empa researchers from the ”nanotech@surfaces” laboratory thus developed a method some time ago to synthesise a form of graphene with larger bandgaps by allowing ultra-narrow graphene nanoribbons to ”grow” via molecular self-assembly.

The researchers, led by Roman Fasel, have now achieved a new milestone by allowing graphene nanoribbons consisting of differently doped subsegments to grow. Instead of always using the same ”pure” carbon molecules, they used additionally doped molecules – molecules provided with ”foreign atoms” in precisely defined positions, in this case nitrogen. By stringing together ”normal” segments with nitrogen-doped segments on a gold (Au (111)) surface, so-called heterojunctions are created between the individual segments. The researchers have shown that these display similar properties to those of a classic p-n-junction, i.e. a junction featuring both positive and negative charges across different regions of the semiconductor crystal, thereby creating the basic structure allowing the development of many components used in the semiconductor industry. A p-n junction causes current to flow in only one direction. Because of the sharp transition at the heterojunction interface, the new structure also allows electron/hole pairs to be efficiently separated when an external voltage is applied, as demonstrated theoretically by theorists at Empa and collaborators at Rensselaer Polytechnic Institute. The latter has a direct impact on the power yield of solar cells. The researchers describe the corresponding heterojunctions in segmented graphene nanoribbons in the recently published issue of “Nature Nanotechnology.”

In addition, the scientists have solved another key issue for the integration of graphene nanotechnology into conventional semiconductor industry: how to transfer the ultra-narrow graphene ribbons onto another surface? As long as the graphene nanoribbons remain on a metal substrate (such as gold used here) they cannot be used as electronic switches. Gold conducts and thus creates a short-circuit that “sabotages” the appealing semiconducting properties of the graphene ribbon. Fasel’s team and colleagues at the Max-Planck-Institute for Polymer Research in Mainz have succeeded in showing that graphene nanoribbons can be transferred efficiently and intact using a relatively simple etching and cleaning process onto (virtually) any substrate, for example onto sapphire, calcium fluoride or silicon oxide.

The Week in Review: September 5, 2014

Friday, September 5th, 2014

Contour Semiconductor, Inc. announced it has been awarded three new patents to back its Diode Transistor Memory (DTM) technology, the world’s lowest production-cost, non-volatile memory technology.

Fujitsu Semiconductor America announced that Shinichi “James” Machida, who led the company from late 2008 until spring of 2011, has been named as the new president and CEO of FSA.

ProPlus Design Solutions announced Samsung Electronics has extended its partnership with ProPlus through the deployment of ProPlus’ BSIMProPlus modeling platform for its 14nm FinFET SPICE modeling.

Analog Devices, Inc. introduced the first and only MEMS gyroscope specified to withstand temperatures of up to 175 degrees Celsius commonly encountered by oil and gas drilling equipment.

GLOBALFOUNDRIES, a provider of advanced semiconductor manufacturing technology, announced that Louis “Lou” Lupin has joined the company as senior vice president and chief legal officer.

Credo Semiconductor announced the appointment of Jeff Twombly as vice president of sales and business development.

Taiwanese chipmakers, LED manufacturers, and Outsourced Semiconductor Assembly and Test (OSAT) firms will spend firm nearly $24 billion in the next two years on equipment and materials, powering excitement for SEMICON Taiwan 2014, which opened this week in Taipei.

United Microelectronics Corporation and Fujitsu Semiconductor Limited announced an agreement for UMC to become a minority shareholder of a newly formed subsidiary of Fujitsu Semiconductor that will include its 300mm wafer manufacturing facility located in Kuwana, Mie, Japan.

Rudolph Technologies, Inc. announced that the SUNY College of Nanoscale Science and Engineering (CNSE), Albany, NY, has selected its Discover Enterprise Yield Management Software (YMS) to provide an integrated data warehouse and analytics system for the Global 450 Consortium (G450C) equipment development program.

Blog review July 21, 2014

Monday, July 21st, 2014

Matthew Hogan, a Product Marketing Manager for Calibre Design Solutions at Mentor Graphics, blogs that SoC Reliability Verification Doesn’t Just Happen, You Know. He says the best way to verify multi-IP, multiple power domain SoCs, is with the Unified Power Format (UPF), which enables a repeatable, comprehensive, and efficient design verification methodology, using industry standards, at the transistor level.

Dick James, Senior Technology Analyst, Chipworks, has a TSMC-fabbed 20-nm part in-house, and is looking forward to the analysis results. Wondering what changes TSMC has made from the 28-nm process, Dick says he expects mostly a shrink of the latter process, with no change to the materials of the high-k stack, though maybe to the sequence.

Ed Korczynski continues his theme of “Moore’s Law is Dead” with a third installment that looks at when that might happen. He says that at ~4nm pitch we run out of room “at the bottom,” after patterning costs explode at 45nm pitch.

Vivek Bakshi, EUV Litho, Inc. blogs about The 2014 EUVL Workshop which was held late last month amid some positive highlights and lots of R&D updates. The keynote talks this year were from Intel, Gigaphoton and Toshiba.

In his 201st Insights from The Leading Edge (IFTLE) blog post, Phil Garrou takes a look at some of the presentations at this year’s ConFab. Subramani Kengeri, Vice President, Advanced Technology Architecture for GlobalFoundries discussed the techno-economics of the semiconductor industry. Gary Patton, VP of IBM Semiconductor Research & Development Center addressed “Semiconductor Technology: Trends, Challenges, & Opportunities.” Adrian Maynes, 450C program manager, discussed the “450mm Transition Toward Sustainability: Facility & Infrastructure Requirements.”

Zvi Or-Bach, President and CEO of MonolithIC 3D Inc., blogs that over the course of three major industry conferences (VLSI 2013, IEDM 2013 and DAC 2014), executives of Qualcomm voiced a call for monolithic 3D “to extend the semiconductor roadmap way beyond the 2D scaling” as part of their keynote presentations.

ST licenses 28nm FD-SOI to Samsung

Friday, May 16th, 2014

By Ed Korczynski, Sr. Technical Editor, SST/SemiMD

On May 14, 2014 it was announced that STMicroelectronics and Samsung Electronics signed an agreement on 28nm Fully Depleted Silicon-on-Insulator (FD-SOI) technology for multi-source manufacturing collaboration. The agreement includes ST’s fully developed process technology and design enablement ecosystem from its 300mm facility in Crolles, France. The Samsung 28nm FD-SOI process will be qualified in early 2015 for volume production.

“Building upon the existing solid relationship between ST and Samsung within the framework of the International Semiconductor Development Alliance, this 28nm FD-SOI agreement expands the ecosystem and augments fab capacity for ST and the entire electronics industry,” said Jean-Marc Chery, COO, STMicroelectronics. “We foresee further expansion of the 28nm FD-SOI ecosystem, to include the leading EDA and IP suppliers, which will enrich the IP catalog available for 28nm FD-SOI.”

According to Handel Jones, founder and CEO of International Business Strategies Inc. (IBS), “The 28nm node will be long-lived; we expect it to represent approximately 4.3 million wafers in the 2017 timeframe, and FD-SOI could capture at least 25 percent of this market.”

Table 1 shows IBS data estimating costs for different 28nm fab process technologies.

“We are pleased to announce this 28nm FD-SOI collaboration with ST. This is an ideal solution for customers looking for extra performance and power efficiency at the 28nm node without having to migrate to 20nm,” said Dr. Seh-Woong Jeong, executive vice president of System LSI Business, Samsung Electronics. “28nm process technology is a highly productive process technology and expected to have a long life span based on well-established manufacturing capabilities.”

In June 2012, ST announced that GLOBALFOUNDRIES had joined the FD-SOI party for the 28nm and 20nm nodes. However, though the name has since changed from “20nm” to “14nm” (Table 2), work continues nonetheless with GLOBALFOUNDRIES on 14nm FD-SOI with prototyping and IP validation vehicles planned to run by the end of this year. Samsung has so far only licensed the 28nm node technology from ST. A representative of GLOBALFOUNDRIES reached for comment on this news expressed welcome to Samsung as an additional supplier in the FD-SOI ecosystem.

“Leti continues its development of further generations and our technology and design results show great promise for the 14nm and 10nm nodes,” said Laurent Malier, CEO of CEA-Leti (Laboratory for Electronics and Information Technology). Leti and ST are not against finFET technology, but sees it as complementary to SOI. In fact the ecosystem plans to add finFETs to the FD-SOI platform for the 10nm node, at which point Taiwanese foundry UMC plans to join.

FD-SOI Substrate Technology

Soitec, a world leader in generating and manufacturing revolutionary semiconductor materials for the electronics and energy industries, supplies most of the world’s SOI wafers. Paul Boudre, COO of Soitec, commented, “Our FD-SOI wafers represent an incredible technology achievement, resulting from over 10 years of continuous research and high-volume manufacturing expertise. With our two fabs and our licensing strategy, the supply chain is in place and we are very excited by this opportunity to provide the semiconductor industry with our smart substrates in high volume to enable widespread deployment of FD-SOI technology.”

Soitec’s R&D of ultra-thin SOI was partly funded and facilitated by the major French program called “Investments for the Future.” Soitec has collaborated with CEA-Leti on process evolution and characterization, with IBM Microelectronics for device validation and collaboration, and with STMicroelectronics to industrialize and demonstrate the first products.

Boudre, in an exclusive interview with SST/SemiMD, explained, “For 28nm node processing we use a 25+-1nm buried oxide layer, which is reduced in thickness to 20+-1nm when going to the 14nm node and we don’t see any differences in the substrate production. However, for the 10nm node the buried oxide layer needs to be 15nm thin, and we will need some new process steps to be able to embed nMOS strain into substrates.”

—E.K.

Solid State Watch: May 2-8, 2014

Friday, May 9th, 2014
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The Week in Review: May 9, 2014

Friday, May 9th, 2014

SEMATECH announced this week that researchers have reached a significant milestone in reducing tool-generated defects from the multi-layer deposition of mask blanks used for extreme ultraviolet lithography, pushing the technology another significant step toward readiness for high-volume manufacturing.

University of California, Berkeley researchers sponsored by Semiconductor Research Corporation (SRC) are pursuing a novel approach to 3D device integration that promises to lead to advanced mobile devices and wearable electronics featuring increased functionality in more low-profile packages.

GlobalFoundries this week introduced an optimized semiconductor manufacturing platform aimed specifically at meeting the stringent and evolving needs of the automotive industry.

Peregrine Semiconductor announced shipment of the first RF switches built on the UltraCMOS 10 technology platform.

BASF inaugurated a new Electronic Materials Sampling and Development facility in Hillsboro, Oregon. The new facility is a strategic step towards establishing a North American footprint to supply materials for semiconductor manufacturing applications related to the electronics industry.

Veeco Instruments Inc. has appointed Shubham Maheshwari, 42, as its new Executive Vice President, Finance and Chief Financial Officer (CFO). Mr. Maheshwari replaces David D. Glass, who announced his retirement from Veeco last December.

Avago Technologies Limited and LSI Corporation announced Avago has completed its acquisition of LSI Corporation for $11.15 per share in an all-cash transaction valued at approximately $6.6 billion.

Microchip Technology Inc., a provider of microcontroller, mixed-signal, analog and Flash-IP solutions, this week introduced a new parallel Flash memory device.

The Semiconductor Industry Association announced that worldwide sales of semiconductors reached $78.47 billion during the first quarter of 2014, marking the industry’s highest-ever first quarter sales.

Qualcomm elected Harish Manwani to board of directors. Manwani brings more than 35 years of consumer product and global management experience, and currently serves as the Chief Operating Officer at Unilever PLC.

Blog review April 22, 2014

Tuesday, April 22nd, 2014

Pete Singer blogs that it’s difficult to make interconnects much smaller without introducing significant increases in resistivity. At the upcoming IITC/AMC joint conference in May, many papers focus on new materials that could lead to reduced resistivity and enable further interconnect scaling. Most notably, graphene and CNTs provide an interesting alternative to copper.

Phil Garrou continues his analysis of the IMAPS Device Packaging Conference with a look at the presentations made by Flip Chip International and SUSS (the use of lasers in the manufacturing of WLP); GLOBALFOUNDRIES, Amkor and Open Silicon (a 2.5D ARM dual core product demonstrator which consists of 2 ARM die on a high density silicon interposer); Corning (results of multiple glass interposer programs) and Namics (underfill products for FC BGA and FC CSP).

GLOBALFOUNDRIES and Samsung join forces on 14nm finFETs

Thursday, April 17th, 2014

By Ed Korczynski and Pete Singer, SemiMD and Solid State Technology

Fabless companies could skip the 20nm node and move straight to 14nm FinFETs. That is the hope of GLOBALFOUNDRIES and Samsung who are announcing a joint program that offers a single process design kit (PDK) and manufacturing at four different fabs with identical processes. The PDKs are available now, and 14nm manufacturing could move into high volume production by the end of the year.

This is unprecedented,” said Kelvin Low, senior director of marketing at Samsung. “It never has happened in the industry, especially at the very leading edge nodes. We are confident that this will transform the supply chain model,” he added.

Fabless companies such as Qualcomm have been lobbying for such multi-sourcing for some time, and are eager to move to FinFETs which offer higher performance and reduced power consumption. 14nm FinFETs offer a 20% improvement in performance and a 35% reduction in power compared to 20nm technology.

“For both Samsung and GLOBALFOUNDRIES, we will be providing our customers with a choice and assurances of supply, enabled by the unprecedented global capacity across our respective manufacturing facilities throughout different locations worldwide,” Low said. “For Samsung, we have facilities in the U.S. in Austin. We also have a couple of plants in Korea. For GLOBALFOUNDRIES, the 14 nm capacity will be in Malta, NY.”


The single process design kit will allow customers to do a single design that is capable of being multi-sourced from different locations.

“This really is a change from the existing supply chain model where customers are trying to design multiple designs to multi-source their products,” Low said. “True design compatibility in this collaboration will allow customers to better manage their design NRE and they can focus on bringing the product to market on time. Both companies see this as a necessary advancement of the supply chain model and we start off with the 14nm LPE as well as the 14nm LPP technology node.” 14nm LPP is a follow-on offering which has additional performance enhancements as well as power reduction attributes.

Samsung had already developed much of the process technology for LPP and LPE flows to run using 14nm node finFETs, while GLOBALFOUNDRIES was working independently on another 14nm node process variant. The two companies decided to pool resources to save both time and money in bringing 14nm node finFET capability to the commercial IC foundry market.

Because of customer interest in having that assurance of supply and being able to do one GDS and being able to work off of one common PDK and source at both of our companies, we decided to work together and go with the 14 LPE and 14 LPP as common offerings between Samsung and GLOBALFOUNDRIES,” said Ana Hunter, VP of product management at GLOBALFOUNDRIES.

Low said that Samsung is already running 14nm products in its fab in Korea. The 14nm LPE, for example, was qualified earlier this year.

“We are already in silicon validation of our lead customer products. We expect to ramp production by the end of this year,” he said. Design activities started almost three years ago. “Right now, we are seeing a lot more pickup overall by the lead adopters and even other customers following suit, mainly because the marketplace does see that the 14nm FinFET is at the right maturity level for volume production,” Low said.

Although there is still lot of activity at 28nm, the technology is considered to be in a mature phase. “We still continue to see healthy, new design-ins,” Low said. “Of course, there are a lot of requests to see what additional enhancements we can do at our 28nm node to prolong the lifespan of that node.”

What about 20nm? “From Samsung’s viewpoint, we see that a relatively short-lived node, mainly because of the overall resonance of FinFETs and the eagerness of customers to migrate from 28nm directly to 14nm FinFETs.”

Hunter agrees, noting that 28nm has been in high volume production for several years now. She said GLOBALFOUNDRIES does have 20nm product tapeouts running in the line, but said that she does not see 20nm being a very extensive node in that most customers are eager to get onto FinFETs.

“We do have products running at 20nm, but I think the design efforts will quickly go over to FinFET and we’ll see that be a much longer lived node with a lot more product tapeouts,” she said.

The companies say the 14nm FinFET offering could be up to 15% smaller than that available from other foundries due to aggressive gate pitch, smaller memory solution and innovative layout schemes for compact logic.


Hunter, having been a VP at Samsung before holding her current position at GLOBALFOUNDRIES, noted that the two companies, along with IBM, have been in collaboration for quite some time on “The Common Platform” at 65, 45, and 28nm nodes, but this announcement is strictly between GF and Samsung.

“We do continue to work with IBM in other areas at the Albany Nanotech center, where there is continuing collaboration on more advanced nodes, on materials research, pathfinding, and advanced module development kind of work,” she said.

Fabless customers use a single PDK to do a single design, allowing a single GDS file to be sent to either company. The design-for-manufacturing (DFM) and reticle-enhancement technologies (RET) needed at the 14nm node are challenging.

“We go deep into the collaboration, even to the OPC level and a lot of sharing on DFM as well. It is a very extensive collaboration,” confirmed Hunter. “At 14nm the designs are extremely complex, and to be able to truly supply multi-sourcing from one GDS, you have to have that level of collaboration to ensure that the output from all of our factories is the same. That’s a huge advantage to customers because the idea that you could source from two different companies without the kind of collaboration that GLOBALFOUNDRIES and Samsung are doing is just simply impossible when you get into 14nm FinFETs. When you get into the complexity of the designs, the databases, the amount of reticle enhancement techniques that are required to be able to print these geometries, you need to have that kind of in-depth collaboration.”

Low said that the two companies have a “fabsync” structure running in the background to ensure the fabs are fully synchronized.

“There are a couple of things we are doing proactively,” he said. “The technology teams are deeply engaged with each other. We have technology workshops across both companies. We have test chips that are run regularly to ensure that the process continues to stay synchronized. These test chips are not just simple transistors. We have product level elements that we’ve included to make sure we measure the critical parameters. This is only enabled through open sharing of technology information.”

Hunter adds: “We run the same test chips, we share wafers back and forth to measure each other’s products to make sure all of our equipment is calibrated, test equipment calibrated, results are the same on exactly the same test chip.We have test-chips with product-level structures that run in all fabs and both companies share all data to ensure that all fabs stay in alignment. Not just SPICE models and SRAMs, but full chip-like design features.”

However, customers will have to re-do lithography masks if they want to move manufacturing from one company to the other, in part because of issues with shipping masks. Kevin Low, Samsung’s senior director of marketing, commented, “We’ll be providing our customers choice and secure supply. At Samsung we have capacity in Texas and Korea.”

Cost/transistor for 14nm may not be lower compared to 20nm and 28nm. Hunter said, “To continue with optical lithography, it is challenging to do double-patterning and keep costs low.” However, since much of the motivation in moving from 20nm to 14nm is for power-sipping mobile SoCs, by reducing the power consumption by the claimed 35% there could be cost-savings at the packaging level such that the overall product cost is reduced.

To be able to offer essentially the same manufacturing process to customers, GLOBALFOUNDRIES and Samsung had to harmonize not just process recipes but many of the OEM tools used in these fabs.

Hunter says, “To get the same results at this node, it does require engineering down to the tool level and the individual recipe level. That doesn’t mean all tools are exactly the same, however, since cost and availability of tools may have been different when the fabs were equipped.”

Customers can choose which foundry that choose to work with, and then they can choose to discuss commercial terms such as which specific foundry site may be booked to do the work.

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