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Blog review July 21, 2014

Monday, July 21st, 2014

Matthew Hogan, a Product Marketing Manager for Calibre Design Solutions at Mentor Graphics, blogs that SoC Reliability Verification Doesn’t Just Happen, You Know. He says the best way to verify multi-IP, multiple power domain SoCs, is with the Unified Power Format (UPF), which enables a repeatable, comprehensive, and efficient design verification methodology, using industry standards, at the transistor level.

Dick James, Senior Technology Analyst, Chipworks, has a TSMC-fabbed 20-nm part in-house, and is looking forward to the analysis results. Wondering what changes TSMC has made from the 28-nm process, Dick says he expects mostly a shrink of the latter process, with no change to the materials of the high-k stack, though maybe to the sequence.

Ed Korczynski continues his theme of “Moore’s Law is Dead” with a third installment that looks at when that might happen. He says that at ~4nm pitch we run out of room “at the bottom,” after patterning costs explode at 45nm pitch.

Vivek Bakshi, EUV Litho, Inc. blogs about The 2014 EUVL Workshop which was held late last month amid some positive highlights and lots of R&D updates. The keynote talks this year were from Intel, Gigaphoton and Toshiba.

In his 201st Insights from The Leading Edge (IFTLE) blog post, Phil Garrou takes a look at some of the presentations at this year’s ConFab. Subramani Kengeri, Vice President, Advanced Technology Architecture for GlobalFoundries discussed the techno-economics of the semiconductor industry. Gary Patton, VP of IBM Semiconductor Research & Development Center addressed “Semiconductor Technology: Trends, Challenges, & Opportunities.” Adrian Maynes, 450C program manager, discussed the “450mm Transition Toward Sustainability: Facility & Infrastructure Requirements.”

Zvi Or-Bach, President and CEO of MonolithIC 3D Inc., blogs that over the course of three major industry conferences (VLSI 2013, IEDM 2013 and DAC 2014), executives of Qualcomm voiced a call for monolithic 3D “to extend the semiconductor roadmap way beyond the 2D scaling” as part of their keynote presentations.

ST licenses 28nm FD-SOI to Samsung

Friday, May 16th, 2014

By Ed Korczynski, Sr. Technical Editor, SST/SemiMD

On May 14, 2014 it was announced that STMicroelectronics and Samsung Electronics signed an agreement on 28nm Fully Depleted Silicon-on-Insulator (FD-SOI) technology for multi-source manufacturing collaboration. The agreement includes ST’s fully developed process technology and design enablement ecosystem from its 300mm facility in Crolles, France. The Samsung 28nm FD-SOI process will be qualified in early 2015 for volume production.

“Building upon the existing solid relationship between ST and Samsung within the framework of the International Semiconductor Development Alliance, this 28nm FD-SOI agreement expands the ecosystem and augments fab capacity for ST and the entire electronics industry,” said Jean-Marc Chery, COO, STMicroelectronics. “We foresee further expansion of the 28nm FD-SOI ecosystem, to include the leading EDA and IP suppliers, which will enrich the IP catalog available for 28nm FD-SOI.”

According to Handel Jones, founder and CEO of International Business Strategies Inc. (IBS), “The 28nm node will be long-lived; we expect it to represent approximately 4.3 million wafers in the 2017 timeframe, and FD-SOI could capture at least 25 percent of this market.”

Table 1 shows IBS data estimating costs for different 28nm fab process technologies.

“We are pleased to announce this 28nm FD-SOI collaboration with ST. This is an ideal solution for customers looking for extra performance and power efficiency at the 28nm node without having to migrate to 20nm,” said Dr. Seh-Woong Jeong, executive vice president of System LSI Business, Samsung Electronics. “28nm process technology is a highly productive process technology and expected to have a long life span based on well-established manufacturing capabilities.”

In June 2012, ST announced that GLOBALFOUNDRIES had joined the FD-SOI party for the 28nm and 20nm nodes. However, though the name has since changed from “20nm” to “14nm” (Table 2), work continues nonetheless with GLOBALFOUNDRIES on 14nm FD-SOI with prototyping and IP validation vehicles planned to run by the end of this year. Samsung has so far only licensed the 28nm node technology from ST. A representative of GLOBALFOUNDRIES reached for comment on this news expressed welcome to Samsung as an additional supplier in the FD-SOI ecosystem.

“Leti continues its development of further generations and our technology and design results show great promise for the 14nm and 10nm nodes,” said Laurent Malier, CEO of CEA-Leti (Laboratory for Electronics and Information Technology). Leti and ST are not against finFET technology, but sees it as complementary to SOI. In fact the ecosystem plans to add finFETs to the FD-SOI platform for the 10nm node, at which point Taiwanese foundry UMC plans to join.

FD-SOI Substrate Technology

Soitec, a world leader in generating and manufacturing revolutionary semiconductor materials for the electronics and energy industries, supplies most of the world’s SOI wafers. Paul Boudre, COO of Soitec, commented, “Our FD-SOI wafers represent an incredible technology achievement, resulting from over 10 years of continuous research and high-volume manufacturing expertise. With our two fabs and our licensing strategy, the supply chain is in place and we are very excited by this opportunity to provide the semiconductor industry with our smart substrates in high volume to enable widespread deployment of FD-SOI technology.”

Soitec’s R&D of ultra-thin SOI was partly funded and facilitated by the major French program called “Investments for the Future.” Soitec has collaborated with CEA-Leti on process evolution and characterization, with IBM Microelectronics for device validation and collaboration, and with STMicroelectronics to industrialize and demonstrate the first products.

Boudre, in an exclusive interview with SST/SemiMD, explained, “For 28nm node processing we use a 25+-1nm buried oxide layer, which is reduced in thickness to 20+-1nm when going to the 14nm node and we don’t see any differences in the substrate production. However, for the 10nm node the buried oxide layer needs to be 15nm thin, and we will need some new process steps to be able to embed nMOS strain into substrates.”

—E.K.

Solid State Watch: May 2-8, 2014

Friday, May 9th, 2014
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The Week in Review: May 9, 2014

Friday, May 9th, 2014

SEMATECH announced this week that researchers have reached a significant milestone in reducing tool-generated defects from the multi-layer deposition of mask blanks used for extreme ultraviolet lithography, pushing the technology another significant step toward readiness for high-volume manufacturing.

University of California, Berkeley researchers sponsored by Semiconductor Research Corporation (SRC) are pursuing a novel approach to 3D device integration that promises to lead to advanced mobile devices and wearable electronics featuring increased functionality in more low-profile packages.

GlobalFoundries this week introduced an optimized semiconductor manufacturing platform aimed specifically at meeting the stringent and evolving needs of the automotive industry.

Peregrine Semiconductor announced shipment of the first RF switches built on the UltraCMOS 10 technology platform.

BASF inaugurated a new Electronic Materials Sampling and Development facility in Hillsboro, Oregon. The new facility is a strategic step towards establishing a North American footprint to supply materials for semiconductor manufacturing applications related to the electronics industry.

Veeco Instruments Inc. has appointed Shubham Maheshwari, 42, as its new Executive Vice President, Finance and Chief Financial Officer (CFO). Mr. Maheshwari replaces David D. Glass, who announced his retirement from Veeco last December.

Avago Technologies Limited and LSI Corporation announced Avago has completed its acquisition of LSI Corporation for $11.15 per share in an all-cash transaction valued at approximately $6.6 billion.

Microchip Technology Inc., a provider of microcontroller, mixed-signal, analog and Flash-IP solutions, this week introduced a new parallel Flash memory device.

The Semiconductor Industry Association announced that worldwide sales of semiconductors reached $78.47 billion during the first quarter of 2014, marking the industry’s highest-ever first quarter sales.

Qualcomm elected Harish Manwani to board of directors. Manwani brings more than 35 years of consumer product and global management experience, and currently serves as the Chief Operating Officer at Unilever PLC.

Blog review April 22, 2014

Tuesday, April 22nd, 2014

Pete Singer blogs that it’s difficult to make interconnects much smaller without introducing significant increases in resistivity. At the upcoming IITC/AMC joint conference in May, many papers focus on new materials that could lead to reduced resistivity and enable further interconnect scaling. Most notably, graphene and CNTs provide an interesting alternative to copper.

Phil Garrou continues his analysis of the IMAPS Device Packaging Conference with a look at the presentations made by Flip Chip International and SUSS (the use of lasers in the manufacturing of WLP); GLOBALFOUNDRIES, Amkor and Open Silicon (a 2.5D ARM dual core product demonstrator which consists of 2 ARM die on a high density silicon interposer); Corning (results of multiple glass interposer programs) and Namics (underfill products for FC BGA and FC CSP).

GLOBALFOUNDRIES and Samsung join forces on 14nm finFETs

Thursday, April 17th, 2014

By Ed Korczynski and Pete Singer, SemiMD and Solid State Technology

Fabless companies could skip the 20nm node and move straight to 14nm FinFETs. That is the hope of GLOBALFOUNDRIES and Samsung who are announcing a joint program that offers a single process design kit (PDK) and manufacturing at four different fabs with identical processes. The PDKs are available now, and 14nm manufacturing could move into high volume production by the end of the year.

This is unprecedented,” said Kelvin Low, senior director of marketing at Samsung. “It never has happened in the industry, especially at the very leading edge nodes. We are confident that this will transform the supply chain model,” he added.

Fabless companies such as Qualcomm have been lobbying for such multi-sourcing for some time, and are eager to move to FinFETs which offer higher performance and reduced power consumption. 14nm FinFETs offer a 20% improvement in performance and a 35% reduction in power compared to 20nm technology.

“For both Samsung and GLOBALFOUNDRIES, we will be providing our customers with a choice and assurances of supply, enabled by the unprecedented global capacity across our respective manufacturing facilities throughout different locations worldwide,” Low said. “For Samsung, we have facilities in the U.S. in Austin. We also have a couple of plants in Korea. For GLOBALFOUNDRIES, the 14 nm capacity will be in Malta, NY.”


The single process design kit will allow customers to do a single design that is capable of being multi-sourced from different locations.

“This really is a change from the existing supply chain model where customers are trying to design multiple designs to multi-source their products,” Low said. “True design compatibility in this collaboration will allow customers to better manage their design NRE and they can focus on bringing the product to market on time. Both companies see this as a necessary advancement of the supply chain model and we start off with the 14nm LPE as well as the 14nm LPP technology node.” 14nm LPP is a follow-on offering which has additional performance enhancements as well as power reduction attributes.

Samsung had already developed much of the process technology for LPP and LPE flows to run using 14nm node finFETs, while GLOBALFOUNDRIES was working independently on another 14nm node process variant. The two companies decided to pool resources to save both time and money in bringing 14nm node finFET capability to the commercial IC foundry market.

Because of customer interest in having that assurance of supply and being able to do one GDS and being able to work off of one common PDK and source at both of our companies, we decided to work together and go with the 14 LPE and 14 LPP as common offerings between Samsung and GLOBALFOUNDRIES,” said Ana Hunter, VP of product management at GLOBALFOUNDRIES.

Low said that Samsung is already running 14nm products in its fab in Korea. The 14nm LPE, for example, was qualified earlier this year.

“We are already in silicon validation of our lead customer products. We expect to ramp production by the end of this year,” he said. Design activities started almost three years ago. “Right now, we are seeing a lot more pickup overall by the lead adopters and even other customers following suit, mainly because the marketplace does see that the 14nm FinFET is at the right maturity level for volume production,” Low said.

Although there is still lot of activity at 28nm, the technology is considered to be in a mature phase. “We still continue to see healthy, new design-ins,” Low said. “Of course, there are a lot of requests to see what additional enhancements we can do at our 28nm node to prolong the lifespan of that node.”

What about 20nm? “From Samsung’s viewpoint, we see that a relatively short-lived node, mainly because of the overall resonance of FinFETs and the eagerness of customers to migrate from 28nm directly to 14nm FinFETs.”

Hunter agrees, noting that 28nm has been in high volume production for several years now. She said GLOBALFOUNDRIES does have 20nm product tapeouts running in the line, but said that she does not see 20nm being a very extensive node in that most customers are eager to get onto FinFETs.

“We do have products running at 20nm, but I think the design efforts will quickly go over to FinFET and we’ll see that be a much longer lived node with a lot more product tapeouts,” she said.

The companies say the 14nm FinFET offering could be up to 15% smaller than that available from other foundries due to aggressive gate pitch, smaller memory solution and innovative layout schemes for compact logic.


Hunter, having been a VP at Samsung before holding her current position at GLOBALFOUNDRIES, noted that the two companies, along with IBM, have been in collaboration for quite some time on “The Common Platform” at 65, 45, and 28nm nodes, but this announcement is strictly between GF and Samsung.

“We do continue to work with IBM in other areas at the Albany Nanotech center, where there is continuing collaboration on more advanced nodes, on materials research, pathfinding, and advanced module development kind of work,” she said.

Fabless customers use a single PDK to do a single design, allowing a single GDS file to be sent to either company. The design-for-manufacturing (DFM) and reticle-enhancement technologies (RET) needed at the 14nm node are challenging.

“We go deep into the collaboration, even to the OPC level and a lot of sharing on DFM as well. It is a very extensive collaboration,” confirmed Hunter. “At 14nm the designs are extremely complex, and to be able to truly supply multi-sourcing from one GDS, you have to have that level of collaboration to ensure that the output from all of our factories is the same. That’s a huge advantage to customers because the idea that you could source from two different companies without the kind of collaboration that GLOBALFOUNDRIES and Samsung are doing is just simply impossible when you get into 14nm FinFETs. When you get into the complexity of the designs, the databases, the amount of reticle enhancement techniques that are required to be able to print these geometries, you need to have that kind of in-depth collaboration.”

Low said that the two companies have a “fabsync” structure running in the background to ensure the fabs are fully synchronized.

“There are a couple of things we are doing proactively,” he said. “The technology teams are deeply engaged with each other. We have technology workshops across both companies. We have test chips that are run regularly to ensure that the process continues to stay synchronized. These test chips are not just simple transistors. We have product level elements that we’ve included to make sure we measure the critical parameters. This is only enabled through open sharing of technology information.”

Hunter adds: “We run the same test chips, we share wafers back and forth to measure each other’s products to make sure all of our equipment is calibrated, test equipment calibrated, results are the same on exactly the same test chip.We have test-chips with product-level structures that run in all fabs and both companies share all data to ensure that all fabs stay in alignment. Not just SPICE models and SRAMs, but full chip-like design features.”

However, customers will have to re-do lithography masks if they want to move manufacturing from one company to the other, in part because of issues with shipping masks. Kevin Low, Samsung’s senior director of marketing, commented, “We’ll be providing our customers choice and secure supply. At Samsung we have capacity in Texas and Korea.”

Cost/transistor for 14nm may not be lower compared to 20nm and 28nm. Hunter said, “To continue with optical lithography, it is challenging to do double-patterning and keep costs low.” However, since much of the motivation in moving from 20nm to 14nm is for power-sipping mobile SoCs, by reducing the power consumption by the claimed 35% there could be cost-savings at the packaging level such that the overall product cost is reduced.

To be able to offer essentially the same manufacturing process to customers, GLOBALFOUNDRIES and Samsung had to harmonize not just process recipes but many of the OEM tools used in these fabs.

Hunter says, “To get the same results at this node, it does require engineering down to the tool level and the individual recipe level. That doesn’t mean all tools are exactly the same, however, since cost and availability of tools may have been different when the fabs were equipped.”

Customers can choose which foundry that choose to work with, and then they can choose to discuss commercial terms such as which specific foundry site may be booked to do the work.

Blog review April 7, 2014

Monday, April 7th, 2014

Pete Singer reveals the lineup of presenters for Session 1 of The ConFab, to be held June 22-25 in Las Vegas, and provides summaries of their talks. Speakers will be Vijay Ullal, COO, Fairchild Semiconductor; Dave Anderson, President and CEO, Novati Technologies; Gopal Rao, Senior Director Business Development, SEMATECH; Adrian Maynes, Program Manager, F450C; and Bill McClean, President, IC Insights.

Phil Garrou blogs about a variety of diverse issues this week, including GLOBALFOUNDRIES’ potential purchase of IBM’s semiconductor business, Altera’s separate deals with Intel and TSMC, why FinFET could be more expensive that more conventional CMOS strategies, as view by Handle Jones of IBS, and a new joint development program between ASE and Inotera focused on 3D IC packaging.

Blog review March 17, 2014

Monday, March 17th, 2014

Pete Singer is delighted to report that Dr. Roawen Chen, Senior Vice Present of global operations at Qualcomm, has accepted our invitation to deliver the keynote talk at The ConFab, on Monday June 23rd. As previously announced, Dr. Gary Patton, Vice President of IBM’s Semiconductor Research and Development Center in East Fishkill, New York, will deliver the keynote on the second day, on Tuesday June 24th.

Phil Garrou takes a look at what was reported at SEMI’s 2.5/3D IC Summit held in Grenoble, focusing on presentations from Gartner, GLOBALFOUNDRIES, TSMC and imec. He writes that GLOBALFOUNDRIES has been detailing their imminent commercialization of 2.5/3D IC for several years, and provide a chart showing the current status report. TSMC offered a definition of their supply chain model where OSATS are now integrated.

Bharat Ramakrishnan of Applied Materials writes about the importance of wearable electronics in the Internet of Things (IoT) era, and the role that precision materials engineering will play. He note that one key part of the wearables ecosystem that is still in need of new innovations is the battery. Two of the biggest challenges to overcome are the thick form factor due to battery size, and the lack of adequate battery life, thus requiring frequent recharging.

Solid State Watch: February 21-28, 2014

Friday, February 28th, 2014
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Blog Review: November 25, 2013

Monday, November 25th, 2013

Zvi Or-Bach, president and CEO of MonolithIC 3D, blogs about a recent announcement by Intel CEO Brian Krzanich on company expansion focused on a foundry plan. Or-Bach said that if Intel could keep the traditional 30% cost reduction per node from 28nm to 10nm, and the foundry’s cost per transistor is staying flat, then Intel would be able to provide their foundry customers SoC products at a third of the other foundries cost, and accordingly Intel should be able to do very well in its foundry business.

Vivek Bakshi, EUV Litho, Inc. reports on work presented at the 2013 Source Workshop (Nov 3-7, 2013, Dublin, Ireland), including data on the readiness of 50 W EUV sources to support EUVL scanners. At the meeting, keynoter Vadim Banine of ASML said that 50 W EUV sources have now demonstrated good dose control and are now available for deployment in the field. ASML also presented data on the feasibility of source power of 175 W at the first focus (720 W at source), and utilizing new, protective cap layers to give collectors six months of life.

At the GaTech Global Interposer Technology Workshop (GIT) in Atlanta, the pervasive theme appeared to be whether a change in substrate is required to lower overall costs and help drive HVM (high volume manufacturing) applications. Phil Garrou reports on the workshop, including presentations from Ron Huemoeller of Amkor and David McCann of GLOBALFOUNDRIES.

Pete Singer provides a preview of a special focus session at the upcoming IEEE International Electron Devices Meeting (IEDM), scheduled for December 9 – 11, 2013. The session covers many of today’s hot topics: memory, LEDs, silicon photonics, interposers, SOI finFETS and 450mm.

Dr. Lianfeng Yang of ProPlus Design Solutions, Inc., blogs that these days, circuit designers are talking about the increasing giga-scale circuit size. Semiconductor CMOS technology downscaled to nano-scale, forcing the move to make designing for yield (DFY) mandatory and compelling them to re-evaluate how they design and verify their chips.

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