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3DIC Technology Drivers and Roadmaps

Monday, June 22nd, 2015

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By Ed Korczynski, Sr. Technical Editor

After 15 years of targeted R&D, through-silicon via (TSV) formation technology has been established for various applications. Figure 1 shows that there are now detailed roadmaps for different types of 3-dimensional (3D) ICs well established in industry—first-order segmentation based on the wiring-level/partitioning—with all of the unit-processes and integration needed for reliable functionality shown. Using block-to-block integration with 5 micron lines at leading international IC foundries such as GlobalFoundries, systems stacking logic and memory such as the Hybrid Memory Cube (HMC) are now in production.

Fig. 1: Today’s 3D technology landscape segmented by wiring-level, showing cross-sections of typical 2-tier circuit stacks, and indicating planned reductions in contact pitches. (Source: imec)

“There are interposers for high-end complex SOC design with good yield,” informed Eric Beyne, Scientific Director Advanced Packaging & Interconnect for imec in an exclusive interview with Solid State Technology. ““For a systems company, once you’ve made the decision to go 3D there’s no way back,” said Beyne. “If you need high-bandwidth memory, for example, then you’re committed to some sort of 3D. The process is happening today.” Beyne is scheduled to talk about 3D technology driven by 3D application requirements in the imec Technology Forum to be held July 13 in San Francisco.

Adaptation of TSV for stacking of components into a complete functional system is key to high-volume demand. Phil Garrou, packaging technologist and SemiMD blogger, reported from the recent ConFab that Hynix is readying a second generation of high-bandwidth memory (HBM 2) for use in high performance computing (HPC) such as graphics, with products already announced like Pascal from Nvidia and Greenland from AMD.

For a normalized 1 cm2 of silicon area, wide-IO memory needs 1600 signal pins (not counting additional power and ground pins) so several thousand TSV are needed for high-performance stacked DRAM today, while in more advanced memory architectures it could go up by another factor of 10. For wide-IO HVM-2 (or Wide-IO2) the silicon consumed by IO circuitry is maybe 6 cm2 today, such that a 3D stack with shorter vertical connections would eliminate many of the drivers on the chip and would allow scaling of the micro-bumps to perhaps save a total of 4 cm2 in silicon area. 3D stacks provide such trade-offs between design and performance, so the best results are predicted for 3DICs where the partitioning can be re-done at the gate or transistor level. For example, a modern 8-core microprocessor could have over 50% of the silicon area consumed by L3-cache-memory and IO circuitry, and moving from 2D to 3D would reduce total wire-lengths and interconnect power consumptions by >50%.

There are inherent thresholds based on the High:Width ratio (H:W) that determine costs and challenges in process integration of TSV:

-    10:1 ratio is the limit for the use of relatively inexpensive physical vapor deposition (PVD) for the Cu barrier/seed (B/S),

-    20:1 ratio is the limit for the use of atomic-layer deposition (ALD) for B/S and electroless deposition (ELD) for Cu fill with 1.5 x 30 micron vias on the roadmap for the far future,

-    30:1 ratio and greater is unproven as manufacturable, though novel deposition technologies continue to be explored.

TSV Processing Results

The researchers at imec have evaluated different ways of connecting TSV to underlying silicon, and have determined that direct connections to micro-bumps are inherently superior to use of any re-distribution layer (RDL) metal. Consequently, there is renewed effort on scaling of micro-bump pitches to be able to match up with TSV. The standard minimum micro-bump pitch today of 40 micron has been shrunk to 20, and imec is now working on 10 micron with plans to go to 5 micron. While it may not help with TSV connections, an RDL layer may still be needed in the final stack and the Cu metal over-burden from TSV filling has been shown by imec to be sufficiently reproducible to be used as the RDL metal. The silicon surface area covered by TSV today is a few percents not 10s of percents, since the wiring level is global or semi-global.

Regarding the trade-offs between die-to-wafer (D2W) and wafer-to-wafer (W2W) stacking, D2W seems advantageous for most near-term solutions because of easier design and superior yield. D2W design is easier because the top die can be arbitrarily smaller silicon, instead of the identically sized chips needed in W2W stacks. Assuming the same defectivity levels in stacking, D2W yield will almost always be superior to W2W because of the ability to use strictly known-good-die. Still, there are high-density integration concepts out on the horizon that call for W2W stacking. Monolithic 3D (M3D) integration using re-grown active silicon instead of TSV may still be used in the future, but design and yield issues will be at least comparable to those of W2W stacking.

Beyne mentioned that during the recent ECTC 2015, EV Group showed impressive 250nm overlay accuracy on 450mm wafers, proving that W2W alignment at the next wafer size will be sufficient for 3D stacking. Beyne is also excited by the fact the at this year’s ECTC there was, “strong interest in thermo-compression bonding, with 18 papers from leading companies. It’s something that we’ve been working on for many years for die-to-wafer stacking, while people had mistakenly thought that it might be too slow or too expensive.”

Thermal issues for high-performance circuitry remain a potential issue for 3D stacking, particularly when working with finFETs. In 2D transistors the excellent thermal conductivity of the underlying silicon crystal acts like a built-in heat-sink to diffuse heat away from active regions. However, when 3D finFETs protrude from the silicon surface the main path for thermal dissipation is through the metal lines of the local interconnect stack, and so finFETs in general and stacks of finFETs in particular tend to induce more electro-migration (EM) failures in copper interconnects compared to 2D devices built on bulk silicon.

3D Designs and Cost Modeling

At a recent North California Chapter of the American Vacuum Society (NCCAVS) PAG-CMPUG-TFUG Joint Users Group Meeting discussing 3D chip technology held at Semi Global Headquarters in San Jose, Jun-Ho Choy of Mentor Graphics Corp. presented on “Electromigration Simulation Flow For Chip-Scale Parametric Failure Analysis.” Figure 2 shows the results from use of a physics-based model for temperature- and residual-stress-aware void nucleation and growth. Mentor has identified new failure mechanisms in TSV that are based on coefficient of thermal expansion (CTE) mismatch stresses. Large stresses can develop in lines near TSV during subsequent thermal processing, and the stress levels are layout dependent. In the worst cases the combined total stress can exceed the critical level required for void nucleation before any electrical stressing is applied. During electrical stress, EM voids were observed to initially nucleate under the TSV centers at the landing-pad interfaces even though these are the locations of minimal current-crowding, which requires proper modeling of CTE-mismatch induced stresses to explain.

Fig. 2: Calibration of an Electronic Design Automation (EDA) tool allows for accurate prediction of transistor performance depending on distance from a TSV. (Source: Mentor Graphics)

Planned for July 16, 2015 at SEMICON West in San Francisco, a presentation on “3DIC Technology Past, Present and Future” will be part of one of the side Semiconductor Technology Sessions (STS). Ramakanth Alapati, Director of Packaging Strategy and Marketing, GLOBALFOUNDRIES, will discuss the underlying economic, supply chain and technology factors that will drive productization of 3DIC technology as we know it today. Key to understanding the dynamic of technology adaptation is using performance/$ as a metric.

Samsung to put 10nm chips into mass production by end of 2016

Friday, May 22nd, 2015

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By Jeff Dorsch, Contributing Editor

Samsung Semiconductor on Thursday announced that it will have 10-nanometer FinFET chips in volume production by the end of next year.

At an event in San Francisco, the Samsung Electronics subsidiary exhibited a 12-inch wafer with what it said were 10nm FinFET semiconductors. Over the next 18 months, Samsung will provide process design kits and multi-die wafers for the 10nm FinFET chips.

Samsung Semiconductor is also ramping up volume production of 14nm FinFET chips at its S1 wafer fabrication facility in South Korea and its S2 fab in Austin, Texas, while preparing the S3 fab in South Korea for 14nm FinFET volume production. In addition, GlobalFoundries will implement the Samsung 14nm FinFET process at its chip-making facilities in New York State.

“We are in business for 14-nanometer FinFET,” said Hong Hao, senior vice president for Samsung’s foundry business. “We have brought broad competition back into the foundry business.”

Samsung Foundry has closely matched Taiwan Semiconductor Manufacturing in providing 14nm and now 10nm chips.

Hao said Samsung will support “a broad range of applications” with chips coming out of its foundry fablines – consumer electronics, mobile devices, computing, networking, and data center infrastructure.

He also noted that Samsung is offering a 28nm fully-depleted silicon-on-insulator process, licensed from STMicroelectronics.

Samsung Semiconductor executives made brief presentations on other product areas for the chipmaker, and also reported on progress in constructing the company’s new facility in northern San Jose, Calif., which will be occupied this summer.

Solid State Watch: May 1-8, 2015

Tuesday, May 12th, 2015
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Silicon Summit speakers look at the future of chip technology

Friday, April 17th, 2015
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Gregg Bartlett

By Jeff Dorsch, Contributing Editor

Quick quiz: What topics do you think were discussed at length Wednesday at the Global Semiconductor Alliance’s Silicon Summit?

A. The Internet of Things.

B. Augmented reality and virtual reality.

C. Cute accessories for spring and summer looks.

The answers: A and B. C could be right if you count wearable electronics as “cute accessories.”

Wednesday’s forum at the Computer History Museum in Mountain View, Calif., not far from  Google’s headquarters, was dominated by talk of IoT, AR, VR, and (to a lesser extent) wearable devices.

Gregg Bartlett, senior vice president of the Product Management Group at GlobalFoundries, kicked off the morning sessions with a talk titled “IoT: A Silicon Perspective.” He said, “A lot of the work left in IoT is in the edge world.”

Bartlett noted, “A lot of the infrastructure is in place,” yet the lack of IoT standards is inhibiting development, he asserted.

“IoT demands the continuation of Moore’s Law,” Bartlett said, touting fully-depleted silicon-on-insulator technology as a cost-effective alternative to FinFET technology. FD-SOI “is the killer technology for IoT,” he added.

Next up was James Stansberry, senior vice president and general manager of IoT Products at Silicon Laboratories. Energy efficiency is crucial for IoT-related devices, which must be able to operate for 10 years with little or no external power, he said.

Bluetooth Smart, Thread, Wi-Fi, and ZigBee provide the connectivity in IoT networks, with a future role for Long-Term Evolution, according to Stansberry. He also played up the importance of integration in connected devices. “Nonvolatile memory has to go on the chip” for an IoT system-on-a-chip device, he said.

For 2015, Stansberry predicted a dramatic reduction in energy consumption for IoT devices; low-power connectivity standards will gain traction; and the emergence of more IoT SoCs.

Rahul Patel, Broadcom’s senior vice president and general manager of wireless connectivity, addressed health-care applications for the IoT. “Security is key,” he said. Reliability, interoperability, and compliance with government regulations are also required, Patel noted.

“My agenda is to scare everyone to death,” said Martin Scott, senior vice president and general manager of the Cryptography Research Division at Rambus. Cybersecurity with the IoT is causing much anxiety, he noted. “Silicon can come to the rescue again,” he said. “If your system relies on software, it’s hackable.”

To build trust in IoT devices and networks, the industry needs to turn to silicon-based security, according to Scott. “Silicon is the foundation of trusted services,” he concluded.

The second morning session was titled “The Future of Reality,” with presentations by Keith Witek, corporate vice president, Office of Corporate Strategy, Advanced Micro Devices; Mats Johansson, CEO of EON Reality; and Joerg Tewes, CEO of Avegant.

Augmented reality and virtual reality technology is “incredibly exciting,” Witek said. “I love this business.” He outlined four technical challenges for VR in the near future: Improving performance; ensuring low latency of images; high-quality consistency of media; and system-level advances. “Wireless has to improve,” Witek said.

VR is “starting to become a volume market,” Johansson said. What matters now is proceeding “from phone to dome,” where immersive experiences meet knowledge transfer, he added. Superdata, a market research firm, estimates there will be 11 million VR users by next year, according to Johansson.

Avegant had a successful Kickstarter campaign last year to fund its Glyph VR headset, with product delivery expected in late 2015, Tewes said. The Glyph has been in development for three years, he said, employing digital micromirror device technology, low-power light-emitting diodes, and latency of less than 12 microseconds to reduce or eliminate the nausea that some VR users have experienced, he said.

The afternoon session was devoted to “MEMS and Sensors, Shaping the Future of the IoT.” Attendees heard from Todd Miller, Microsystems Lab Manager at GE Global Research; Behrooz Abdi, president and CEO of InvenSense; Steve Pancoast, Atmel’s vice president of software and applications; and David Allan, president and chief operating officer of Virtuix.

Miller outlined the challenges for the industrial Internet – cybersecurity, interoperability, performance, and scale. “Open standards need to continue,” he said.

General Electric and other companies, including Intel, are involved in the Industrial Internet Consortium, which is developing use cases and test beds in the area, according to Miller.

He noted that GE plans to begin shipping its microelectromechanical system devices to external customers in the fourth quarter of this year.

Abdi said, “What is the thing in the Internet of Things? The IoT is really about ambient computing.” IoT sensors must continuously answer these questions: Where are you, what are you doing, and how does it feel, he said.

The IoT will depend upon “always on” sensors, making it more accurate to call the technology “the Internet of Sensors,” Abdi asserted. He cautioned against semiconductor suppliers getting too giddy about business prospects for the IoT.

“You’re not going to sell one billion sensors for a buck [each],” Abdi said.

Pancoast of Atmel said sensors would help provide “contextual computing” in IoT networks. “Edge/sensing nodes are a major part of IoT,” he noted. Low-power microcontrollers and microprocessors are also part of the equation, along with “an ocean of software” and all IoT applications, Pancoast added. He finished with saying, “All software is vulnerable.”

Allan spoke about what he called “the second machine age,” with the first machine age dating to 1945, marking the advent of the stored-program computer and other advances. “The smartphone is the first machine of the second machine age,” he said.

IoT involves wireless sensor networks and distributed computing, he said. Google has pointed the way over the past decade, showing how less-powerful computers, implemented in large volumes, have become the critical development in computing, Allan noted. Because of this ubiquity of distributed computing capabilities, “Moore’s Law doesn’t matter as much,” he said.

With the IoT, “new machines will augment human desires,” Allan predicted, facilitating such concepts as immortality, omniscience, telepathy, and teleportation. He explained how technology has helped along the first three – we know what people are thinking through Facebook and Twitter – and the last is just a matter of time, according to Allan.

Solid State Watch: March 20-26, 2015

Thursday, March 26th, 2015
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Blog review March 9, 2015

Monday, March 9th, 2015

Pete Singer is delighted to announce the keynotes and other speakers for The ConFab 2015, to be held May 19-22 at The Encore at The Wynn in Las Vegas. The line-up includes Ali Sebt, President and CEO of Renesas America, Paolo Gargini, Chairman of the ITRS and Subramani Kengeri, Vice President, Global Design Solutions at GLOBALFOUNDRIES.

Mark Simmons, Product Marketing Manager, Calibre Manufacturing Group, Mentor Graphics writes about cutting fab costs and turn-around time with smart, automated resource management. He notes that the competition for market share is brutal for both the pure-play and independent device manufacturer (IDM) foundries. Success involves tuning a lot of knobs and dials. One of the important knobs is the ability to continually meet or exceed aggressive time-to-market schedules.

Paul Stockman, Commercialization Manager, Linde Electronics blogs that there is an increasing demand for and focus on sustainable manufacturing that will contribute to a greening of semiconductors. This greening must be robust and responsive to change and cannot constrain the individual processes or operation of a fab.

Applied Materials’ Max McDaniel writes on the quest for more durable displays. He says the same innovators who created such amazingly thin, light and highly functional smartphones (with the help of Applied Materials display technology) are already developing durability improvements that may eliminate the need for protective covers.

Batteries? We don’t need no stinking batteries, says Ed Korczynski. We’re still used to thinking that low-power chips for “mobile” or “Internet-of-Things (IoT)” applications will be battery powered…but the near ubiquity of lithium-ion cells powering batteries could be threatened by capacitors and energy-harvesting circuits connected to photovoltaic/thermoelectric/piezoelectric micro-power sources.

With the 2015 SPIE Advanced Lithography (AL) conference around the corner, some people have asked me what remaining EUVL challenges need to be addressed to ensure it will be ready for mass production later this year or next.  Vivek Bakshi of EUV Litho, Inc. provides thoughts on this topic and what he expects to hear at the conference.

Phil Garrou continues his look at presentations from the Grenoble SEMI 3D Summit which took place in January, focusing on an interesting presentation by ATREG consultants on the future of Assembly & Test.

On Tuesday, January 20, President Obama once again stood before a joint session of Congress to deliver a State of the Union Address.  With the newly seated Republican-controlled Congress and his Cabinet present, the President discussed topics ranging from the current state of the economy to foreign affairs and his ideas on how to move the nation forward.  Jamie Girard of SEMI was pleased to hear that the President supported multiple policy goals including expansion of free trade, corporate tax reform, support for basic science research and development and others.

Solid State Watch: February 13-19, 2015

Friday, February 20th, 2015
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5nm Node Needs EUV for Economics

Thursday, January 29th, 2015

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By Ed Korczynski, Sr. Technical Editor

#mce_temp_url#

At IEDM 2014 last month in San Francisco, Applied Materials sponsored an evening panel discussion on the theme of “How do we continue past 7nm?” Given that leading fabs are now ramping 14nm node processes, and exploring manufacturing options for the 10nm node, “past 7nm” means 5nm node processing. There are many device options possible, but cost-effective manufacturing at this scale will require Extreme Ultra-Violet (EUV) lithography to avoid the costs of quadruple-patterning.

Fig. 1: Panelists discuss future IC manufacturing and design possibilities in San Francisco on December 16, 2014. (Source: Pete Singer)

Figure 1 shows the panel being moderated by Professor Mark Rodwell of the University of California Santa Barbara, composed of the following industry experts:

  • Karim Arabi, Ph.D. – vice president, engineering, Qualcomm,
  • Michael Guillorn, Ph.D. – research staff member, IBM,
  • Witek Maszara, Ph.D. – distinguished member of technical staff, GLOBALFOUNDRIES,
  • Aaron Thean, Ph.D. – vice president, logic process technologies, imec, and
  • Satheesh Kuppurao, Ph.D. – vice president, front end products group, Applied Materials.

Arabi said that from the design perspective the overarching concern is to keep “innovating at the edge” of instantaneous and mobile processing. At the transistor level, the 10nm node process will be similar to that at the 14nm node, though perhaps with alternate channels. The 7nm node will be an inflection point with more innovation needed such as gate-all-around (GAA) nanowires in a horizontal array. By the 5nm node there’s no way to avoid tunnel FETs and III-V channels and possibly vertical nanowires, though self-heating issues could become very challenging. There’s no shortage of good ideas in the front end and lots of optimism that we’ll be able to make the transistors somehow, but the situation in the backend of on-chip metal interconnect is looking like it could become a bottleneck.

Guillorn extolled the virtues of embedded-memory to accelerate logic functions, as a great example of co-optimization at the chip level providing a real boost in performance at the system level. The infection at 7nm and beyond could lead to GAA Carbon Nano-Tube (CNT) as the minimum functional device. It’s limited to think about future devices only in terms of dimensional shrinks, since much of the performance improvement will come from new materials and new device and technology integration. In addition to concerns with interconnects, maintaining acceptable resistance in transistor contacts will be very difficult with reduced contact areas.

Maszara provided target numbers for a 5nm node technology to provide a 50% area shrink over 7nm:  gate pitch of 30nm, and interconnect level Metal 1 (M1) pitch of 20nm. To reach those targets, GLOBALFOUNDRIES’ cost models show that EUV with ~0.5 N.A. would be needed. Even if much of the lithography could use some manner of Directed Self-Assembly (DSA), EUV would still be needed for cut-masks and contacts. In terms of device performance, either finFET or nanowires could provide desired off current but the challenge then becomes how to get the on current for intended mobile applications? Alternative channels with high mobility materials could work but it remains to be seen how they will be integrated. A rough calculation of cost is the number of mask layers, and for 5nm node processing the cost/transistor could still go down if the industry has ideal EUV. Otherwise, the only affordable way to go may be stay at 7nm node specs but do transistor stacking.

Thein detailed why electrostatic scaling is a key factor. Parasitics will be extraordinary for any 5nm node devices due to the intrinsically higher number of surfaces and junctions within the same volume. Just the parasitic capacitances at 7nm are modeled as being 75% of the total capacitance of the chip. The device trend from planar to finFET to nanowires means proportionally increasing relative surface areas, which results in inherently greater sensitivity to surface-defects and interface-traps. Scaling to smaller structures may not help you if you loose most of the current and voltage in non-useful traps and defects, and that has already been seen in comparisons of III-V finFETs and nanowires. Also, 2D scaling of CMOS gates is not sustainable, and so one motivation for considering vertical transistors for logic at 5nm would be to allow for 20nm gates at 30nm pitch.

Kappurao reminded attendees that while there is still uncertainty regarding the device structures beyond 7nm, there is certainty in 4 trends for equipment processes the industry will need:

  1. everything is an interface requiring precision materials engineering,
  2. film depositions are either atomic-layer or selective films or even lattice-matched,
  3. pattern definition using dry selective-removal and directed self-assembly, and
  4. architecture in 3D means high aspect-ratio processing and non-equilibrium processing.

An example of non-equilibrium processing is single-wafer rapid-thermal-annealers (RTA) that today run for nanoseconds—providing the same or even better performance than equilibrium. Figure 2 shows that a cobalt-liner for copper lines along with a selective-cobalt cap provides a 10x improvement in electromigration compared to the previous process-of-record, which is an example of precision materials engineering solving scaling performance issues.

Fig. 2: ElectroMigration (EM) lifetimes for on-chip interconnects made with either conventional Cu or Cu lined and capped with Co, showing 10 times improvement with the latter. (Source: Applied Materials)

“We have to figure out how to control these materials,” reminded Kappurao. “At 5nm we’re talking about atomic precision, and we have to invent technologies that can control these things reliably in a manufacturable manner.” Whether it’s channel or contact or gate or interconnect, all the materials are going to change as we keep adding more functionality at smaller device sizes.

There is tremendous momentum in the industry behind density scaling, but when economic limits of 2D scaling are reached then designers will have to start working on 3D monolithic. It is likely that the industry will need even more integration of design and manufacturing, because it will be very challenging to keep the cost-per-function decreasing. After CMOS there are still many options for new devices to arrive in the form of spintronics or tunnel-FETs or quantum-dots.

However, Arabi reminded attendees as to why the industry has stayed with CMOS digital synchronous technology leading to design tools and a manufacturing roadmap in an ecosystem. “The industry hit a jackpot with CMOS digital. Let’s face it, we have not even been able to do asynchronous logic…even though people tried it for many years. My prediction is we’ll go as far as we can until we hit atomic limits.”

Solid State Watch: December 12-19, 2014

Saturday, December 20th, 2014
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Solid State Watch: October 31-November 6, 2014

Monday, November 10th, 2014
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