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GLOBALFOUNDRIES and Samsung join forces on 14nm finFETs

Thursday, April 17th, 2014

By Ed Korczynski and Pete Singer, SemiMD and Solid State Technology

Fabless companies could skip the 20nm node and move straight to 14nm FinFETs. That is the hope of GLOBALFOUNDRIES and Samsung who are announcing a joint program that offers a single process design kit (PDK) and manufacturing at four different fabs with identical processes.The PDKs are available now, and 14nm manufacturing could move into high volume production by the end of the year.

This is unprecedented,” said Kelvin Low, senior director of marketing at Samsung. “It never has happened in the industry, especially at the very leading edge nodes. We are confident that this will transform the supply chain model,” he added.

Fabless companies such as Qualcomm have been lobbying for such multi-sourcing for some time, and are eager to move to FinFETs which offer higher performance and reduced power consumption. The 14nm FinFET offer a 20% improvement in performance and a 35% reduction in power compared to 20nm technology.

“For both Samsung and GLOBALFOUNDRIES, we will be providing our customers with a choice and assurances of supply, enabled by the unprecedented global capacity across our respective manufacturing facilities throughout different locations worldwide,” Low said. “For Samsung, we have facilities in the U.S. in Austin. We also have a couple of plants in Korea. For GLOBALFOUNDRIES, the 14 nm capacity will be in Malta, NY.”


The single process design kit will allow customers to do a single design that is capable of being multi-sourced from different locations.

“This really is a change from the existing supply chain model where customers are trying to design multiple designs to multi-source their products,” Low said. “True design compatibility in this collaboration will allow customers to better manage their design NRE and they can focus on bringing the product to market on time. Both companies see this as a necessary advancement of the supply chain model and we start off with the 14nm LPE as well as the 14nm LPP technology node.” 14nm LPP is a follow-on offering which has additional performance enhancements as well as power reduction attributes.

Samsung had already developed much of the process technology for LPP and LPE flows to run using 14nm node finFETs, while GLOBALFOUNDRIES was working independently on another 14nm node process variant. The two companies decided to pool resources to save both time and money in bringing 14nm node finFET capability to the commercial IC foundry market.

Because of customer interest in having that assurance of supply and being able to do one GDS and being able to work off of one common PDK and source at both of our companies, we decided to work together and go with the 14 LPE and 14 LPP as common offerings between Samsung and GLOBALFOUNDRIES,” said Ana Hunter, VP of product management at GLOBALFOUNDRIES.

Low said that Samsung is already running 14nm products in its fab in Korea. The 14nm LPE, for example, was qualified earlier this year.

“We are already in silicon validation of our lead customer products. We expect to ramp production by the end of this year,” he said. Design activities started almost three years ago. “Right now, we are seeing a lot more pickup overall by the lead adopters and even other customers following suit, mainly because the marketplace does see that the 14nm FinFET is at the right maturity level for volume production,” Low said.

Although there is still lot of activity at 28nm, the technology is considered to be in a mature phase. “We still continue to see healthy, new design-ins,” Low said. “Of course, there are a lot of requests to see what additional enhancements we can do at our 28nm node to prolong the lifespan of that node.”

What about 20nm? “From Samsung’s viewpoint, we see that a relatively short-lived node, mainly because of the overall resonance of FinFETs and the eagerness of customers to migrate from 28nm directly to 14nm FinFETs.”

Hunter agrees, noting that 28nm has been in high volume production for several years now. She said GLOBALFOUNDRIES does have 20nm product tapeouts running in the line, but said that she does not see 20nm being a very extensive node in that most customers are eager to get onto FinFETs.

“We do have products running at 20nm, but I think the design efforts will quickly go over to FinFET and we’ll see that be a much longer lived node with a lot more product tapeouts,” she said.

The companies say the 14nm FinFET offering could be up to 15% smaller than that available from other foundries due to aggressive gate pitch, smaller memory solution and innovative layout schemes for compact logic.


Hunter, having been a VP at Samsung before holding her current position at GLOBALFOUNDRIES, noted that the two companies, along with IBM, have been in collaboration for quite some time on “The Common Platform” at 65, 45, and 28nm nodes, but this announcement is strictly between GF and Samsung.

“We do continue to work with IBM in other areas at the Albany Nanotech center, where there is continuing collaboration on more advanced nodes, on materials research, pathfinding, and advanced module development kind of work,” she said.

Fabless customers use a single PDK to do a single design, allowing a single GDS file to be sent to either company. The design-for-manufacturing (DFM) and reticle-enhancement technologies (RET) needed at the 14nm node are challenging.

“We go deep into the collaboration, even to the OPC level and a lot of sharing on DFM as well. It is a very extensive collaboration,” confirmed Hunter. “At 14nm the designs are extremely complex, and to be able to truly supply multi-sourcing from one GDS, you have to have that level of collaboration to ensure that the output from all of our factories is the same. That’s a huge advantage to customers because the idea that you could source from two different companies without the kind of collaboration that GLOBALFOUNDRIES and Samsung are doing is just simply impossible when you get into 14nm FinFETs. When you get into the complexity of the designs, the databases, the amount of reticle enhancement techniques that are required to be able to print these geometries, you need to have that kind of in-depth collaboration.”

Low said that the two companies have a “fabsync” structure running in the background to ensure the fabs are fully synchronized.

“There are a couple of things we are doing proactively,” he said. “The technology teams are deeply engaged with each other. We have technology workshops across both companies. We have test chips that are run regularly to ensure that the process continues to stay synchronized. These test chips are not just simple transistors. We have product level elements that we’ve included to make sure we measure the critical parameters. This is only enabled through open sharing of technology information.”

Hunter adds: “We run the same test chips, we share wafers back and forth to measure each other’s products to make sure all of our equipment is calibrated, test equipment calibrated, results are the same on exactly the same test chip.We have test-chips with product-level structures that run in all fabs and both companies share all data to ensure that all fabs stay in alignment. Not just SPICE models and SRAMs, but full chip-like design features.”

However, customers will have to re-do lithography masks if they want to move manufacturing from one company to the other, in part because of issues with shipping masks. Kevin Low, Samsung’s senior director of marketing, commented, “We’ll be providing our customers choice and secure supply. At Samsung we have capacity in Texas and Korea.”

Cost/transistor for 14nm may not be lower compared to 20nm and 28nm. Hunter said, “To continue with optical lithography, it is challenging to do double-patterning and keep costs low.” However, since much of the motivation in moving from 20nm to 14nm is for power-sipping mobile SoCs, by reducing the power consumption by the claimed 35% there could be cost-savings at the packaging level such that the overall product cost is reduced.

To be able to offer essentially the same manufacturing process to customers, GLOBALFOUNDRIES and Samsung had to harmonize not just process recipes but many of the OEM tools used in these fabs.

Hunter says, “To get the same results at this node, it does require engineering down to the tool level and the individual recipe level. That doesn’t mean all tools are exactly the same, however, since cost and availability of tools may have been different when the fabs were equipped.”

Customers can choose which foundry that choose to work with, and then they can choose to discuss commercial terms such as which specific foundry site may be booked to do the work.

Blog review April 7, 2014

Monday, April 7th, 2014

Pete Singer reveals the lineup of presenters for Session 1 of The ConFab, to be held June 22-25 in Las Vegas, and provides summaries of their talks. Speakers will be Vijay Ullal, COO, Fairchild Semiconductor; Dave Anderson, President and CEO, Novati Technologies; Gopal Rao, Senior Director Business Development, SEMATECH; Adrian Maynes, Program Manager, F450C; and Bill McClean, President, IC Insights.

Phil Garrou blogs about a variety of diverse issues this week, including GLOBALFOUNDRIES’ potential purchase of IBM’s semiconductor business, Altera’s separate deals with Intel and TSMC, why FinFET could be more expensive that more conventional CMOS strategies, as view by Handle Jones of IBS, and a new joint development program between ASE and Inotera focused on 3D IC packaging.

Blog review March 17, 2014

Monday, March 17th, 2014

Pete Singer is delighted to report that Dr. Roawen Chen, Senior Vice Present of global operations at Qualcomm, has accepted our invitation to deliver the keynote talk at The ConFab, on Monday June 23rd. As previously announced, Dr. Gary Patton, Vice President of IBM’s Semiconductor Research and Development Center in East Fishkill, New York, will deliver the keynote on the second day, on Tuesday June 24th.

Phil Garrou takes a look at what was reported at SEMI’s 2.5/3D IC Summit held in Grenoble, focusing on presentations from Gartner, GLOBALFOUNDRIES, TSMC and imec. He writes that GLOBALFOUNDRIES has been detailing their imminent commercialization of 2.5/3D IC for several years, and provide a chart showing the current status report. TSMC offered a definition of their supply chain model where OSATS are now integrated.

Bharat Ramakrishnan of Applied Materials writes about the importance of wearable electronics in the Internet of Things (IoT) era, and the role that precision materials engineering will play. He note that one key part of the wearables ecosystem that is still in need of new innovations is the battery. Two of the biggest challenges to overcome are the thick form factor due to battery size, and the lack of adequate battery life, thus requiring frequent recharging.

Solid State Watch: February 21-28, 2014

Friday, February 28th, 2014
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Blog Review: November 25, 2013

Monday, November 25th, 2013

Zvi Or-Bach, president and CEO of MonolithIC 3D, blogs about a recent announcement by Intel CEO Brian Krzanich on company expansion focused on a foundry plan. Or-Bach said that if Intel could keep the traditional 30% cost reduction per node from 28nm to 10nm, and the foundry’s cost per transistor is staying flat, then Intel would be able to provide their foundry customers SoC products at a third of the other foundries cost, and accordingly Intel should be able to do very well in its foundry business.

Vivek Bakshi, EUV Litho, Inc. reports on work presented at the 2013 Source Workshop (Nov 3-7, 2013, Dublin, Ireland), including data on the readiness of 50 W EUV sources to support EUVL scanners. At the meeting, keynoter Vadim Banine of ASML said that 50 W EUV sources have now demonstrated good dose control and are now available for deployment in the field. ASML also presented data on the feasibility of source power of 175 W at the first focus (720 W at source), and utilizing new, protective cap layers to give collectors six months of life.

At the GaTech Global Interposer Technology Workshop (GIT) in Atlanta, the pervasive theme appeared to be whether a change in substrate is required to lower overall costs and help drive HVM (high volume manufacturing) applications. Phil Garrou reports on the workshop, including presentations from Ron Huemoeller of Amkor and David McCann of GLOBALFOUNDRIES.

Pete Singer provides a preview of a special focus session at the upcoming IEEE International Electron Devices Meeting (IEDM), scheduled for December 9 – 11, 2013. The session covers many of today’s hot topics: memory, LEDs, silicon photonics, interposers, SOI finFETS and 450mm.

Dr. Lianfeng Yang of ProPlus Design Solutions, Inc., blogs that these days, circuit designers are talking about the increasing giga-scale circuit size. Semiconductor CMOS technology downscaled to nano-scale, forcing the move to make designing for yield (DFY) mandatory and compelling them to re-evaluate how they design and verify their chips.

The Week in Review: Nov. 22, 2013

Friday, November 22nd, 2013

GLOBALFOUNDRIES, Open-Silicon and Amkor Technology have jointly exhibited a functional system-on-chip (SoC) solution on a 2.5D silicon interposer featuring two 28nm logic chips, with embedded ARM processors. The jointly developed design is a test vehicle that showcases the benefits of 2.5D technology for mobile and low-power server applications. The companies recently demonstrated the functioning SoC at ARM TechCon in Santa Clara, CA.

North America-based manufacturers of semiconductor equipment posted $1.12 billion in orders worldwide in October 2013 (three-month average basis) and a book-to-bill ratio of 1.05, according to the October EMDS Book-to-Bill Report published this week by SEMI.   A book-to-bill of 1.05 means that $105 worth of orders were received for every $100 of product billed for the month. “Both equipment orders and billings improved in the October data, resulting in a book-to-bill ratio returning above parity,” said Denny McGuirk, president and CEO of SEMI.  ”Order activity is well above the figures reported one year ago and point towards on-going investments in advanced process technologies for NAND Flash, microprocessor, and foundry.”

Soraa, a developer of GaN on GaN LED technology, announced that it will open a new semiconductor fabrication plant in Buffalo, New York. In partnership with the State of New York, the company will construct a new state-of-the-art GaN on GaN LED fabrication facility that will employ hundreds of workers. The new facility is projected to be operational in 2015. Soraa currently operates an LED fabrication plant in Fremont, California, one of only a few in the US.

Dow Corning introduced new Dow Corning MS-2002 Moldable White Reflector Silicone at Strategies in Light Europe 2013. This highly reflective white material extends the excellent photo-thermal stability and high-moldability that typifies Dow Corning’s award-winning optical-grade Moldable Silicone family to the reflective elements of LED lamp and luminaire applications. Dow Corning MS-2002 Moldable White Reflector Silicone targets reflectivity as high as 98 percent to help further boost light output from LED devices, improve overall energy efficiency and prolong device reliability.

SUSS MicroTec, a global supplier of equipment and process solutions for the semiconductor industry and related markets, has successfully installed an ELP300 excimer laser stepper to support next generation advanced packaging and 3D IC laser debonding applications at the Fraunhofer Institute for Reliability and Microintegration (IZM), Berlin. The ELP300 excimer laser platform is designed for high volume manufacturing and processing of 100mm to 300mm wafers.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, introduced the EVG PHABLE exposure system, which is designed specifically for manufacturing photonic components.  Leveraging EVG’s expertise in photolithography, the EVG PHABLE system incorporates a unique contactless lithography mask-based approach that enables full-field, high-resolution and cost-efficient micro- and nanopatterning of passive and active photonic components, such as patterned structures on light emitting diode (LED) wafers, in high-throughput production environments.

GLOBALFOUNDRIES, Open-Silicon and Amkor demo 2.5D test vehicle

Friday, November 22nd, 2013

GLOBALFOUNDRIES, Open-Silicon and Amkor Technology have jointly exhibited a functional system-on-chip (SoC) solution on a 2.5D silicon interposer featuring two 28nm logic chips, with embedded ARM processors. The jointly developed design is a test vehicle that showcases the benefits of 2.5D technology for mobile and low-power server applications. The companies recently demonstrated the functioning SoC at ARM TechCon in Santa Clara, CA.

The test vehicle features two ARM Cortex-A9 processors manufactured using GLOBALFOUNDRIES’ 28nm-SLP (Super Low Power) process technology. The processors are attached to a silicon interposer, which is built on a 65nm manufacturing flow with through-silicon-vias (TSVs) to enable high-bandwidth communication between the chips.

Open-Silicon provided the processor, interposer, substrate, and test design, as well as the test and characterization of the final product. GLOBALFOUNDRIES provided the PDKs (process design kits), interposer reference flow and manufactured both the 28nm ARM processors and the 65nm silicon interposer with embedded TSVs. Amkor provided the package-related design rules and manufacturing processes for back-side integration, copper pillar micro-bumping, and 2.5D product assembly. GLOBALFOUNDRIES and Amkor collaborated closely throughout the project to develop and validate the design rules, assembly processes, and required material sets.

The companies developed the custom SoC to help overcome some of the challenges associated with bringing 2.5D technology to market. The 2.5D system features the following characteristics:

· Logic die including dual-core ARM Cortex-A9 CPUs, as well as DDR3, USB and AXI bridge interfaces

· A special EDA reference flow designed to address the additional requirements of 2.5D design, including top-level interposer design creation and floor planning, as well as the increased complexity of using TSVs, front-side and back-side bumps, and redistribution layer (RDL) routing

· Support for additional verification steps brought on by 2.5D design rules

· Custom die-to-die IO for better area and power characteristics providing a maximum of 8GB/s full-duplex data-rate across the two die through the silicon interposer

· A development board with memory, boot-ROM, and basic peripherals to demonstrate the die-to-die interface functionality through software running on the CPUs embedded in the logic dies

· A test methodology consisting of Boundary Scan and Loopback modes

· Package-related design rules, back-side integration, copper pillar micro-bumping, and 2.5D product assembly by Amkor Technology, a leading supplier of outsourced semiconductor packaging and test services.

GLOBALFOUNDRIES said this demonstrates the value of its open and collaborative approach to delivering next-generation chip packaging technologies, which it calls “Foundry 2.0,” which is aimed at enabling an open supply chain through collaboration with ecosystem partners and customers. This approach allows GLOBALFOUNDRIES’ customers to choose their preferred supply chain partners, while leveraging the experience of ecosystem partners who have developed deep expertise in design, assembly and test methodologies. This open and collaborative model is expected to deliver lower overall cost and less risk in bringing 2.5D technologies to market.

“As the fabless-foundry business model evolves to address the realities of today’s dynamic market, foundries are taking on increasing responsibility for enabling the supply chain to deliver end-to-end solutions that meet the requirements of the broad range of leading-edge designs,” said David McCann, vice president of packaging R&D at GLOBALFOUNDRIES. “To help address these challenges, we are driving our ‘Foundry 2.0’ collaborative supply chain model by engaging early with ecosystem partners like Open-Silicon and Amkor to jointly develop solutions that will enable the next wave of innovation in the industry.”

The companies demonstrated first-time functionality of the processor, interposer, and substrate designs, and the die-to-substrate (D2S) process used by the supply chain resulted in high yields. The design tools, process design kit (PDK), design rules, and supply chain are now in place and proven for 2.5D interposer products from GLOBALFOUNDRIES, Amkor, and Open-Silicon.

“This project is a testament to the value of an open and collaborative approach to innovation, leveraging expertise from across the supply chain to demonstrate progress in bringing a critical enabling technology to market,” said Ron Huemoeller, senior vice president of advanced product development at Amkor Technology. “This collaborative model will offer chip designers a flexible approach to 2.5D SoC designs, while delivering cost savings, faster time-to-volume, and a reduction in the technical risk associated with developing new technologies.”

“We are pleased to be at the forefront of making 2.5D a reality with our foundry and OSAT partners,” said Dr. Shafy Eltoukhy, vice president of technology development at Open-Silicon. “This approach will allow designers to choose the right technology for each function of their SoC while simultaneously enabling finer grain and lower power connectivity than traditional packaging solutions along with reduced power budgets for next-generation electronic devices.”

Blog Review November 18 2013

Monday, November 18th, 2013

Dick James of Chipworks says that 28-nm samples they have seen from GLOBALFOUNDRIES and Samsung are remarkably similar, and ponders the possibility of Apple’s A7 chips being fabricated in New York in the not too distant future.

Recent progress in silicon photonics and optical interconnects is the focus of Pete Singer’s blog. Fujitsu and Intel recently demonstrated the world’s first Optical PCIe Express (OPCIe) based server, using Intel’s silicon photonics chip. Ludo Deferm of imec talks about what’s’ needed for intrachip optical communication.

Rich Wawrzyniak of Semico talks about what he learned from a discussion with Sundar Iyer, CEO of Memoir Systems, on the company’s new Pattern Aware Memory IP technology. Memoir has identified several different types of memory-processor operations and has created memories that perform these functions in the normal course of their operation within the system. In addition, this approach can save designers and device architects a considerable amount of die area, producing tangible power savings while increasing device performance.

Phil Garrou covers three new developments in the area of 3D integration this week. He looks at work from Leti/ST Microelectronics that explored the limits of conventional interconnects on RDL (vs damascene). They were able to achieve 8 µm line/spaces with high uniformity and reproducibility. He also reports on work from BESI and imec on thin wafer handling, and a new low temp via reveal process developed by SPTS.

Design for Yield Trends

Tuesday, November 12th, 2013

By Sara Ver-Bruggen

Should foundries establish and share best practices to manage sub-nanometer effects to improve yield and also manufacturability?

Team effort

Design for yield (DFY) has been referred to previously on this site as the gap between what the designers assume they need in order to guarantee a reliable design and what the manufacturer or foundry thinks they need from the designer to be able to manufacture the product in a reliable fashion. Achieving and managing this two-way flow of information becomes more challenging as devices in high volume manufacturing have 28 nm dimensions and the focus is on even smaller dimension next-generation technologies. So is the onus on the foundries to implement DFY and establish and share best practices and techniques to manage sub-nanometer effects to improve yield and also manufacturability?

Read more: Experts At The Table: Design For Yield Moves Closer to the Foundry/Manufacturing Side

‘Certainly it is in the vital interest of foundries to do what it takes to enable their customers to be successful,’ says Mentor Graphics’ Senior Marketing Director, Calibre Design Solutions, Michael Buehler, adding, ‘Since success requires addressing co-optimization issues during the design phase, they must reach out to all the ecosystem players that enable their customers.’

Mentor refers to the trend of DFY moving closer to the manufacturing/foundry side as ‘design-manufacturing co-optimization’, which entails improving the design both to achieve higher yield and to increase the performance of the devices that can be achieved for a given process.

But foundries can’t do it alone. ‘The electronic design automation (EDA) providers, especially ones that enable the critical customer-to-foundry interface, have a vital part in transferring knowledge and automating the co-optimization process,’ says Buehler. IP suppliers must also have a greater appreciation for and involvement in co-optimization issues so their IP will implement the needed design enhancements required to achieve successful manufacturing in the context of a full chip design.

As they own the framework of DFY solutions, foundries that will work effectively with both the fabless and the equipment vendors will benefit from getting more tailored DFY solutions that can lead to shorter time-to-yield, says Amiad Conley, Applied Materials’ Technical Marketing Manager, Process Diagnostics and Control. But according to Ya-Chieh Lai, Engineering Director, Silicon and Signoff Verification, at Cadence, the onus and responsibility is on the entire ecosystem to establish and share best practices and techniques. ‘We will only achieve advanced nodes through a partnership between foundries, EDA, and the design community,’ says Ya-Chieh.

But whereas foundries are still taking the lead when it comes to design for manufacturability (DFM), for DFY the designer is intimately involved so he is able to account for optimal trade-off in yield versus PPA that result in choices for specific design parameters, including transistor widths and lengths.

For DFM, foundries are driving design database adjustments required to make a particular design manufacturable with good yield. ‘DFM modifications to a design database often happen at the end of a designer’s task. DFM takes the “ideal” design database and manipulates it to account for the manufacturing process,’ explains Dr Bruce McGaughy, Chief Technology Officer and Senior Vice President of Engineering at ProPlus Design Solutions.

The design database that a designer delivers must have DFY considerations to be able to yield. ‘The practices and techniques used by different design teams based on heuristics related to their specific application are therefore less centralized. Foundries recommend DFY reference flows but these are only guidelines. DFY practices and techniques are often deeply ingrained within a design team and can be considered a core competence and, with time, a key requirement,’ says McGaughy.

In the spirit of collaboration

Ultimately, as the industry continues to progress requiring manufacturing solutions that increasingly tailored and more and more device specific, this requires earlier and deeper collaboration between equipment vendors and foundry customers in defining and developing the tailored solutions that will maximize the performance of equipment in the fab. ‘It will also potentially require more three-way collaboration between the designers from fabless companies, foundries, and equipment vendors with the appropriate IP protection,’ says Conley.

A collaborative and open approach between the designer and the foundry is critical and beneficial for many reasons. ‘Designers are under tight pressures schedule-wise and any new steps in the design flow will be under intense scrutiny. The advantages of any additional steps must be very clear in terms of the improvement in yield and manufacturability and these additional steps must be in a form that designers can act on,’ says Ya-Chieh. The recent trend towards putting DFM/DFY directly into the design flow is a good example of this. ‘Instead of purely a sign-off step, DFM/DFY is accounted for in the router during place and route. The router is able to find and fix hotspots during design and, critically, to account for DFM/DFY issues during timing closure,’ he says. Similarly, Ya-Chieh refers to DFM/DFY flows that are now in place for custom design and library analysis. ‘Cases of poor transistor matching due to DFM/DFY issues can be flagged along with corresponding fixing guidelines. In terms of library analysis, standard cells that exhibit too much variability can be systematically identified and the cost associated with using such a cell can be explicitly accounted for (or that cell removed entirely).’

‘The ability to do “design-manufacturing co-optimization” is dependent on the quality of information available and an effective feedback loop that involves all the stakeholders in the entire supply chain: design customers, IP suppliers, foundries, EDA suppliers, test vendors, and so on,’ says Buehler. ‘This starts with test chips built during process development, but it must continue through risk manufacturing, early adopter experiences and volume production ramping. This means sharing design data, process data, test failure diagnosis data and field failure data,’ he adds.

A pioneer of this type of collaboration was the Common Platform Consortium initiated by IBM. Over time, foundries have assumed more of the load for enabling and coordinating the ecosystem. ‘GLOBALFOUNDRIES has identified collaboration as a key factor in its overall success since its inception and been particularly open about sharing foundry process data,’ says Buehler.

TSMC has also been a leader in establishing a well-defined program among ecosystem players, starting with the design tool reference flows it established over a decade ago. Through its Open Innovation Platform program TSMC is helping to drive compatibility among design tools and provides interfaces from its core analysis engines and third party EDA providers.

In terms of standards Si2 organizes industry stakeholders to drive adoption of collaborative technology for silicon design integration and improved IC design capability. Buehler adds: ‘Si2 working groups define and ratify standards related to design rule definitions, DFM specifications, design database facilities and process design kits.’

Open and trusting collaboration helps understand the thriving ecosystem programs that top-tier foundries have put together. McGaughy says: ‘Foundry customers, EDA and IP partners closely align during early process development and integration of tools into workable flows. One clear example is the rollout of a new process technology. From early in the process lifecycle, foundries release 0.x versions of their PDK. Customers and partners expend significant amounts of time, effort and resources to ensure the design ecosystem is ready when the process is, so that design tapeouts can start as soon as possible.’

DFY is even more critically involved in this ramp-up phase, as only when there is confidence in hitting yield targets will a process volume ramp follow. ‘As DFY directly ties into the foundation SPICE models, every new update in PDK means a new characterization or validation step. Only a close and sustained relationship can make the development and release of DFY methodologies a success,’ he states.

The Week In Review: Nov. 7, 2013

Friday, November 8th, 2013

Peregrine Semiconductor Corp. and GLOBALFOUNDRIES are sampling the first RF Switches built on Peregrine’s new UltraCMOS 10 RF SOI technologies. This partnership unites Peregrine’s 25 years of RF SOI experience with a tier-one foundry. In a joint development effort, GLOBALFOUNDRIES and Peregrine created a unique fabrication flow for the versatile, new, 130 nm UltraCMOS 10 technology platform. This new technology delivers a more than 50-percent performance improvement over comparable solutions. UltraCMOS 10 technology gives smartphone manufacturers unparalleled flexibility and value without compromising quality for devices ranging from 3G through LTE networks.

Peregrine Semiconductor this week celebrated two significant milestones – its 25th anniversary of pioneering RF SOI solutions and the shipment of the two-billionth chip. Peregrine reaches the two-billionth-chip milestone in an order to Murata Manufacturing Company, the supplier of RF front-end modules for the global mobile wireless marketplace.

Rubicon Technology announced the launch of the first commercial line of large diameter patterned sapphire substrates (PSS) in four-inch through eight-inch diameters.  This new product line provides LED chip manufacturers with a ready-made source of large diameter PSS to serve the needs of the rapidly growing LED general lighting industry.

Semiconductor Research Corporation and Northeastern University researchers announced advancements in radio-frequency (RF) circuit technology that promise to improve and widen the applications of mobile devices.

Imec announced that it has successfully demonstrated the first III-V compound semiconductor FinFET devices integrated epitaxially on 300mm silicon wafers, through a unique silicon fin replacement process. The achievement illustrates progress toward 300mm and future 450mm high-volume wafer manufacturing of advanced heterogeneous CMOS devices, monolithically integrating high-density compound semiconductors on silicon.

STMicroelectronics announced this week its close collaboration with Memoir Systems has made the revolutionary Algorithmic Memory Technology available for embedded memories in application-specific integrated circuits (ASICs) and Systems on Chips (SoCs) manufactured in ST’s fully-depleted silicon-on-insulator (FD-SOI) process technology.

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