By David Lammers
Intel’s decision to invest as much as $4.1 billion in ASML has raised overall confidence levels in EUV lithography, and should allow the Dutch lithography vendor to funnel more funds into the stubbornly difficult effort to raise the EUV source power.

ASML has said it needs to reach 250 Watts of average source power to achieve the 125 wph throughputs sought by its early customers—roughly 10x today’s situation. However, with an influential Intel lithography manager saying that EUV source power needs to be in the 1,000 Watt range for contact holes and other critical layers, it is clear that source power remains far less than is needed.

Cymer Inc. (San Diego) recently said it has achieved 50 watts of average output power at a 40% percent duty cycle, operating for five hours in a closed loop. While scanners must step between die and pause for a few milliseconds, one lithography expert said a 40% duty cycle at 50W is essentially a 25W source at the required 80% to 90% duty cycle.

Hans Meiling, director of product management at ASML, emphasized the rate of progress, saying that a year ago the Cymer laser-produced-plasma (LPP) sources on the NXE: 3100 scanners were capable of only 1 to 2 watts of source power. “Today we are a factor of 10 higher, at 10 watts, which gives a throughput of six to seven wafers per hour,” he said. By the middle of next year ASML expects to have 70 watts of source power in its NXE:3300B EUV scanners.

EUV radiation is produced by hitting tin droplets with a powerful laser, and then filtering the 13.5 nm EUV wavelength. “Our suppliers are focused on the pre-pulse concept to create a mist of tin for higher conversion efficiency,” Meiling said at the Semicon West trade show.

Nigel Farrar, vice president of technical marketing at Cymer, said pre-pulsing the tin droplets—as they are dropping at 60 meters per second—“puffs them up a bit” so the CO2 laser can achieve a higher in-band conversion efficiency.

Three avenues at Cymer
Pre-pulsing is one of a trio of techniques Cymer is building in to the second-generation sources that ASML will integrate with its NXE:3300B scanners coming to market next year. These “HVM II” sources are a new architecture, and will boost the laser input power by using four amplifiers instead of three. Also, the collector efficiency is being improved by using a built-in capping layer on top of the molybdenum-silicon (MoSi) multilayer on the collector optics.

The vessel for the HVM II source being developed by Cymer, Inc. (Source: Cymer)

Farrar said Cymer was able to operate the collector module for four months, up from what Meiling said was about a week a year ago, extending the operating time by incorporating a hydrogen clean technique.

“We are going through learning cycles, using parallel activities on three dedicated systems,” Farrar said. While reaching its source-power goals is taking much longer than expected, he said there are no fundamental scientific reasons standing in the way of adequate source power. “It is not physics; it is engineering,” Farrar said.

Nevertheless, breakthroughs are needed. Meiling said ASML engineers are working at Cymer to create fully automated controls and introduce other techniques. “The leveling off can be eliminated. We can reach 90 to 100 watts with our current knowledge. A year ago we could not show you pre-pulse. Now we can do that for 5.5 hours,” he said.

Throughput, however, depends on combining a more-powerful source with a photoresist, which combines sensitivity and acceptable shot noise, line edge and line width roughness (LER and LWR) and other variables. Meiling noted that contacts—the holes that are one of the most critical device layers, requiring the best-resolution lithography—require a less-sensitive resist chemistry, which in turn calls for a higher source power.

“A joint effort has to come from both sides, from the resists and the source-scanner development,” Meiling said.

1,000 watts for contacts?
Yan Borodovsky, an Intel senior fellow and director of advanced lithography at the Technology and Manufacturing Group in Portland, said that EUV source power needs to be in the range of 1,000 watts for the contact holes, partly due to the much slower resists required for good contact hole patterning. Contact resists must be in the range of 60 to 70 milliJoules/cm².

Speaking at the 2012 International Workshop on EUV Lithography, held recently in Maui, Hawaii, Borodovsky spoke about the need for optical proximity correction (OPC) infrastructure development in order to overcome the 3D effects in EUV masks.

At the EUVL Workshop, Borodovsky concluded that EUV source power targets “need to be revised upwards” to more than a kilowatt of average in-band source power at the intermediate interface for EUV to be used for contact patterning and complementary lithography: a combination of gratings patterned with immersion ArF scanners with “cut mask” layers to create cuts in the lines.

Franklin Kalk, CTO at Toppan Photomasks, said EUV could be far more efficient that immersion ArF for the cut masks, requiring only one mask layer rather than four for 193 immersion.

The relationship between EUV source power and resist sensitivity has been hotly debated for the last decade, with EUV critics arguing that the ITRS roadmap assumes EUV resists which are far more sensitive than can be realistically achieved. Borodovsky said much of the discussion about EUV lithography has focused on using EUV for contacts and vias, while failing to fully acknowledge the shot noise, LER, and random or stochastic effects of EUV resists. At Semicon West, Borodovsky praised the rate of progress on EUV resist development, but emphasized that the most sensitive resists are not practical for the contacts and vias, where much slower resists are required to meet yield targets.

“Shot noise statistics alone lead to the conclusion that source in-band average power needed to expose resist capable of meeting the high-volume-manufacturing contacts and cuts patterning requirements might need to exceed 1,000W at the intermediate focus (IF),” Borodovsky said at the workshop.

Directed Self Assembly (DSA) might help relieve the situation, shrinking the contacts, vias, and cuts created either with 193i, EUV or direct-write E-beam, Borodovsky said during the lithography TechXPOT at Semicon West. “DSA will be used extensively, either in conjunction with 193i, or to shrink the cuts and vias down while rectifying EUV/EB size variability induced by shot noise and other stochastics,” he concluded.

By David Lammers
Two key areas of the semiconductor industry’s future—the 450mm wafer transition and EUV lithography—are the focus of the new NFX (NanoFab Xtension) building now under construction at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany.

Alain Kaloyeros

The cooperative research effort at CNSE and the Global 450 Consortium (G450C) could springboard New York into the 450mm fab era at some point, said Alain Kaloyeros, senior vice president and CEO of CNSE. The consortium, announced by New York Governor Andrew Cuomo in September 2011, includes IBM, Intel, GlobalFoundries, TSMC and Samsung, as well as CNSE.

Kaloyeros, in an interview at the NanoFab complex, said, “Now that there is a consensus that 450 is happening, our role is to create the environment, enable the resource innovation and the manufacturing innovation for the transition. The NFX facility is going to be heavily focused on tool development and demonstration, but at the end of the day, all this is going to be driven by innovation.”

With the 14nm node as the potential baseline at the NFX facility, half of the building is dedicated to the work of the G450C consortium, with the remainder for EUV-related programs which are part of an extension of the Center for Semiconductor Research (CSR), led by CNSE and IBM, with a focus on 14nm and beyond technologies.

The currently operating NanoFab North (NFN) building has an initial set of six 450mm tools within 4,000 to 5,000 square feet of cleanroom space. The early work has focused on automation development. To get ready for the tool and process development phases, the consortium is building a bank of 450 wafers to be shared by the members. The consortium has ordered 6,000 450mm wafers, at a per wafer price of $4,500, he said.

The new building will have 280,000 square feet of total space in a four-level building, with a total of 60,000 square feet of clean space, of which 45,000 square feet of cleanroom is on a waffle slab. The waffle slab in the NFX building is a reinforced 4-ft.-thick concrete structure capable of supporting 750 lbs. per square foot to obtain the load rating and vibration specification needed for the EUV NSE:3300 tool.

Interior view of the NFX clean room at CNSE. (Source: CNSE)

The 45,000 square foot cleanroom will have a single separation wall with the G450 space on one side and the CSR (Center for Semiconductor Research) EUV Center of Competency in the other. In addition, there is a quiet SEM/TEM room in the subfab on a 6-foot-thick slab, said Jonathan Holder, vice president for facilities and infrastructure at CNSE.

Construction of the building is expected to wrap up late this year; the schedule has been gated by delays to the EUV lithography source power modules. Tool hook-up work needed for the ASML NXE:3300 scanner will begin in October of this year with tool components arriving during the fourth quarter and into early next year. Installation of the dedicated gantry crane above the scanner is scheduled for July of this year.

The NFX building, at top center, is connected to CNSE Nanofab North.

EUV and 450

Kaloyeros said the G450C members are “working on a lithography solution, but we don’t know if it is going to be an early EUV tool or immersion 193 or imprint. We are in the process of having those discussions with the consortium members, and I can’t say now if they are contemplating one option or multiple options. But all of us understand that having a litho program is critical to the G450C.”

Despite the delays, Kaloyeros said the companies working at CNSE still see EUV as “very much a viable solution. They haven’t given up on it. A different question is: What litho technology is needed for a 450 fab? That could be EUV, or it could be by immersion litho being pushed. It could be immersion—who knows? The point is that by the time the 450 fabs are ready to be built if they don’t have EUV it is not going to kill construction of the 450mm fabs.”

A 450mm Fab in New York?

A decade ago Kaloyeros was critical of Intel for not doing much of its consortia R&D at CNSE. Now he is singing a different tune, happy that Intel is taking a leading role in the G450C effort based in Albany. “Intel was not a big player here. Now they are a big player. That is a big breakthrough for CNSE.”

Asked if Intel or other G450C member companies might build a fab in New York, Kaloyeros replied that “there is a very strong hope that when they are ready to build a 450 millimeter fab that they will consider New York. Governor Cuomo has said that New York really is open for business, and he personally has been leading this.”

By David Lammers
With the industry facing challenges in the introduction of EUV lithography and high costs for double patterning, TSV introductions have taken on heightened importance, participants said at the SEMI Advanced Semiconductor Manufacturing Conference (ASMC), held in Saratoga Springs, N.Y. in mid-May.

Risto Puhakka, president of market research firm VLSI Research Inc., said the gradual shift to both finFETs and TSVs will bolster equipment spending over the rest of this decade. “FinFETs will have a very dramatic impact on equipment spending, and wafer fab equipment spending will rapidly move to support 3D,” Puhakka said at the ASMC meeting.

Due to their initial high costs, however, TSVs will be adopted initially for performance reasons. By 2016, VLSI Research expects that TSV-connected chips will account for almost $12 billion in revenues. While that is a significant number, he noted that it will account for only about 5 percent of the sub-45nm silicon shipped in 2016. By that year, TSV-related equipment revenues will total $940 million, much of it for plating and etch equipment, he said.

Because of the relatively high cost of adding TSVs – an average of about $400 per wafer, double the normal packaging costs, according to VLSI Research – usage will be concentrated in high-performance chips, such as FPGAs, CPUs and GPUs, and application processors, and not in commodity DRAMs.

Overall, the semiconductor industry is in a healthy period, with VLSI Research expecting an average growth rate of 5-8 percent over the next several years, higher than the worldwide GDP increase. In 2011, IC revenues were $252.4 billion, which he said is expected to increase to $342.8 billion by 2016.

Equipment sales also are on an upward track, ratcheting up from about $50 billion last year and this year to $67.3 billion in 2016, he said. However, Puhakka qualified his remarks at the outset, saying his forecasts could be disrupted if Europe has a financial crash, or what he called “Europe’s Lehman Brothers moment.”

Michael Campbell

Michael Campbell, senior vice president of engineering at Qualcomm, said, “We have to go smaller, whether it is by stacking or shrinking.”

“EUV will come, and we are betting on 2014 or 2015. But there are limits to how we can do the 14nm generation cost effectively. There are cost barriers with double patterning/double etch, but we still don’t know if EUV will get there. It sounds ugly,” he said in a keynote speech at ASMC.

Transistor scaling will continue, bolstered by a shift to finFETs. And Campbell said tests of a 0.18 micron SOI process for power and radio functions have shown “really cool” results.

Noting that many of the functions of a cellphone chip set, including memory, power management, and RF, could be stacked vertically, Campbell said. “As a system solution for consumers, TSVs have a lot of interesting potential.”

Subramanian Iyer, an IBM fellow who has managed IBM’s embedded memory and several other programs, took a similar view toward TSV-enabled 3D chips: arguing that the performance benefits are real, but remaining uncommitted about when the technology will be introduced.

IBM has been hiring more engineers to accelerate its 3D programs, participants at ASMC said. (Prof. James Lu, a packaging guru who teaches at Rensselaer Polytechnic Institute, said demand for his engineering graduates is so high that “I need to graduate more students.”)

But Iyer declined to say when IBM will introduce a TSV-connected product, though he showed a slide of a processor connected to a memory chip underneath with TSVs.

Iyer said the thinned wafers tend to bow, adding difficulty to alignment and processing. “Wafer bow is still the biggest technical issue. Overall, we have to get the costs down,” Iyer said.

The bandwidth and performance benefits from dense TSV connections are real: Iyer said 30 percent of total power consumption is in “chips talking to chips” over long traces on a printed circuit board. Book-sized printed circuit boards can be reduced to a 50-by-50 mm size with TSV connections between the MPU and the memory.

SOI Embedded Memory

Iyer said the semiconductor industry is in “a new age of non-optimal scaling” in which performance and power do not improve as much as in past generations. IBM found one answer in an SOI-based embedded DRAM technology.

“Scaling is becoming quite difficult, with expensive development costs. The benefits are still there but the improvements are saturating. And every generation is more complex,” said Iyer, who has worked at IBM since 1981.

He said EUV lithography will not be available at the 14nm node, and the industry is still “debating its use for 10nm.” During an ASMC panel discussion, he suggested that if EUV is not ready for the 10nm node, it may be essentially too late, as CMOS itself may run out of scaling room after the 7nm node.

Already, the DRAM stacked capacitor is “dead,” Iyer said. That may be one reason why TSMC announced at its recent technology event that it will no longer develop an embedded DRAM technology for its foundry customers, with the move to TSV-connected DRAMs as a replacement going forward, TSMC managers said.

IBM, which began using SOI technology in 1998, found that it could develop a fast, low-leakage eDRAM on an SOI substrate. “Making a DRAM on SOI is a lot easier than on bulk,” Iyer said. “When we first made the move to SOI, we thought it would be terrifying. It turned out to be an immense process simplification.”

Using the buried oxide layer in SOI substrates, IBM could dispense with a thick oxide collar it had used to shut off parasitic capacitance in the pFET well. And implant steps were dispensed with by buying an SOI substrate with N+ and P- epi layers built-in.

IBM uses a deep trench DRAM capacitor, and builds 96 MB of cache on its latest Power processors for the Z series machines ( mainframes), estimating that those chips have 25 percent higher throughput than they would if only SRAM memory was available.

In addition, Iyer said “almost everything IBM makes” has an eDRAM component to it, and said IBM is open to licensing its SOI-based eDRAM technology. “If 10 percent of the die is SRAM, it makes sense to use eDRAM,” he said.

By David Lammers
For much of the past year, many in the chip industry have viewed with alarm the slow progress in EUV source power. But GlobalFoundries’ Stefan Wurm, the director of Sematech’s lithography program, said the bigger challenge lies in the mask area, including getting the two major EUV mask blank vendors to boost their investments.

Stefan Wurm

At the recent Advanced Semiconductor Manufacturing Conference in Saratoga Springs, N.Y., Wurm said while boosting the source power has been a bigger challenge than expected, the investments of time and engineering resources have been large enough to solve the problem. “I have a lot more confidence today” that source power will increase sufficiently by the end of the year to support a 30 wafers-per-hour throughput level on the ASML NXE:3100 scanners now in the field.

“I am much more worried about the mask issue,” Wurm said, particularly the EUV mask blanks. The blanks have MoSi multilayers, and must be free of defects and particles to a much higher degree than today’s mask substrates. EUV blanks used by logic companies must have three or fewer total defects, and none larger than 100nm, he said. As design rules shrink, the size of critical defects also gets smaller.

“The real challenge is not the (MoSi) deposition process. The real problem is defects on the substrate. The number of (meaningful) substrate defects really increases as the defects get smaller,” Wurm said. (See a contributed article from Sematech on the mask defect issue.)

There are only two mask blank suppliers, Asahi Glass and Hoya, both Japan-based, mid-sized companies which Wurm said are now cautious about making relatively large investments – on the order of $100 million – to add significant mask blank capacity. “They see that the source power is taking a longer time than expected, and so they may be thinking they don’t have to make investments now. And they both have other businesses.”

Without being specific, Wurm said meetings have been held with the two mask blank suppliers to discuss ways to boost their investments. Time is growing short. Some memory suppliers want to start using EUV lithography as soon as next year, and logic vendors want to begin commercial use of EUV scanners in 2015, Wurm said. By that time, the industry will need a mask blank capacity of about 6,000 units, he estimated. Defect levels will need to be improved by 100-500 times compared with today’s levels in order to support high-volume manufacturing.

By David Lammers

IBM and its partners are making progress on a EUV Center of Competency at the Albany Nanotech complex that will move into operation in the second half of this year, said Gary Patton, vice president of the IBM Semiconductor Research & Development Center.

Speaking at the Common Platform technology event Wednesday (March 14) in Santa Clara, Patton said construction is nearing completion on the EUV building, where IBM, Samsung, GlobalFoundries, and several equipment and materials suppliers will tackle the challenges. The building will also house the Global 450 Consortium for 450mm development.

“The lithography community has done an incredible job to improve resolution, without an improvement in the wavelength or numerical aperture,” Patton said. However, the advances in source-mask optimization and other computational lithography techniques are reaching their own limits, and the industry now faces “brute force” linewidth shrinks by using double patterning.

“If we can make EUV happen, we can get the k1 factor back to a much higher number,” in the 50-60 range. The Common Platform partners have used EUV to print contacts which are much smaller than contacts created with double patterning techniques.

The need for EUV and its 13.5nm wavelength is acute. But Patton said EUV faces several major challenges. The source power, now in the 25W range, needs to reach 250W in order to begin volume manufacturing at roughly 100 wafers per hour of throughput.

Learning to pattern in a vacuum, with reflective optics and masks, and without a pellicle, all introduce new challenges to lithographers. Resists are another challenge facing the Common Platform partners at the EUV Center.

To prepare for the introduction of EUV, IBM also is expanding its Burlington, Vermont mask center, adding a large (40,000 sq. ft) clean room. The ability to image mask defects also requires collaborative research, some of which will be done in Burlington.

Block copolymers also could play a role in advancing the lithography roadmap, with directed self assembly (DSA) enabling the industry to move to the 10-40nm pitch range, he said. Self-aligned vias, requiring hard masks, are another research focus by the partners.

IBM and its design partners are focusing on “prescriptive design rules” rather than the restrictive design rules (RDRs) used thus far. RDRs are getting too complicated, requiring the Common Platform partners to prescribe a set of design rules, with limited exceptions. “The number of RDRs is still too large. And it is becoming difficult for the lithography community to improve the tools,” Patton said.

Optical Interconnects in 3D Stacks

Patton said optical interconnects also will be needed to achieve performance scaling. “Devices like scaling, but interconnects do not,” Patton said, referring to the worsening resistance and capacitance values as copper lines shrink. One solution is photonic interconnects, which could be created on a separate die connected to logic and memory by through-silicon vias. On-chip photonics are another possibility, he added.

IBM and its research partners have developed 3D test chips which use TSVs to bring power and signaling to the front surface of logic and memory chips. Photonic interconnects could provide 1 TB/s connections to separate logic and memory layers, with 30 GB of memory on the memory layer. IBM is developing both interposer and stacked TSV solutions, Patton said.

Extremely thin silicon-on-insulator is being developed in conjuction with STMicroelectronics and Leti, Patton said, aimed at mobile devices. Planar ETSOI is relatively straightforward way to advance CMOS into the fully depleted regime, with contacts to the source and drain regions as the main challenge.

FinFET transistors have significantly higher drive current than CMOS planar devices at low (0.5V) power supplies, Patton said, showing microphotographs of 6nm wide fins and finFET-based SRAMs with 0.04 square micron area.

The “ultimate” solution might incorporate silicon nanowires with a gate all around structure, he said. IBM has been research Si nanowires and carbon nanotubes-based devices, with ring oscillator demonstrations. At the same power, CNT based circuits have 10X the performance, he said.

“There are many pessimists who look at the challenges we face at the 14nm and 10nm technology generations, and they argue that we will not be able to extend CMOS beyond that. But I am here to tell you unequivocally that, based on the pipeline of innovations we have now, we will keep scaling. Many people forget that scaling has never been a linear process,” Patton said.

SPIE 2012 AL EUVL Conference Review

By David Lammers

The Imec research consortium expects to move to 450mm wafers for “selected module” process development by 2015, including patterning and gate formation, Imec CEO Luc Van den hove told reporters at the center’s Leuven, Belgium headquarters.

Luc Van den hove

“By 2015 we expect the key (450mm) tools to become available,” he said. Van den hove said he could not comment on when he expects a 450mm scanner to become available from ASML or any other vendor. “I could not imagine that the key tools would become available before 2015,” he answered in response to questions regarding when a 450mm EUV scanner will become available.

While the current EUV optics can be extended to a 450mm scanner, it will take a major development effort to maintain the stability of the larger wafers and reticles. “The g-forces (on the wafer stage) are much higher, which will worsen the stability challenge,” said Ven den hove, who earlier ran the consortium’s core lithography program.

Imec has built an extension to its 300mm clean room that is capable of handling the 450mm tools.  Van den hove said Imec will continue to do its core CMOS process development on 300mm wafers until 2015 “or a few years longer.” It expects to begin partial CMOS processing on 450mm wafers beginning in 2015, and plans to build a major addition to its existing 300mm clean room to essentially double the available cleanroom space, so that both 300mm wafers and 450mm wafers can run through a full CMOS process line. Construction of the fab expansion would have to begin in the next couple of years to be ready for the 2015 target date.

Imec will expand its newest clean room space (upper right building) to accomodate a 450mm process line.

“It makes no sense to do all of our research too early on 450mm tools, because that would be too costly. And tool testing is not our core competency,” Van den hove told the reporters. He said early work, for example, will enable the epitaxial deposition steps required to add stressors to transistors built on 450mm wafers.

Over its 27-year history, Imec has had a long and close relationship with lithography vendor ASML, located north of Imec in Veldhoven, Netherlands. At the press event here Monday (Oct. 10), Imec and ASML announced a five-year extension to their existing cooperative research work.

Imec installed ASML’s NXE:3100 pre-production EUV scanner this spring. On Monday, Imec announced that it will install ASML’s NXE:3300B tool, a production-level scanner. Van den hove told SemiMD that he expects the 3300B tool to be installed by early 2013.

ASML will install its state-of-the-art 193nm immersion litho tool, the NXT1950i system, at Imec by this November, which will support research in double and quad-patterning required to backup and complement EUV.

Van den hove said the engineering resources required to boost the EUV source power have gone up sharply, adding that an earlier development effort was required to improve the excimer lasers used in today’s 193nm scanners. “Today those excimer lasers are among the most reliable components of a CMOS processing line. But when we started, their up-time was terrible.”

Also, Imec and ASML will work together computational lithography tools and the metrology platform, the ASML Yieldstar S200.

At the press event, the head of Imec’s “CMORE” program, Stephane Donnay, said Imec and ASML have co-developed a set of sensors which can be used to align the reticle and wafer, and to measure the EUV energy dose.

The sensors will be integrated on ASML’s NXE:3300 EUV platform, he said.

“The dose sensor can withstand the high-energy EUV radiation,” Donnay said. “We are very proud that we can make a small contribution to our long-time partner, ASML, in making an EUV scanner with better performance.”

Imec uses its 200mm fab to codevelop MEMS, sensors, and other “More than Moore” products. The CMORE program works differently than the consortium’s core CMOS program, which focuses on the process modules required to advance CMOS scaling. With the CMORE program, Imec works on product development with a single partner, Donnay said. Five such co-development sensor efforts are underway, but he said he could only identify the joint work with ASML at this point.

“This is the first qualified CMORE product integrated in a customer’s product,” Donnay said.

Imec has nearly 2000 people working on a broad range of programs, including about 400 assignees from its program member companies. It has an annual budget of about 300 million Euros.

Recently, the state of New York said it will support establishment of the Global 450 Consortium, which is expected to have a 450mm process line ready by early 2013, though it remains an open question whether a full 450mm toolset will be available by then. G450C expects to begin its early 2013 patterning with a specially-designed imprint scanner capable of 450mm wafer handling. The imprint tool will be complemented with a 450mm-capable immersion 193 scanner by late 2013, according to Intel Corp.

Sematech named Stefan Wurm as director of lithography, putting the GlobalFoundries assignee in charge of the consortium’s critical lithography R&D programs, including the EUV lithography development effort which Wurm has helped lead since 2004.

As a GlobalFoundries assignee, Wurm most recently served as Sematech’s associate director of lithography, reporting to Intel assignee Bryan Rice.

Stefan Wurm

Wurm first joined Sematech in the late 1990s as part of the International 300-mm Initiative (I300I), where he was responsible for 300-mm metrology tool equipment demonstrations. Wurm then served four years as Sematech’s extreme ultraviolet (EUV) program manager, and was named Sematech’s associate director in 2008.

He is a principal member of the technical staff at the GlobalFoundries Technology Development Group, and earlier worked at Advanced Micro Devices, Siemens Semiconductor Group, Infineon, and Qimonda.

Wurm holds a doctorate in physics from the Technische Universität München, Germany, and holds more than ten U.S. and non-U.S. patents.

Sematech announced the speakers for the 2011 International Symposia on Extreme Ultraviolet Lithography (EUVL) and Lithography Extensions.

Jia Li of Nvidia, Han-ku Cho of Samsung Electronics; and Risto Puhakka of VLSI Research, will address the conference, planned for Oct. 17-21 at Miami’s JW Marriott Marquis Hotel. The EUVL event is organized by Sematech, in cooperation with EIDEC and Imec, while the Lithography Extensions Symposium is in cooperation with Imec.

Jia Li, director of wafer foundry operations at Nvidia, leads a team evaluating 20nm and 14nm process technologies, including the readiness of EUV for and the extendability of 193nm immersion lithography to the 14nm node. His speech will address lithography challenges, including critical dimension/line-edge roughness (LER) control, defect elimination, and throughput.

Han-ku Cho, vice president and head of the photomask team at Samsung Electronics, is the keynote speaker at the 2011 International Symposium on Extreme Ultraviolet Lithography. Cho joined Samsung’s Electronics Semiconductor Business in 1995 and has served as vice president and director since 2007, in charge of production, management, and technology development of the Photomask Team at the company’s  Semiconductor R&D Center. Cho led the Korean government program in EUV lithography for nine years.

Cho’s topic, “EUV Readiness and ASML NXE: 3100 Performance,” will look at the current status and readiness of EUVL as well as the EUV mask fabrication process from the viewpoint of a device manufacturer. He will include imaging performance and issues related to the NXE: 3100, as well as achievements and prospects in EUV resist development focused on line width roughness reduction.

Risto Puhakka, president of VLSI Research, Inc., is the keynote speaker at the 2011 International Symposium on Lithography Extensions. He will explore the conditions that enable innovative lithography technologies to be introduced into mainstream semiconductor manufacturing.

By M. David Levenson

The top concerns for advocates of EUV Lithography now involve the mask or its lagging infrastructure, and so it was appropriate that the 2011 SPIE Photomask Technology (BACUS) Conference concluded with a special session entitled, “Is it too late to panic?  EUV is Real!”

According to session organizer Frank Abboud of Intel, the purpose was to highlight how the total mask paradigm change required by the adoption of reflective EUVL masks with 1nm precision would create new opportunities for maskmakers and their suppliers. Other speakers were not so sanguine. Defect-free EUV masks will be needed for volume manufacturing in 2014, but today are impossible, they claimed.

Bill Arnold, chief scientist of ASML, spoke first at the session, pointing out that alternatives to EUVL are not compelling. The 15nm half-pitch (hp) word lines needed soon for NAND flash memories will need 17 process steps (and four masks) if implemented using 193nm immersion exposure and quadruple patterning. Such complex methods cannot be supported by NAND flash pricing.

According to Arnold, ASML has built six NXE:3100 1^st generation EUVL scanners and has shipped three to customers. They have demonstrated useable process windows at 21nm hp, and have printed 18nm hp structures using a slow (70mJ/cm²) inorganic resist with dipole illumination. Future ASML tools will have larger numerical apertures and fancier illumination options, facilitating shrinks to the 8nm node in 2018 and perhaps beyond – if masks are available – Arnold said.

Throughput and line edge roughness remain issues, but secondary to defect-free mask yield. According to Arnold, the first installed machines produce only 5-6 wph, but ASML is working with three suppliers of EUV sources to upgrade power and believes it is on track to meeting current targets. There is a trade-off involving resist sensitivity, resolution and line edge roughness. Low sensitivity resists give lower throughput but better resolution and edge roughness. So, the resist chemists have to improve their products, too.

Brian Haas

Brian Haas, vice president and general manager of KLA-Tencor’s Reticle & Photomask Inspection Division (RAPID),
pointed out that the industry consensus was all in favor of EUVL in 2008, but the R&D decisions made recently by semiconductor manufacturers have emphasized alternatives such as multiple patterning and e-beam direct write. That perceived diminution in resolve has discouraged suppliers of the very mask making, inspection and repair technologies that are needed for EUVL success. Haas pointed out a very clear chicken and egg conundrum: If the EUVL wafer stepper throughput stays low (and the chip yield lower), few masks will be ordered and the market for mask making tools will be tiny. Mask tool makers won’t even recover the NRE needed to develop those few unique tools and so won’t build them, he argued.

On the other hand, if EUV stepper throughput exceeds 150 good wafers per hour in actual production, EUVL will be cost-effective for most manufacturing, and many masks will be ordered. The market for KLA-Tencor’s 7XX Series Actinic Inspection Tools will be huge and Haas’s RAPID Division will thrive even with affordable prices. So, where will it begin? Haas suggested an initial target of 80 wph for high-volume manufacturing in 2020. The later that throughput is achieved, the higher the costs of achieving it. According to Haas, the industry needs a credible economic model for EUVL infrastructure and the resolve to persist in it.  Haas concluded, “EUVL is an economic imperative.”   He suggested the industry just needs to “man up.”

Oliver Kienzle, managing director of Carl Zeiss Semiconductor Metrology Systems, described how his company (which is already making the optics used in the ASML EUV steppers) is working to solve the EUV mask defectivity problem. They are developing an EUV aerial image metrology system (AIMS) based on an existing discharge plasma source (with adaptive optics to correct for its wobble) that will review 50 prospective defect sites an hour by simulating EUV stepper imaging.

Kienzle predicted that the first tool would be shipped in 3Q2014. If defects are found to be printable, the Zeiss MeRit HR 32 repair system (which includes an in-situ AFM) can deposit or ablate the absorber to correct the problem. Even phase-shifts due to substrate bumps can be “repaired” though a compensating edge profile change, Kienzle claimed. Of course an EUV-AIMS would then be needed qualify the repaired mask.

Since EUV masks may never have pellicle protection, repeated qualifications will be needed to avoid wasted stepper time due to contamination and soft defects. Sheng-Ji Chin of TSMC pointed out that test wafer printing is 50X too slow and expensive. He suggested that in-building EUV mask shops might be a partial solution until the EUV-AIMS actually becomes available.

Hiraota Morimoto of Toppan (whose mask facilities are located outside customer fabs) was upbeat about EUVL masks for the 2x nm and 1x nm nodes. He pointed out that mask inspection had completely changed because only reflected radiation inspection was now possible. Nevertheless some DUV inspection tools proved adequate for first-generation EUV masks, even finding phase defects 1.2nm high with diameters around 50nm. If existing DUV equipment can be used, producing 1 EUVL mask/month would be economic break even, but more than 20/month would be needed to justify dedicated actinic tools, according to Morimoto. In conclusion, he predicted that defect-free masks would be available in 2013-14, but seemed to joke about their affordability.

Byung-Gook Kim of Samsung was upbeat on the prospects for using EUV to make 22nm DRAMs, based on experience with one of the first EUVL steppers to be delivered. His main concern was the source, rather than the mask. Kim pointed out that the phase defects all result from bumps on the substrate surface, under the multi-layer reflector, and thus they can be (in principle) polished away or hidden. Two existing inspection tools can locate the ones likely to print – those larger than 20nm. Fewer than 10 percent of the blank defects actually print, Kim reported.  Pattern defects are different, but can be found at 22nm and repaired. DRAM redundancy helps yield, which is at 88% of the targeted value now. He predicts that masks with one printable defect per plate will be available in late 2012 and effectively defect free DRAM masks will appear by the second half of 2013. That, however, assumes that multilayer (phase) defects are reduced by a factor of 100 to no more than 2 per blank.

So, the consensus appeared to be that at present it is not too late to panic, at least not about the technology. Even if EUVL is delayed again, alternative methods will take the mask making and semiconductor industries to the next node or two. EUV mask quality is improving. The economics, however, is more problematic. If defect-free EUV masks can be delivered in volume without respins in 2014, then EUVL will be competitive. If not, it will be too late to panic.