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Waddle-room for Black Swans: EUV Stochastics

Friday, April 13th, 2018


By Ed Korczynski, Sr. Technical Editor

Long-delayed and extremely complex, extreme ultra-violet (EUV) lithography technology is now being readied for the high-volume manufacturing (HVM) of commercial semiconductor integrated circuits (IC). The International Society for Optics and Photonics (SPIE) Advanced Lithography conferences held yearly in San Jose, California gather the world’s top lithographers focused on patterning of ICs, and the 2018 gathering included several days of in-depth presentations on the progress of EUV sources, steppers, masks, and photoresists.

With a nod to Taleb’s “black swan theory” ( stochastic defects in advanced lithography have been called the “black swans” of yield loss. They hide in the long-tail on the short side of the seven-sigma distribution of a billion contact-holes. They cause missing contacts and cannot be controlled with source-mask optimization (SMO). They breed in etch chambers.

Many yield losses in lithography are classified as “systematic” due to predicable interactions of photons and masks and photoresists, and modeling can show how to constrain them. White swan “random” defects—such as those caused by particles or molecular contaminants—can be penned up and controlled with proper materials-engineering and filtration of photoresist blends. In contrast, “stochastic” black swans appear due to atomic-scale inhomogeneities in resists and the wiggliness of atoms.

The wavelength of EUV is ~13.5nm, which the IC fab industry would like to use to pattern half-pitches (HP) in the range of 16-20nm in a single-exposure. At these dimensions, we find black swans hiding in lithography and in etch results.

An ongoing issue is lack of ability to model the multi-dimensional complexity of plasma etching multi-layer resist stacks. In Moshe Preil’s 2016 SPIE keynote titled “Patterning Challenges in the sub-10 nm Era,” he wrote:

It is certainly not surprising that etch simulation is not as predictive as lithography. The plasma environment is significantly more chaotic than the relatively well behaved world of photons and photosensitive molecules. Even the evolving need for stochastic simulation in the lithography domain is significantly simpler than the three dimensional controlled chaos of an etch chamber. The number of different chemical pathways available for reaction within an etcher can also present a daunting challenge. The etch process actually needs these multiple pathways to passivate sidewalls while etching vertically in order to carefully balance lateral vs. vertical etch rates and provide the desired material selectivity.

Etch faces additional challenges due to the resist pattern itself. Over the years, resist films have been reduced in thickness to such an extent that the resist itself is no longer adequate to act as the transfer mask for the entire etch process. Etch stacks are now a complex layer cake of optical materials (anti-reflection coatings) and multiple hard masks. While this simplifies the resist patterning process, it has shifted the burden to etch, making the stack more complex and difficult to model. Etch recipe optimization remains largely the domain of highly talented and diligent engineers whose work is often more an art than a science.

Today’s Tri-Layer-Resist (TLR) stacks of photoresist over silicon-based hard-mask over carbon-based anti-reflective coating continue to evolve in complexity. Quadruple-Layer Resist (QLR) stacks add an adhesion/buffer layer of material between the photoresist and the hard-mask. Even without considering multi-patterning process integration, just transferring the pattern from a single-exposure now entails extreme etch complexity.

Figure 1 from “Line-edge roughness performance targets of EUV lithography” presented at 2017 SPIE by Brunner et al. (Proc. of SPIE Vol. 10143, 10143E-2) shows simulated stochastic variation in 18nm HP line grids. The authors explain why such black swan events cannot be ignored.

Fig. 1: Stochastic image simulation in PROLITH™ software of a single exposure of EUV to form long trenches at 36nm pitch: (LEFT) aerial image first calculated as a smooth profile, (CENTER) stochastic calculation of photo-acid concentration before post-exposure bake (PEB) as “latent image”, and (RIGHT) final calculated image after development, based on stochastic de-blocking reactions during PEB. (Source: Brunner et al., Proc. of SPIE Vol. 10143, 10143E-2)

Such stochastic noise is present for all lithographic processes but is more worrisome for EUV lithography for several reasons:

  • fewer photons per unit dose, since each EUV photon carries 14X more energy than a 193nm photon,
  • limited EUV power – only a fraction (~1%) of the source power at intermediate focus makes it to the wafer,
  • only a fraction of EUV photons are actually absorbed within the resist, typically <20% for polymer materials, and
  • smaller features as we progress to more advanced nodes, and so less area to collect EUV photons. Ideally, as the lithographic pixel size shrinks, the number of photons per pixel would stay the same.

Stochastic phenomena – photon shot noise, resist molecular inhomogeneities, electron scattering events, etc. – now contribute to dimensional variation in EUV resist patterns at levels comparable to or greater than customary sources of variation, such as defocus. These stochastic effects help to limit k1 to higher values (worse resolution) than traditional optical lithography, and will counteract the benefits of high NA EUV optics. The quest to improve EUV lithography pattern quality will increasingly focus on overcoming stochastic barriers. Higher power EUV light sources are urgently needed as features shrink. Photoresist materials with higher EUV absorption will also help with stochastic issues. Alternative non-polymeric resist materials and post-develop smoothing processes may also play a future role.

In “Stochastic effects in EUV lithography: random, local CD variability, and printing failures” by Peter De Bisschop of IMEC (J. Micro/Nanolith. MEMS MOEMS, Oct-Dec 2017, Vol. 16/4) data are shown in support of the need for new stochastic control metrics in addition to the established “process window” metrics. A dose experiment using a family of chemically-amplified resists (CAR) to produce 18nm HP line/space (L/S) grids showed that increasing dose in the range from 30 to 60 mJ/cm2 reduced line-width roughness (LWR) from 4.6 to 3.9nm, with no further improvement when increasing dose to 70 and 80 mJ/cm2. However, micro-bridging across spaces continued to drop by orders of magnitude over the entire range of doses, proving that stochastic defects are different “animals.”

In general, we can categorize sources of stochastic variation in advanced lithography as follows:

1)    Number and spacial-distribution of photons absorbed (a.k.a. “shot noise”),

2)    Quantum efficiency of photo-acid generation(PAG)/diffusion along with quencher distribution,

3)    Develop and rinse solution inhomogeneities,

4)    Underlayer (hardmask/anti-reflective coating/adhesion layer) optical and chemical interactions,

5)    Smoothing techniques including deposition, etch, and infusion, and

6)    Design layout and OPC and SMO.

While we cannot eliminate stochastics by design, we can start to design around them using sophisticated process simulation models. At 2018 SPIE, Ping-Jui Wu et al. from National Taiwan University and TSMC used sophisticated molecular dynamics simulations to model “Nanoscale inhomogeneity and photoacid generation dynamics in extreme ultraviolet resist materials.” Figure 2 shows that ion-pair interactions in CAR create different nano-scale domains of poly(4-hydroxystyrene) (PHS) base polymers and triphenylsulfonium (TPS) based PAGs, depending upon the concentration of tert-butyl acrylate (TBA) copolymers in the blend.

Fig. 2: Molecular dynamics simulation of nano-scale domain separation within 8nm edge-length cubes of CAR composed of phenol groups (grey), TBA (red), and TPS (yellow) for (a) phenol-rich blend, and (b) TBA-rich blend. (Source: Wu et al., Proc. of SPIE Vol. 10586, 10586-10)

Table 1 shows modeled (Brainard, Trefonas & Gallatin, Proc. of SPIE Vol. 10583/10583-40) contributions to stochastic LWR from PS-CAR exposed with 0.33NA EUV to form 16nm HP L/S grids. For this PS-CAR blend the quencher variability contributes nearly as much LWR as the photon shot-noise, indicating room for improvement by fine-tuning the PS-CAR formulation.

One way to scare away black swans hiding in the resist is with bright light, as shown at 2018 SPIE by a team led by researchers from TEL in “EUV resist sensitization and roughness improvement by PSCAR™ with in-line UV flood exposure system.” Photo-Sensitized (PS) CAR contains a precursor molecule that converts to PS when exposed to EUV light, in addition to PS-PAG and “photo decomposable base (quencher) which can be photosensitized” (PS-PDB) molecules. UV flood exposure after EUV pattern exposure but before development generates extra acid, allowing for higher quencher loading, such that higher image contrast with reduced LWR can be obtained. By increasing the concentrations of PAG and quencher in the resist blend there is a reduction in the stochastic at any target dose.

DUV Ducks:  ArFi multi-patterning

As shown by Nikon Precision at the company’s 2018 workshop in San Jose pre-SPIE, deep ultra-violet (DUV) steppers using 248nm KrF or 193 ArF sources continue to improve in IC fabrication capability. ASML also continues to improve its DUV steppers, including integrating the advanced metrology technology acquired from Hermes Microvision as part of the company’s Holistic Lithography offering.

“The Challenge of Multi-Patterning Lithography for Contact Layer in 7nm and Beyond” by Wan-Hsiang Liang et al. of GlobalFoundries at 2018 SPIE showed how multiple ArF-immersion (ArFi) exposures can replace one EUV step. They characterized the process window (PW) for patterning as limited by two types of defects:  1) single-layer bridging or missing contacts driven by lithography, and 2) multi-layer bridging or unlanded contacts or extra patterns driven by both lithography and hard-mask open (HMO) etch. They found that a patterning PW can only be obtained by co-optimizing lithography and etch.

DUV versus EUV cost estimates

The target metal HP for IMEC node 7nm (iN7) on-chip IC interconnects is 16nm, dropping to 10nm for the next iN5. A single-exposure of 0.33NA EUV can create the former half-pitch, but 10nm will require double-exposure of EUV.

The capital expenditure (CapEx) for 8 EUV or 16 ArFi steppers is ~US$1B. We know that EUV could improve fab yields, but we also know that black swans will cause new yield losses. The least risk for first use of EUV is for blocks/cuts to ArFi SAQP lines, so that multi-color ArFi masks could be substituted in an EUV yield-loss emergency without having to change the design.

In my ongoing role as an analyst with TECHCET, at 2018 SPIE I presented a poster on “Cost modeling 22nm pitch patterning approaches” in HVM using either EUV or ArFi DUV steppers in complex multi-patterning process flows. In this model, all yield losses including those from stochastic black swans are assumed as zero to create a Cost Per Wafer Pass (CPWP) metric. Real Cost of Ownership (CoO) calculations can start with these relative CPWP numbers and then factor in systematic yield losses dependent upon design, as well as random yield losses dependent upon particles and wafer-breakage. CPWP includes only fab costs, not including EDA nor masks nor final test.

Figure 3 shows that EUV-based process flows could save money over strict use of ArFi in multi-patterning, assuming 1 EUV exposure can replace 3 ArFi exposures with similar yield. EDA for EUV should cost less than doing multi-color ArFi layouts, and design:process-induced systematic yield losses should be reduced. By reducing the number of deposition and etch steps needed in the full flow, use of EUV should significantly reduce the turn-around-time (TAT) through the fab. GlobalFoundries’ Gary Patton has said that such TAT savings for advanced logic chips could be a month or more.

Fig. 3: Cost Per Wafer Pass (CPWP)—with all yield losses including those from stochastics set to zero—modeled for different process flows to achieve 22nm pitch patterns, showing that flows using EUV could reduce HVM costs if yields can be managed. (Source: Korczynski, Proc. of SPIE Vol. 10589, 10589-25)

EUV resist materials have additional stochastic constraints compared to ArFi resists, and as more highly engineered materials are expected to cost more. Nonetheless, the cost of stepper CapEx depreciation per wafer is ~10x the cost of all lithography materials for both ArFi and EUV in this model. More details of the CPWP model including materials assumptions will be presented at the 2018 Critical Materials Council (CMC) Conference, April 26-27 in Chandler, Arizona [DISCLOSURE: Ed Korczynski is co-chair of this public conference].


As the commercial IC fab industry begins ramping EUV lithography into HVM, engineers now must anticipate new stochastic failures. Perfect dose and focus cannot prevent them. A new constraint is added to the myriad challenges of engineering photoresist blends.

At the level of atoms we find plenty of kinetic energy to make things wiggle…or waddle. Waddling black swans have always been with us, but we used to be able to ignore them. While we can control random white swans, these black swans cannot be controlled but we can give them room to waddle around.


Logic Densities Advance at IEDM 2017

Monday, December 18th, 2017

By Dave Lammers

The 63rd International Electron Devices Meeting brought an optimistic slant to transistor density scaling. While some critics have declared the death of Moore’s Law, there was little evidence of that — on the density front at least — at the IEDM, held Dec. 2-6 in San Francisco.

And an Intel engineering manager gave a presentation at IEDM that took a somewhat optimistic view of EUV lithography readiness, auguring further patterning improvements, starting with contacts and vias.

GlobalFoundries, which is skipping the 10nm node, presented its 7nm logic technology, expects to move into manufacturing in mid-2018. John Pellerin, vice president of global R&D, said the foundry has worked closely with its two lead customers, AMD and IBM, to define a high-performance-computing 7nm logic technology that achieves a 2.8X improvement of routed logic density compared with its 14nm technology.

Pellerin said the current 7nm process of record (POR) delivers “the right mix of performance, power, and area (PPA),” adding that GlobalFoundries plans to bring in EUV patterning at an undefined later point in the 7+ generation for further improvements.

Contact Over Active Gate

Chris Auth, director of advanced transistor development at Intel Corp., described a 10nm logic technology that sharply increased the transistor density compared with the 14nm generation, partly due to a contact-over-active-gate (COAG) architecture. The 10nm ring oscillator performance was improved by 20 percent compared with the comparable 14nm test vehicle.

Chris Auth, who presented Intel’s 10nm technology paper at IEDM, was surrounded by questioners following the presentation.

Auth said the COAG approach was a key contributor to Intel’s ability to increase its transistor density by 2.7 times over the company’s previous generation, to 100 million transistors per square millimeter of silicon. While the traditional approach puts the contact via over the isolation area, COAG places the contact via directly over the gate. Auth said the approach does require a second etch stop layer and other process complexities, but contributes “a sizable 10 percent reduction in area.” Elimination of the dummy gate for cell boundary isolation, and the use of cobalt at three layers (see related story), also contributed.

While there has been much hand wringing in the industry over the costs involved with multi-level patterning, Auth didn’t appear phased by it. Intel used a self-aligned quad patterning (SAQP) scheme to create fins with a tight pitch. The SAQP approach required two sacrificial layers, with lithography defining the first large pattern and four additional steps to remove the spacers and create the final lines and spaces.

The Intel 10nm fins are 46nm in height.

The SAQP approach starts by exposing a 130nm line, depositing the two spacers, halving the pattern to 68nm, and again to 34nm. “It is a grating and cut process similar to what we showed at 22nm, except it is SAQP instead of SADP,” using patterning to form a grating of fins, and cutting the ends of the fins with a cut mask.

“There were no additional lithography steps required. The result was fins that are tighter, straighter, and taller, with better drive current and matching” than Intel’s 14nm-generation fins, he said. Intel continued to use self-aligned double patterning (SADP) for M 2-5, and for gate patterning.

GlobalFoundries — which has been in production for 18 months with the 14nm process used by AMD, IBM, and others — plans to ramp its 7nm logic generation starting in mid-2018. The 7nm high-density SRAM cell measures .0269 um2, slightly smaller than TSMC’s published 7nm cell, while Intel reported a .0312 um2 cell size for its 10nm process.

Intel argues that the traditional way of calculating density improvements needs to be replaced with a metric that combines NAND and scan flip-flop densities. (Source: Intel)

GlobalFoundries chief technology officer Gary Patton said, “all of us are in the same zip code” when it comes to SRAM density. What is increasingly important is how the standard cells are designed to minimize the track height and thereby deliver the best logic cell technology to designers, Patton said.

EUV Availability Needs Improvements

Britt Turkot, senior principal engineer at Intel, discussed the readiness of EUV lithography at an IEDM session, giving a cautiously bullish report. With any multi-patterning solution for leading-edge silicon, including etch and CMP steps, placement error is the biggest challenge. With quad patterning, Turkot said multiple masks are involved, creating “compounded alignment errors.”

EUV has its own challenges, including significant secondary ions from the EUV photons. The key challenge for much of the decade, source power, seems to be partially resolved. “We are confident that the 250 Watts of source power needed for volume manufacturing will be ready once the field tools are upgraded,” she said.

Pellicles may be another challenge, with ASML expected to have a polysilicon-based pellicle ready in time for EUV production. However, she said a polysilicon membrane “does give quite a hit to the transmissivity” of the mask. “The transmissivity impact is quite significant,” she acknowledged during the Q&A period following her talk.

Intel has succeeded in repairing some mask defects, Turkot said, and implements pattern shifting so that other defects do not impinge on the patterned wafer.

Asked by a member of the audience about EUV availability or up-time, Turkot said “one day, availability can be great,” and less than good on other days, with “long unscheduled downs.” Intel is predicting 88 percent availability next year, she said in response to a question.

Pellicle Needed for Wiring Layers

Scotten Jones, president of semiconductor cost consultancy IC Knowledge (Boston), said companies may be able to get by without a pellicle for EUV patterning of contacts and via layers late next year. However, a pellicle will be needed for patterning the lower-level wiring layers, absorbing 10-15 percent of the photons and impacting EUV patterning throughput accordingly.

“Companies can do the contacts and vias without a pellicle, but doing the metal layers will required a pellicle and that means that a ton of work still needs to be done. And then at 5nm, the dose you need for the resist goes up dramatically,” Jones said, adding that while it will take some time for ASML to roll out the 250 W source, “they should be able to do it.”

GlobalFoundries will take possession of its second EUV scanner in December 2017, while Intel is believed to own four EUV systems.

Pellerin said GlobalFoundries defined the ground rules for its 7nm process so that the foundry can do a phased implementation of EUV without causing its customers “design discontinuity, bringing a benefit to design costs.”

John Pellerin, v.p. of R&D, said GlobalFoundries plans a phased implementation of EUV without “design discontinuity.”

The foundry will first do the hole levels and then move into the tight-pitch metal levels as mask defectivity improves. “The mask ecosystem needs to evolve,” Pellerin said.

Cost-per-Function on Track

In a keynote speech at IEDM, Lisa Su, the CEO of Advanced Micro Devices, said over the last 10 years the semiconductor industry has succeeded in doubling transistor density every 2-2.4 years. But she said the performance gains have been much smaller. “We are making progress, but it is taking a tremendous amount of work,” said Su, who received a best paper award at the IEDM 25 years earlier.

About 40 percent of the CPU performance improvement now comes from pure process technology, Su said, while the remainder comes from better microarchitectures, power management, and integration of system components such as an on-chip memory controller. While instructions per cycle are increasing at a 7 percent annual clip, Su said “the tricks have run out.”

Overall, the leading semiconductor companies seem to continue to make progress on transistor density. And costs per transistor may also be on track. Kaizad Mistry, co-director of logic technology development at Intel, contends that with its Intel’s 10nm process Intel’s per-transistor costs are actually better than the historical  curve.

Jones said the IC Knowledge cost analysis of TSMC’s processes indicates TSMC also is hewing to historical improvements on the per-transistor cost front. However, the foundries are catching up to Intel.

Intel Cadence Lagging

“What really strikes me is that Intel brought out its 45nm process in 2007, 32nm in 2009, and 22nm in 2011, but then it took three years to do 14nm. We are about to be in the year 2018, and Intel still doesn’t have its 10nm process done. It is a very nice process, but it is not out yet, and TSMC’s 7nm process is ramping right now. By the time Intel gets to 7nm, the foundries may be at 3nm. GlobalFoundries skipped a generation but is ramping its 7nm next year. All will have processes competitive to Intel at the same time, or even earlier,” Jones said.

While foundries such as GlobalFoundries, Samsung, and TSMC may be able to quickly offer advanced logic platforms, the wider semiconductor industry faces design cost challenges, Jones said. “Yes, the cost-per-transistor is going down, and that’s nice, but the cost of a design with finFETs is in the 100-million-dollar range. Intel can do it, but many smaller companies can’t afford to design with FinFETs.”

That is why both GlobalFoundries and Samsung are offering FD-SOI based platforms that use planar transistors, reducing design costs.

“The Internet of Things market is going to be nine million things, at relatively low volumes. IoT companies are finding it hard to justify the cost of a FinFET design, but with the cheaper design costs, SOI gives them an economical path,” Jones said.

EUV Leads the Next Generation Litho Race

Friday, October 20th, 2017


As previously reported by Solid State Technology, the eBeam Initiative recently reported the results of its lithography perceptions and mask-makers’ surveys. After the survey results were presented at the 2017 Photomask Technology Symposium, Aki Fujimura, CEO of D2S, the managing company sponsor of the eBeam Initiative, spoke with Solid State Technology about the survey results and current challenges in advanced lithography.

The Figure shows the consensus opinions of 75 luminaries from 40 companies who provided inputs to the perceptions survey regarding which Next-Generation Lithography (NGL) technologies will be used in volume manufacturing over the next few years. “We don’t want to interpret these data too much, but at the same time the information should be representative because people will be making business decisions based on this,” said Fujimura.

Figure 1

Confidence in Extreme Ultra-Violet (EUV) lithography is now strong, with 79 percent of respondents predicting it will be used in HVM by the end of 2021, a huge increase from 33 percent just three years ago. Another indication of aggregate confidence in EUVL technology readiness is that only 7 percent of respondents thought that “actinic mask inspection” would never be used in manufacturing, significantly reduced from 22 percent just last year.

“Asking luminaries is very meaningful, and obviously the answers are highly correlated with where the industry will be spending on technologies,” explained Fujimura. “The predictability of these sorts of things is very high. In particular in an industry with confidentiality issue, what people ‘think’ is going to happen typically reflects what they know but cannot say.”

Fujimura sees EUVL technology receiving most of the investment for next-generation lithography (NGL), “Because EUV is a universal technology. Whether you’re a memory or logic maker it’s useful for all applications. Whereas nano-imprint is only useful for defect-resistant designs like memory.”

Vivek Bakshi’s recent blog post details the current status of EUVL technology evolution. With practical limits on the source-power, many organization are looking at ways to increase the sensitivity of photoresist so as to increases the throughput of EUVL processes. Unfortunately, the physics and chemistry of photoresists means that there are inherent trade-offs between the best Resolution and Line-width-roughness (LWR) and Sensitivity, termed the “RLS triangle”.

The Critical Gases and Materials Group (CGMG) of SEMI held a recent webinar in which Greg MacIntyre, Imec’s director of patterning, discussed the inherent tradeoffs within the RLS triangle when attempting to create the smallest possible features with a single lithographic exposure. Since the resist sensitivity directly correlates to the maximum throughput of the lithographic exposure tool, there are various tricks used to improve the resolution and roughness at a given sensitivity:  optimized underlayer reflections for exposures, smoothing materials for post-develop, and hard-masks for etch integration.

Mask-Making Metrics

The business dynamics of making photomasks provides leading indicators of the IC fab industry’s technology directions. A lot of work has been devoted to keeping mask write times consistent compared with last year, while the average complexity of masks continues to increase with Reticle Enhancement Technologies (RET) to extend the resolution of optical lithography. Even with write times equal, the average mask turn-around time (TAT) is significantly greater for more critical layers, approaching 12 days for 7nm- to 10nm-node masks.

“A lot of the increase in mask TAT is coming from the data-preparation time,” explained Fujimura. “This is important for the economics and the logistics of mask shops.” The weighted average of mask data preparation time reported in the survey is significantly greater for finer masks, exceeding 21 hours for 7nm- to 10nm-nodes. Data per mask continues to increase; the most dense mask now averages 0.94 TB, and the most dense mask single mask takes 2.2 TB.


Optimism Reigns at SPIE Lithography Conference, Despite Challenges

Tuesday, February 23rd, 2016


By Jeff Dorsch, Contributing Editor

Semiconductor manufacturing and design is growing increasingly complicated and just plain hard. Everyone knows that. The bad news is it’s only going to get worse.

Relax, there are many smart people gathered in San Jose, Calif., this week for the SPIE Advanced Lithography Symposium to discuss the challenges and figure out how to surmount them.

The changes required in lithography and related technologies to continue IC scaling promise to be painful and costly. Mitigating the pain and the cost is a common theme at the SPIE conference.

The annual SPIE Advanced Lithography conference is often dominated by discussions on the state of extreme-ultraviolet lithography (EUVL). In presentations on Sunday and Monday, the theme was generally the same as 2015 – EUV is making progress, yet it’s still not ready for high-volume semiconductor manufacturing.

Intel Fellow Mark Phillips said the technology has seen “two years of solid progress,” speaking Sunday at Nikon’s LithoVision 2016 event. He added, “There’s no change in Intel’s position: We’ll use EUV only when it’s ready.”

Anthony Yen of Taiwan Semiconductor Manufacturing covered the 30-year history of EUV development in his Monday morning presentation at the SPIE conference. Asked during the question-and-answer session following the presentation on when the world’s largest silicon foundry will use EUV, Yen stuck to the official company line of implementing EUV in production for the 7-nanometer process node, after some involvement at 10nm.

Seong-Sam Kim of Samsung Electronics also sees EUV realizing its long-aborning potential at 7nm, a node at which “argon fluoride multipatterning will hit the wall.” He touted the 80-watt power source Samsung has achieved with its NXE-3300 scanner from ASML Holding, saying it had maintained that level over more than eight months.

Intel’s Britt Turkot reported 200W source power “has been achieved recently,” and said the tin droplet generator in its ASML scanner has been significantly improved, increasing its typical lifetime by three times. EUV has demonstrated “solid progress,” she said, including ASML’s development of a membrane pellicle for EUV reticles.

While work with the ASML scanner on Intel’s 14nm pilot fab line has been “encouraging,” Turkot said, she added, “We do need to keep the momentum going.” Intel sees EUV entering into volume production with 7nm chips, according to Turkot. “It will be used when it’s ready,” she said.

EUV technology has shown “good progress” in productivity, while its availability and cost considerations have “a long way to go,” Turkot concluded, adding, “We need an actinic solution for the long term.”

An industry consensus has emerged that EUV will be used with ArF 193i immersion lithography in the near future, and this trend is likely to continue for some time, according to executives at the SPIE conference. There may also be wider adoption of directed self-assembly (DSA) and nanoimprint lithography technology, among other alternative lithography technologies.

Mark Phillips of Intel pointed to complementary implementation of EUV and 193i. “We must use EUV carefully,” he said. “We need to replace three-plus 193i masks.” Phillips added, “EUV can’t be applied everywhere affordably. 193i will continue to be used whenever possible.”

Nikon executives touted the capabilities of their new NSR-S631E ArF immersion scanner, introduced just before the SPIE conference. The new scanner can turn out 250 wafers per hour, and can be pushed to 270 wph with certain options, according to Nikon’s Ryoichi Kawaguchi.

Yuichi Shibazaki of Nikon said the company will next year introduce the S63xE scanner, improving on S631E.

For all the challenges of transitioning to 7nm and beyond, executives at SPIE remain optimistic about solving the issues of 193i multipatterning, DSA, and EUV. Harry Levinson of GlobalFoundries said in response to a question, “The ultimate resource is the human mind.”

SPIE Photomask Panel: Money Is An Issue

Friday, October 2nd, 2015

By Jeff Dorsch, Contributing Editor

The best things in life are free
But you can give them to the birds and bees
I want money
That’s what I want

Berry Gordy, Jr. and Janie Bradford wrote those lyrics in 1959 for the first hit song released by Tamla Records, later known as Motown. Barrett Strong was the first to record the song, which would be covered by The Beatles, The Rolling Stones, and many other artists.

“Money (That’s What I Want)” could have been the theme song for playing off the EUV Mask Readiness panel discussion on Thursday morning (October 1) at the SPIE Photomask Technology conference in Monterey, California.

Panelist Yalin Xiong of KLA-Tencor called for “a new model of discussing technology and economic terms” in developing inspection equipment for extreme-ultraviolet lithography photomasks and pellicles. “Long-term solutions that require investment are risky,” he said of actinic inspection technology, adding, “They require a new collaboration model.”

Xiong engaged with a fellow panelist, Jeff Farnsworth of Intel Mask Operations, in talking about such “economic terms” and forms of collaboration among mask shops, equipment vendors, and other parties in the semiconductor industry.

The KLA-Tencor executive asserted, “Photomask is an enabling technology for lithography. We have to make our voice heard.” He later added, “The voice [of the mask community] is not heard in lithography. We need to be louder.”

The last panelist on Thursday morning was Takahiro Onoue of HOYA, who reviewed the status of EUV mask blank manufacturing, where a substantial reduction in defects has been achieved in the past three years, he said.

Wrapping up his presentation, Onoue pointed to “economy” as “a significant challenge in 2015,” taking precedence over methodology and other key parameters. He added that “economic feasibility” is important to increasing production of defect-free, high-grade EUV mask blanks, and that will require “support from stakeholders for investment toward HVM [high-volume manufacturing].”

Onoue added for emphasis, “It’s very important.”

Funding and money issues aside, most of the panel session was devoted to discussion of technology issues in getting to HVM with EUV photomasks.

Farnsworth said during his presentation, “We’re serious about implementing EUV on 7 nanometer.”

Emily Gallagher of imec spoke about the necessity for pellicles to protect EUV masks. Handling of masks with pellicles can often add “large particles,” she said. While ASML Holding has a pellicle commercialization program well under way, Gallagher said the status of pellicles for EUV lithography is “not ready,” while adding there has been “a lot of progress.”

Chih-Cheng Lin of Taiwan Semiconductor Manufacturing reported that the foundry has been able to process 15,040 wafers in four weeks — an average of 518 wafers a day — using ASML’s NXE:3300 scanner this year, with tool availability increasing to 70.2 percent, compared with 55 percent during an eight-week period in 2014.

While ASML “has made a lot of progress” with EUV pellicles, Lin said, “the job is not done yet.”

The Week in Review: May 9, 2014

Friday, May 9th, 2014

SEMATECH announced this week that researchers have reached a significant milestone in reducing tool-generated defects from the multi-layer deposition of mask blanks used for extreme ultraviolet lithography, pushing the technology another significant step toward readiness for high-volume manufacturing.

University of California, Berkeley researchers sponsored by Semiconductor Research Corporation (SRC) are pursuing a novel approach to 3D device integration that promises to lead to advanced mobile devices and wearable electronics featuring increased functionality in more low-profile packages.

GlobalFoundries this week introduced an optimized semiconductor manufacturing platform aimed specifically at meeting the stringent and evolving needs of the automotive industry.

Peregrine Semiconductor announced shipment of the first RF switches built on the UltraCMOS 10 technology platform.

BASF inaugurated a new Electronic Materials Sampling and Development facility in Hillsboro, Oregon. The new facility is a strategic step towards establishing a North American footprint to supply materials for semiconductor manufacturing applications related to the electronics industry.

Veeco Instruments Inc. has appointed Shubham Maheshwari, 42, as its new Executive Vice President, Finance and Chief Financial Officer (CFO). Mr. Maheshwari replaces David D. Glass, who announced his retirement from Veeco last December.

Avago Technologies Limited and LSI Corporation announced Avago has completed its acquisition of LSI Corporation for $11.15 per share in an all-cash transaction valued at approximately $6.6 billion.

Microchip Technology Inc., a provider of microcontroller, mixed-signal, analog and Flash-IP solutions, this week introduced a new parallel Flash memory device.

The Semiconductor Industry Association announced that worldwide sales of semiconductors reached $78.47 billion during the first quarter of 2014, marking the industry’s highest-ever first quarter sales.

Qualcomm elected Harish Manwani to board of directors. Manwani brings more than 35 years of consumer product and global management experience, and currently serves as the Chief Operating Officer at Unilever PLC.

Blog Review: November 25, 2013

Monday, November 25th, 2013

Zvi Or-Bach, president and CEO of MonolithIC 3D, blogs about a recent announcement by Intel CEO Brian Krzanich on company expansion focused on a foundry plan. Or-Bach said that if Intel could keep the traditional 30% cost reduction per node from 28nm to 10nm, and the foundry’s cost per transistor is staying flat, then Intel would be able to provide their foundry customers SoC products at a third of the other foundries cost, and accordingly Intel should be able to do very well in its foundry business.

Vivek Bakshi, EUV Litho, Inc. reports on work presented at the 2013 Source Workshop (Nov 3-7, 2013, Dublin, Ireland), including data on the readiness of 50 W EUV sources to support EUVL scanners. At the meeting, keynoter Vadim Banine of ASML said that 50 W EUV sources have now demonstrated good dose control and are now available for deployment in the field. ASML also presented data on the feasibility of source power of 175 W at the first focus (720 W at source), and utilizing new, protective cap layers to give collectors six months of life.

At the GaTech Global Interposer Technology Workshop (GIT) in Atlanta, the pervasive theme appeared to be whether a change in substrate is required to lower overall costs and help drive HVM (high volume manufacturing) applications. Phil Garrou reports on the workshop, including presentations from Ron Huemoeller of Amkor and David McCann of GLOBALFOUNDRIES.

Pete Singer provides a preview of a special focus session at the upcoming IEEE International Electron Devices Meeting (IEDM), scheduled for December 9 – 11, 2013. The session covers many of today’s hot topics: memory, LEDs, silicon photonics, interposers, SOI finFETS and 450mm.

Dr. Lianfeng Yang of ProPlus Design Solutions, Inc., blogs that these days, circuit designers are talking about the increasing giga-scale circuit size. Semiconductor CMOS technology downscaled to nano-scale, forcing the move to make designing for yield (DFY) mandatory and compelling them to re-evaluate how they design and verify their chips.

Blog Review November 5 2013

Tuesday, November 5th, 2013

New blogs delve into the packaging technology of Apple’s A7, the road ahead for bulk FinFETs as defined by imec, with EUV is a gating factor for 450mm, split-manufacturing for U.S. trusted IC (TIC) program and Japan’s growing market for equipment and materials.

For the 10nm node and beyond, transistor research efforts are focused on high mobility designs with Ge and III-V channel, reducing VDD supply voltage as well as the subthreshold slope in transistors and optimizing multi-Vt designs. Pete Singer reports on work underway at imec in Belgium.

At the IEEE 3DIC in San Francisco Dan Radack of the Institute of Defense Analysis gave an update on the IARPA trusted Integrated Chip Program. Phil Garrou reports how it is now focused on split-manufacturing with FEOL done off-shore and BEOL done by trusted facilities in the U.S.

The A7 is manufactured by Samsung on a high-κ metal gate (HKMG) 28 nm process and the chip includes over 1 billion transistors on a die 102 mm2 in size. Phil Garrou reports on observations on the Package-on-Package (PoP) design as noted by fellow blogger Dick James. In an earlier blog, Dick described how the Apple A7 is using Samsung’s 28nm process.

Simon Favre of Mentor Graphics notes how EUV could possibly be a gating factor for 450mm. “Would you put in 450mm immersion steppers, and then yank them out to put in EUV before they’re fully depreciated?” he asks.

In advance of Semicon Japan, to be hold December 4-6 at the Makuhari Messe, SEMI’s Dan Tracy and Yoichiro Ando report that restructuring and consolidation has led to a new focus for the semiconductor manufacturers in Japan. As a result, the semiconductor equipment market in Japan will experience double-digit growth in both 2013 and 2014, driven by higher spending for memory production and in spending increases planned for the manufacturing of power semiconductors and “More than Moore” semiconductor technologies. Total equipment spending in Japan is estimated to reach $4.6 billion by 2014. Combining this with the $8 billion-plus spending on semiconductor materials, Japan represents a $12 billion market in 2014 for the suppliers of equipment and materials.

Research Bits: Oct. 22, 2013

Tuesday, October 22nd, 2013

Size matters in the giant magnetoresistance effect in semiconductors

Professors at Georgia State University reported that a giant magnetoresistance effect depends on the physical size of the device in the GaAs/AlGaAs semiconductor system.

In research that is supported by grants from the U.S. Department of Energy and the U.S. Army Research Office, Dr. Ramesh Mani, professor of physics and astronomy, studied the magnetoresistance in flat, very thin sheets of electrons in the ultra high quality GaAs/AlGaAs semiconductor with his colleagues Annika Kriisa from Emory University and Werner Wegscheider from the ETH-Zurich in Switzerland.

The researchers found that the change in the resistance or resistivity with the magnetic field depends on the size of the device. They demonstrated that, under the application of a magnetic field, wide devices develop a smaller and quicker change, while small devices develop a bigger but slower change in the resistivity. The resistance or resistivity of a material to the flow of electricity is a technologically important property, especially in semiconductors.

This research team developed a model to understand the observations and deduced that when the semiconductor system becomes of even better quality, the change in the resistance under the application of a magnetic field will become even bigger. Indeed, the change might become so big that the resistance vanishes entirely in the small magnetic field.

Thin film semiconductors that will drive production of next-generation displays

Researchers at the National Institute for Materials Science have developed a pixel switching semiconductor, which will be the key to driving next-generation displays, by using an oxide film with a new elemental composition.

When an oxide film contains metal with low bond dissociation energy, the thin film absorbs or desorbs oxygen easily and the conductivity of the film changes. For example, zinc has very low bond dissociation energy, so a thin film using zinc absorbs or desorbs oxygen easily when heated or cooled. This finding suggests that the manufacturing conditions for oxide semiconductors can be controlled by focusing on the bond dissociation energy. In fact, the research team confirmed that film deposition conditions can be broadened by adding silicon oxide with high bond dissociation energy to indium oxide. We also confirmed stabilization of thin-film conductivity in post-deposition heat treatment.

The research results are expected to be effective not only for reducing the power consumption of displays which consume about half of the power in rapidly diffusing smartphones, but also for achieving higher frequencies to realize higher-definition TVs. Additionally, the thin film developed in this research contributes to conserving precious resources by not using zinc, which is a trace element of concern, or high-cost gallium which is used in large quantities for galvanized steel sheets or as a rubber vulcanizing agent, while it also enables the manufacture of flat panel displays not affected by wild fluctuations in raw material prices.

Ultraviolet light to the extreme

When you heat a tiny droplet of liquid tin with a laser, plasma forms on the surface of the droplet and produces extreme ultraviolet (EUV) light, which has a higher frequency and greater energy than normal ultraviolet.Now, for the first time, researchers have mapped this EUV emission and developed a theoretical model that explains how the emission depends on the three-dimensional shape of the plasma. In doing so, they found a previously untapped source of EUV light, which could be useful for various applications including semiconductor lithography, the process used to make integrated circuits.

In the experiments, Andrea Giovannini and Reza Abhari from ETH-Zurich in Switzerland blasted a 30-micron-diameter droplet of tin with a high-powered laser 6,000 times a second. They measured the spatial distribution of the resulting EUV emission and found that 30 percent of it came from behind the region of the droplet that was struck by the laser. According to their model, this unexpected distribution was due to the fact that the plasma partially surrounding the droplet was elongated in the direction of the laser pulse.

Devices that produce narrow beams of EUV for purposes like in semiconductor lithography use mirrors to focus the emission. But, until now, no one knew to collect the EUV light radiating from behind the droplet.

Solid State Watch: September 27-October 3

Friday, October 4th, 2013
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