By Mark LaPedus
Change is in store for Taiwan’s United Microelectronics Corp. (UMC), which is struggling to keep up with its leading-edge foundry rivals. UMC is behind in 28nm technology, and plans to skip the 20nm node, thereby jumping from 28nm to finFETs. This week, UMC took more steps to revamp its strategy. UMC has turned its 300mm fab in Singapore from a leading-edge logic plant into a specialty process production and R&D facility. Technologies being developed in this fab include CMOS image sensor backside illumination, embedded memory, high-voltage applications and TSV connections.

Intel’s new CEO Brian Krzanich has implemented a sweeping reorganization at the chipmaker, according to Reuters.

ST-Ericsson, the failed cell-phone chip venture between STMicroelectronics and Ericsson, has sold its GPS mobile business to Intel, according to Reuters. “Intel has purchased ST Ericsson’s mobile GPS, called GNSS (or Global Navigation Satellite System) business unit which includes assets and IP associated with the business,” said Doug Freedman, an analyst with RBC Capital Markets. “We believe the acquisition is prudent as Intel is expected to grow its competitive presence in the mobile area, particularly in 2014 when mobile manufacturing is moved to leading-edge 14nm. Note that Intel does offer high-performance LNAs (low-noise amplifiers) using GiSe:C for GPS signals in mobile communications.”

A group of 19 European companies and academic institutions have launched a three-year, 360 million Euro ($464.5 million) pilot-line project to support the industrialization of fully depleted silicon-on-insulator (FD-SOI) technology. STMicroelectronics and GlobalFoundries will provide the manufacturing capabilities for the program.

Separately, GlobalFoundries also is joining Imec’s advanced MRAM project.

STMicroelectronics said its FD-SOI guru, Jean-Marc Chery, has been appointed general manager of the Embedded Processing Solutions Segment and vice-chairman of the corporate strategic committee. Chery will now be responsible for the digital convergence, imaging, BiCMOS ASIC and silicon photonics, and microcontroller, memory and secure MCU product groups, as well as for the related technology R&D and front-end manufacturing. He was formerly general manager of ST’s Digital Sector and of technology R&D and manufacturing.

Soitec announced the industry’s first four-junction solar cell for concentrator photovoltaic systems. The system has 43.6% efficiency.

North America-based manufacturers of semiconductor equipment posted a book-to-bill ratio of 1.08 in April, down from 1.11 in March, according to SEMI.

Mentor Graphics reported its financial results for the company’s fiscal first quarter ended April 30. “Sales force execution and strong customer demand produced an all-time bookings record for a first quarter,” said Walden Rhines, chairman and CEO of Mentor Graphics.

Mentor Graphics has teamed with OpSIS and Lumerical Solutions to develop a complete EDA-style, full flow process design kit (PDK) for the OpSIS IME (Institute of Microelectronics) silicon photonics process.

In a move to ease and speed the development of complex ICs, Cadence introduced the Tempus Timing Signoff Solution, which significantly speeds up signoff using up to hundreds of processors in parallel.

Look for changes at Tessera Technologies. The chip-packaging IP firm has entered into a settlement agreement with activist firm Starboard Value regarding the composition of the company’s board. The board will consist of 10 directors, including six of Starboard’s nominees and four of Tessera’s nominees.

Now, Starboard Value is looking to gain control of DSP Group. The firm owns approximately 10.1% of DSP Group’s outstanding common stock.

Advanced Semiconductor Engineering (ASE) has acquired shares of Wuxi Tongzhi Microelectronics from Toshiba. The move will strengthen ASE’s ability to provide IC assembly and testing services in China.

Worldwide semiconductor revenues decreased by 2.2% to $295 billion in 2012, according to IDC. The firm expects the semiconductor market to return to growth in 2013 with revenues forecast to increase by 3.5% this year.

A slowdown in notebook and desktop PC purchases coupled with strong growth in smartphones and tablet PCs knocked Advanced Micro Devices down to fourth place in microprocessor sales in 2012 from second, according to IC Insights. Moving ahead of AMD in the 2012 microprocessor rankings were Qualcomm and Samsung.

The solar photovoltaic (PV) market is poised to rise from the ashes of its 2011 crisis to grow to $155 billion in 2018, says Lux Research. In the most likely scenario, the PV market will grow at a modest clip to 35 GW in 2013 before rapidly ramping up to 61.7 GW in 2018.

By Mark LaPedus
Enterprise-based bring your own device (BYOD) programs continue to become more commonplace. In fact, 38% of companies expect to stop providing devices to workers by 2016, according to a global survey of CIOs by Gartner.

What would happen if half of all global DRAM production, two-thirds of NAND flash manufacturing and 70% of the world’s tablet display supply suddenly disappeared from the market? For high-tech companies, this could be the outcome if current tensions escalate to the point of war on the Korean peninsula, resulting in the disruption of South Korea’s technology manufacturing base, says IHS iSuppli.

Intel telegraphed its future directions. The chip giant has named Brian Krzanich as its next chief executive, succeeding Paul Otellini. Krzanich, Intel’s chief operating officer since January 2012, will become the sixth CEO in Intel’s history. As announced, Otellini will step down as CEO. In a research note, Hans Mosesmann, an analyst with Raymond James, said: “We are not entirely shocked by the news but note that some investors preferred an external option on the belief that new blood was needed. Giving Krzanich’s manufacturing background we think the appointment is an indication that Intel will continue Paul Otellini’s strategy of building bigger/better fabs to attack the market. We also believe the move toward better manufacturing processes (like the 450mm transition) will remain front and center.” Added RBC Capital analyst Doug Freedman: “The move to appoint Renee James (as president) is likely in support of the vision of Krzanich’s and the board has laid out for the future of Intel. This appointment validates the increasing importance of on-going software development to Intel’s future, whether it be internally or in collaboration with partners.”

Microsemi has inked a foundry deal with Intel. Microsemi is currently engaged with customers and has started designs utilizing Intel’s 22nm tri-gate technology. Product delivery is anticipated to begin in late 2014 to early 2015.

Infineon and GlobalFoundries announced a joint technology development and production agreement for 40nm embedded flash (eFlash) process technology. The cooperation will focus on technology development based on Infineon’s eFlash cell design and manufacturing of automotive and security microcontrollers with 40nm process structures.

GlobalFoundries has collaborated with Cadence to provide pattern classification data for manufacturing processes of 20nm and 14nm. GlobalFoundries is using the Cadence Pattern Classification and Pattern Matching Solutions.

SEMI announced that Philip Yeo, chairman of Spring Singapore, and Lee Kok Choy, country manager of Micron Technology Singapore, have been voted by the SEMI Singapore Regional Advisory Board as recipients of two prestigious awards recognizing their contributions to the development and success of the Southeast Asian semiconductor industry. The awards will be presented during festivities held at Semicon Singapore 2013 on May 7.

Soitec has finalized a ZAR 1,000,000,000 (more than $100 million) solar financing bond issued by CPV Power Plant No.1 Bond SPV, an affiliate of Soitec Solar GmbH. The bonds will finance the construction of a 44 MWp utility-scale concentrator photovoltaic (CPV) solar power plant in Touwsrivier, South Africa.

Applied Materials and The Center for Science Teaching and Learning (CSTL) announced the San Francisco Bay Area grand-prize winning team and nine finalist teams in the 2013 Clean Tech Competition.

Rudolph has purchased selected assets related to 3D metrology from Tamar Technology.

Proteus Digital Health has completed a second closing of its Series F financing, raising $62.5 million in total. New corporate investor Oracle joins Otsuka, Novartis, Sino Portfolio and others in this funding round. Proteus is working to create a new category of products. Called Digital Medicines, these new pharmaceuticals will contain a tiny sensor that can communicate, via a digital health feedback system, vital information about an individual’s medication-taking behavior and how their body is responding.

Is Mindspeed Technologies on the block? The supplier of semiconductor solutions for communications has retained Morgan Stanley as a financial advisor to assist the board in evaluating various strategic alternatives available to the company.

Spansion has acquired the microcontroller and analog business of Fujitsu Semiconductor for approximately $110 million, plus approximately $65 million for inventory.

Amkor Technology announced that Stephen Kelley has been appointed to serve as president and CEO. He succeeds Ken Joyce, who previously announced his intention to retire.

ASE remained the world’s largest OSAT in 2012, according to the new rankings from Gartner.

Google Wants Faster Glass MPUs
At last week’s IEEE International Solid-State Circuits Conference (ISSCC) in San Francisco, the presentations reached new highs and lows.

Clearly, Google grabbed the spotlight, when the Internet search giant demonstrated Google Glass, an Internet-enabled pair of eyeglasses. The futuristic glasses take the industry one step closer to wearable computing and augmented reality. For example, the glasses can “hand over a virtual object” from one person to another, said Babak Parviz, who heads the Google Glass project at the company.

The glasses also sport a camera, audio, a multi-mode radio and GPS. But to enable the technology, the IC industry needs to step up to the plate. “We need quite a bit more processing power,” he said during a panel at ISSCC. “We need to do this with significantly less power consumption.”

Source: Google

Google isn’t talking about the details or the chips inside the glasses. The company is holding an essay contest in order to win the first wave of the glasses. The catch: If you are chosen, the winners will need to pre-order a Glass Explorer Edition for $1,500 plus tax and attend a special pick-up experience in person in New York, San Francisco or Los Angeles.

Seeing Red
At ISSCC, NASA’s Jet Propulsion Laboratory and Delft University of Technology demonstrated a novel optical sensor for the analysis of the composition and of the origin of geological formations.

Intended for next-generation Mars rover missions, the time-gated single-photon diode (SPAD) camera is designed for use in laser Raman spectroscopy and laser induced breakdown spectroscopy (LIBS). A sensor that integrates this camera into a time-resolved laser spectrometer can determine the chemical composition of minerals in on-surface planetary exploration.

Raman spectroscopy is a non-destructive, label-free optical analysis technique, according to researchers. But Raman signature often is overwhelmed by a strong fluorescence background, prompting the need for CCDs or streak cameras. Still, these devices are bulky and unsuitable for space flight.

One solution to the problem is SPAD technology. The 0.35-micron CMOS high-voltage sensor consists of 16 groups of 64 x 8 SPAD arrays with fast readout interfaces. The camera has a 700-picosecond shutter speed. The sensor has a 44% fill factor and has a 28% photon detection probability at 475nm and 250ps resolutions.

3D Brain Sensor
Also at ISSCC, National Chaio Tung University, China Medical University and Advanced Semiconductor Engineering (ASE) described a brain neural sensing microsystem based on a 3D-like device using through-silicon vias (TSVs). The proposed device is geared for brain function investigation and neural prostheses.

Based on a 0.18-micron process, the chip measures 5 x 5 mm square. A MEMS neural microprobe array and a low-power CMOS readout circuit are fabricated on two sides of the same substrate. The device has a 150um probe height and a 200um TSV height. A total of 480 microprobes is divided into a 4 x 4 sensing area, forming 16 channels. Some 16 TSVs are processed in a front-side via-last flow.

—Mark LaPedus

By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss IC packaging trends with Rich Rice, senior vice president for North America at Taiwan’s Advanced Semiconductor Engineering (ASE), the world’s largest independent IC packaging and test house.

SMD: Amazingly, there are still more than 100 vendors competing in the IC test and assembly business today. But for years, we’ve been waiting for a major shakeout in the sector. When will we see the shakeout?
Rice: It will eventually happen. It’s hard to say when this will take place. In packaging, the top subcontractors are fairly broad-based in the markets they serve. There are only so many companies in this space. Meanwhile, the smaller subcontractors generally offer niche technologies. But some of smaller subcontractors have specialized tooling and unique packaging. That type of thing is difficult to replicate, especially when the cost is very low and there is fully depreciated equipment involved. Those things tend to keep the smaller subcontractors in place for a long time.

SMD: Where are we in the business cycle in IC packaging?
Rice: In packaging, I wouldn’t say business is slow, but it’s not strong. As you know, the global semiconductor market has been somewhat tepid. The products that are selling in the market are the iPhone, iPad, Samsung Galaxy and things like that. If you are designed into one of those products, you are doing okay. If you are not, you are probably struggling.

SMD: Where are we in 3D TSV technology?
Rice: A lot of the fundamental assembly and interposer work is progressing. There are still challenges. Yields are definitely going to be a challenge. The question is how you manage yields. Then, you have test challenges. I personally feel pretty comfortable about the progress on that front. Overall, 3D TSV technology is not ready for high-volume production. Memory seems to be a limiting factor. The memory availability on these larger stacks is going to define when these 3D products will get launched.

SMD: When will we see stacked die in mobile phones?
Rice: In mobile, we’d love to have 3D. But it’s not going to be ready for a while, probably because of memory stack availability. Plus, the big OEMs hold a lot of the cards on when 3D might potentially be used and deployed.

SMD: For some time, ASE has talked about providing silicon interposers and 3D technology. What is the latest at ASE?
Rice: We have an interposer technology that we’ve promoted. We are not sure what the market acceptance is. Poking holes in silicon is mostly a foundry business. We can do some of it. We can do very simple dry etch processes on a die, via last and very course technologies. But for really fine-pitch 3D ICs or 2.5D interposers, that’s really a foundry type of business.

SMD: So ultimately, what role will OSATs play in the 2.5D and 3D market?
Rice: We will do the backend integration processes.

SMD: As you know, TSMC is offering a turnkey solution in 2.5D/3D. How do you see that playing out?
Rice: The guy that does the integrated solution will probably end up with a low mix, meaning a smaller number of device types, but probably at high volumes. My rationale behind that is very simple. Foundries have a common process platform. They are not tweaking their processes a lot. In other words, they have a lot of different devices that go through the same process.

SMD: What challenges will TSMC face doing the backend processes?
Rice: They must deal with having a toolbox with various interconnect technologies, and how you put it together, and how you manage that. It’s something we do day in and day out. And they don’t.

SMD: There is still a lot of activity in traditional packaging. What are some of the trends at the high end?
Rice: There are different markets. The advanced wafer node market has been driven by PCs, graphics, CPUs as well as servers. Typically, you will see larger packages with a ton of pins. For example, you have flip-chip BGA. We’re talking about pin counts in the thousands. This is where you will see the eventual introduction of 2.5D interposers.

SMD: What about other packaging markets?
Rice: On the cost-performance side, we look at this as the consumer market. In this market you have simple wirebond BGA and QFN. QFN is an industry word for quad-flat no-leads. The leads are basically on the bottom of the package. On the systems integration front, this is where you start seeing a lot of multi-die integration. For instance, you have PoP, or package-on-package. In PoP, you have a logic processor on the bottom and a memory on top. In PoP, we are seeing anywhere from 500 to over 1,000 pins. These are typically for mobile devices.

SMD: Where is PoP heading?
Rice: PoP morphs into different approaches as we try to make it thinner. We want to keep that down to 1mm or lower. While we are trying to make it thinner, we are also doing embedded technologies. You might embed a passive or active in the actual substrate itself. You might put capacitors as close as possible to the I/O of the die. You might embed a simple active component such as a power management device. You may want to embed components close to the processor, which can help with the power control and supply. In embedded PoP, you’re trying to get as much silicon packed in a particular volumetric area on the package.

SMD: What are the challenges with embedded PoP?
Rice: It’s disrupts the supply chain on how substrates are made. The substrate suppliers have not had that kind of capability yet, such as handling bare die or handling passive components inside their lines. In addition, if the interconnect is not robust or the yield is bad on the silicon, you throw away the whole substrate.

SMD: Is the embedded PoP shipping now?
Rice: Probably soon.

SMD: Another next-generation PoP is fan-out. Where is fan-out going?
Rice: In fan-out, you could make a really thin package. If you can get your signals from the bottom to the top of the package, and then put another memory package on top, you can get a fairly thin solution. It’s on our roadmap. We’ve had a fan-out production line for a long time. We were one of Infineon’s early fan-out licensees. We’re manufacturing on a 200mm format. To go to 300mm is a large investment. STATS ChipPAC has 300mm capability. We choose not to chase 300mm at this time.

SMD: What are the challenges with fan-out?
Rice: In terms of making holes through that package, we found it to be quite difficult. It’s a different type of mold compound. You have to use alternative means to get the signals up to the top. Secondly, as far as the package infrastructure itself, it is a wafer-level package. Wafer-level package infrastructure is quite different than regular package infrastructure. The investment level is much higher. So, you have to calculate your payback.

SMD: Is that why ASE is pursuing embedded PoP?
Rice: Potentially, you can embed a die into a PCB in a panel format. That could be more cost-effective than using a wafer format. It’s a lower cost infrastructure.

SMD: What else is going on in packaging in mobile phones?
Rice: With mobile phones, the board technology is extremely dense. The PCB is a high-density, built-up substrate. It can also handle very fine-pitch interconnect. You are also placing wafer-level CSPs on top of the substrate, which are essentially bare die. So, the mobile phone platform is essentially becoming a big package. Your cell-phone motherboard, in a sense, is a multi-chip module.

SMD: Is that driving the demand for wafer-level CSPs?
Rice: In most cell phones, a very high percentage of the components now are wafer-level CSPs. These components used to be housed in packages like BGA, QFP or QFN. Now, they are moving towards wafer-level CSPs, which are mounted to the motherboard. That’s why you’re seeing the wafer-level CSP growth rate going so high.

SMD: Will the cell-phone PCB ultimately become the package?
Rice: If you look at all of these bare pieces of silicon that are going on the mobile phone motherboard, it’s almost like a big package. But I don’t see it all becoming one big package for a while. There is not a single chip that does everything in a phone. There are far too many diverse technologies, features and IP in a cell phone. For example, you will continue to see discrete application processor packages.

SMD: What else is going on in multi-die packaging?
Rice: The industry has shipped multi-die packages for decades. In an early and simple configuration, you saw two die in a PDIP or even two die in a transistor package. We are doing a lot of multi-die packaging today. We are literally doing hundreds of millions of units per month. Today, we see high-density, flip-chip being used with a wirebond part stacked on top of it. It is all molded into one package. We see a lot of wirebonding packaging, where you have a lot of multi-die in the package. There are a lot of die-to-die wirebonds. So, you get into some exotic layouts in how you do your wirebonding.

SMD: So where is IC packaging headed?
Rice: The packaging portfolio will continue to expand. We will see more packaging technologies that are different and unique.

By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss 3D device challenges and applications with John Lau, a fellow at the Industrial Technology Research Institute (ITRI), a research organization in Taiwan.

SMD: What is ITRI doing in 3D TSVs?
Lau: At ITRI we have developed the world’s first Applied Materials’ 300mm (3D TSV) integration line. The line was completed two years ago. We developed the process from the very beginning to the end. We don’t have products. We are demonstrating the feasibility for 3D TSVs.

SMD: What else is ITRI doing in the arena?
Lau: We also have a consortium call Ad-STAC (Advanced Stacked-System and Application Consortium). We have more than 22 members. We just develop the necessary technologies for 3D integration. The members are UMC, SPIL, Applied Materials, Brewer, Rambus, Cisco and others. In addition to that, we have some 80 people working on EDA. For 3D, EDA is very critical.

SMD: Where is the industry at with 3D TSVs?
Lau: For me, it’s still very early. You still have to bring the OEMs into the mix. The OEMs may say: ‘Oh, I’m interested.’ Then, you still have to wait three to five years. There are two different kinds of OEMs. One is consumer. 3D TSVs are still too expensive for them. However, it could be a different story for high-end, next-generation servers, networking and test and measurement gear.

SMD: Where is a good starting place for 3D?
Lau: Take the Hybrid Memory Cube Consortium. Several months ago, the group announced they would open up the spec by the end of this year. But that’s only for high-end servers, test and measurement, and networking. It’s for very high performance and not for the consumer. They may adopt 3D. But the Hybrid Memory Cube for mobile products? Come on. Of course, we hope 3D can be for the consumer market. In consumer, there are larger volumes.

SMD: What is the biggest challenge for 3D?
Lau: Cost. The consumer market is cost-driven. For the iPhone 5, the semiconductor bill of materials is less than $30. The ASICs and memory are less than $30. Now take Xilinx’s 2.5D FPGA. The CTO from Xilinx recently gave a keynote at Semicon West. His conclusion was that they need to reduce the cost. A 2.5D FPGA is still costly.

SMD: What are the manufacturing challenges?
Lau: Just to make the TSV is no more than 5% of the cost. But if you look at the other steps, you have temporary bonding, back grinding, and others. The biggest issue is thin wafer handling and temporary bonding/debonding. And then you need to debug it.

SMD: Who should make the TSVs? The OSATs or the foundries?
Lau: Xilinx is using 65nm technology for their 2.5D FPGAs. OSATs like ASE don’t have 65nm technology. If they did, they would become another foundry. The OSATs should not make the TSVs. I still say a dummy piece of silicon like an interposer, where the line widths are 3 microns and above, the OSATs can do that. Last year, Amkor said that they are not going to invest a penny to make TSVs. That’s the right direction.

SMD: Why is Wide I/O memory generating so much interest?
Lau: Memory bandwidth. Bandwidth is defined as the amount of data transferred per second. Typical dynamic random access memory has 4-, 8-, 16-, or 32-bit data width to communicate with CPU/logic/SoC and/or the outside world. These are called ×4-, ×8-, ×16-, or ×32-bit I/O. Wide I/O is defined as ×512-bit I/O or 512-bit data width or greater.

SMD: So memory bandwidth is the name of the game?
Lau: The memory bandwidth is proportional to memory I/O data width. For instance, the DDR3–1600 chip has a speed rating of 1600 Mb/s per I/O. If this DDR3-1600 chip has ×32-bit I/O data width, the chip would have a total memory bandwidth of 32 × 1600 = 51,200 Mb/s or 51.2-Gb/s. The larger the data width, the larger the memory bandwidth.

SMD: So where’s the bottleneck?
Lau: The data width is limited by IC packaging technology. With TSV technology, which provides very small via size (5- to 10-μm sizes are common) and pitch (20- to 40-μm pitches are common), a much wider I/O data path, such as 512-bit data width, is more than possible. On the other hand, wire-bonding technology has pad sizes and pitches that are many times larger than those of TSV. In order to achieve a 512-bit data width, the chip size, and thus the cost, has to be increased substantially. This is why TSV is so attractive for memory bandwidth. Let’s say that if we have TSVs run through a 4-DRAM stack with a ×512-bit data path, we could have the same DDR3-1600 chip with a total memory bandwidth of 102.4-GB/s. Of course, this DRAM stack has to interconnect to the logic/SoC in order to get this bandwidth.

By Mark LaPedus
Over the last year, leading-edge silicon foundries announced their new and respective strategies in the emerging 2.5D/3D chip arena. The ink is barely dry and now the foundry landscape is changing.

One new vendor, Tezzaron Semiconductor, is entering the market. The 3D DRAM supplier plans to provide select 2.5D/3D foundry services within its recently acquired fab in Austin, Texas.

In addition, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) is tweaking its 2.5D/3D foundry strategy. Last year, TSMC announced a controversial turnkey solution. The company not only provides the front-end steps, but also the back-end work traditionally handled by the IC packaging houses. Now, instead of locking in customers with its front-to-back solution, TSMC is rethinking its position.

“We prefer to do it ourselves,” said Morris Chang, chairman and chief executive of TSMC, in a recent conference call. “We have become more flexible to partner with the OSATs.”

Two other vendors, GlobalFoundries and UMC, are sticking with their collaborative approaches. In that model, the foundries handle the front-end steps, but pass on the back-end work to the IC packaging houses.

Another foundry, IBM, has a slightly different strategy. Still to be seen, however, is what Intel and Samsung will do in the arena. And some of the IC packaging houses have given up the notion of doing fine-pitch interposers and through-silicon vias (TSVs). Instead, the OSATs are looking at doing course-pitch TSVs and interposers.

So, in general, there are two prevailing, leading-edge 2.5D/3D foundry models: TSMC’s turnkey solution and the rival collaborative approach. “I think both models will co-exist,” said David McCann, senior director of technical business operations for packaging and central engineering at GlobalFoundries.

Foundries go 3D
The memory bandwidth gap and resistivity problems in planar devices have fueled the development of 2.5D/3D chips. But advanced chip stacking has several challenges and is still a few years away from mass production. For example, TSMC will not see “significant revenue” in 2.5D/3D until 2015 or 2016, Chang said.

2.5D/3D technology and the associated supply chain are immature. Manufacturing costs are falling, but there is still a perception that the 3D devices will be prohibitively expensive, said Niranjan Kumar, product marketing manager for TSV programs at Applied Materials.

So far, only a few chipmakers have announced 3D chips. In 2010, Samsung rolled out one of the first 3D DRAMs using a 40nm process and TSVs. Then, last year, Samsung and Micron formed a consortium to develop a serial specification for a 3D DRAM technology called the Hybrid Memory Cube (HMC). Micron will sample HMC devices in 2013. Aimed at high-end applications, HMC will stack DRAM arrays on a logic chip. IBM is making the logic chip based on an SOI substrate.

Another 3D DRAM vendor, Tezzaron, recently has begun shipping its initial parts. But other 3D DRAM schemes, such as Wide I/O, have been delayed due to an assortment of technical issues. Still, the industry is making more progress on the 2.5D front. “The 2.5D era has arrived,” said E. Jan Vardaman, president of TechSearch International, a research firm.

To date, Altera, Cisco, IBM, Huawei and Xilinx have talked about or shipped 2.5D devices using interposers. In fact, Xilinx has shipped the Virtex-7 2000T FPGA, a product based on a 28nm process and a 65nm silicon interposer.

The device itself is built and assembled by TSMC, which refers to its 2.5D/3D turnkey solution as “Chip on Wafer on Substrate” (CoWoS). Using CoWoS, TSMC is also building a rival 2.5D FPGA for Altera. In CoWoS, the chip is attached to the substrate to form the final component. TSMC provides front-end manufacturing, TSV formation, interposers, chip-on wafer bonding, backside thinning, dicing and final test.

CoWoS has been given a lukewarm reception by the IC packaging houses, many of which believe that TSMC is taking a chunk of the backend business away from the OSATs. “For some customers, (CoWoS) works well. It doesn’t work for all customers,” Vardaman said.

TSMC has defended CoWoS, saying that the in-house, turnkey solution enables the foundry to ensure the quality of the chips and the production process. TSMC also assumes responsibility for the supply chain. “Technically, it is progressing well,” TSMC’s Chang said. “We are trying to reduce the costs.”

Beyond 2.5D FPGAs, TSMC recently taped out a Wide I/O device. To enable Wide I/O, the company requires DRAM from a third party. Originally, it was working with Elpida, which is being acquired by Micron. Now, TSMC is working with Micron and SK Hynix.

TSMC’s model may fall flat when customers ask for DRAM from Samsung. TSMC and Samsung are foundry competitors. It’s unlikely that Samsung will hand over DRAM wafers, along with its proprietary IP and test data to TSMC.

In some cases, it makes more sense to follow the collaborative model, where there are fewer conflicts. A customer can use its own logic and/or memory or buy it from a third party. The foundries do the front-end processing, while the OSATs collect and assemble the pieces.

With that scenario in mind, TSMC is warming up to the idea of working with OSATs to give customers more flexibility. TSMC also may be fending off its rivals, which are offering a collaborative approach.

More models

Others are moving full speed ahead with their strategies. Earlier this year, GlobalFoundries installed the tools to create 3D TSV devices on its 20nm platform within its fab in New York. It will handle the “via creation” steps. Then, it will hand off the traditional backend steps, such as temporary bonding/debonding, grinding and test, to the OSATs.

The foundry vendor also devised a low-volume, 2.5D line using 65nm interposers within its fab in Singapore. GlobalFoundries’ challenge is to demonstrate a smooth flow and good product yields at a competitive cost. “It’s going well,” said GlobalFoundries’ McCann. “The question is, can we make this collaborative supply chain model a one-to-one solution? We have to prove this to our customers.”

Another vendor, IBM, has been working on 2.5D/3D for years, including a specialized interposer technology. “IBM is working with Sematech to connect analog converter functions in a logic device with an interleaver IC in IBM’s BiCMOS SiGe technology,” said TechSearch’s Vardeman. “Applications are fiber optic telecom, high-performance RF, test equipment and processing for radar systems.”

The new kid on the foundry block is Tezzaron. In October, the company acquired the former SVTC fab in Austin. R&D foundry SVTC, which recently went bankrupt, originally acquired the fab from Sematech. Now, the fab operates under the name of Novati Technologies. Tezzaron is the sole shareholder in Novati. “We are going to become a 3D foundry,” said Robert Patti, chief technology officer at Tezzaron. “What we are trying to do is provide an open platform for 2.5D and 3D integration.”

Asked if Novati will compete against TSMC and GlobalFoundries, Patti said Novati can work with other foundries and will not compete against them. Novati will continue to serve SVTC’s customers. The Austin fab is a 200mm CMOS line, with 200mm/300mm backend capabilities.

As part of the plan, Tezzaron will shut down its current fab in Singapore and transfer the tools to the Austin fab by early 2013. By Q3 of next year, the company hopes to provide 3,000 wafer starts a week in Austin.

In the 2.5D/3D foundry arena, Novati will offer advanced stacking capabilities, TSVs and interposers. It can provide Tezzaron’s 3D DRAMs or procure third-party logic and memory chips. And Novati will offer both a turnkey and collaborative model. “We are willing to do a full turnkey solution,” Patti said. “I am willing to take the pieces and assemble them.”

The company prefers customers to use its so-called FaStack technology, which makes use of a proprietary bonding and tungsten process. Its 2.5D/3D technology is based on a 40nm process. By late 2013, it will offer a 28nm platform.

While the foundry landscape continues to evolve, several IC packaging houses are rethinking their plans. Some time ago, Taiwan’s Advanced Semiconductor Engineering (ASE) was looking at fine-pitch interposers and TSVs in a “via-last” production flow. “We have an interposer technology that we’ve promoted,” said Rich Rice, senior vice president of sales for North America at ASE. “We are not sure about the market acceptance.”

As it turns out, ASE discovered that leading-edge TSV and interposer work belongs in the foundries and not at the OSATs. “I think poking holes in silicon is mostly a foundry business,” he said at a recent event sponsored by the Microelectronics Packaging and Test Engineering Council (MEPTEC).

On the other hand, ASE and STATS are looking at course-pitch interposers and TSVs for niche applications like MEMS and RF. The OSATs will also play a major role in fine-pitch 2.5D/3D by offering the critical backend work.

TSMC and its turnkey model will not take all of the backend business away from the OSATs. TSMC is still going up the learning curve in the backend and may find the work a headache in the long run. “This is something we do day in and day out,” Rice added.

By Mark LaPedus
In today’s systems, consumers want more performance and bandwidth with a longer battery life.

Some chip segments are keeping up with the demands. Still other areas are falling way behind the curve. Battery life is an obvious problem, but memory bandwidth is under the radar. “Initially, memory bandwidth nearly doubled every two years, but this trend has slowed over the past few years,” said Abe Yee, senior director of advanced technology and package development at Nvidia. “Memory bandwidth has not kept up.”

In fact, there is a growing gap between memory bandwidth and overall system requirements, creating an unwanted I/O bottleneck, Yee said. The memory bandwidth gap, resistance-capacitance (RC) delays and other factors are fueling the development of new 3D DRAM schemes like Wide I/O. “We need Wide I/O memory,” he said. “We also need a known good die stack.”

But advanced chip stacking has a multitude of challenges and is still a few years away from mass production. One of the bigger, and sometimes forgotten, challenges is the ability to obtain and test known good die (KGD). A KGD is an unpackaged part or a bare die that meets a given specification.

As chip complexity increases, the industry may need to lower its targets and not expect a perfect KGD. In other words, the idea of having a KGD may not be attainable. “Ensuring KGD is (expected to be) more difficult in the ‘more than Moore Era,’ “ said Bill Bottoms, chairman and chief executive of ATE vendor Third Millennium Test Solutions (3MTS), in a recent presentation. “The era of known good die is drawing to an end. The concept of known good die will be displaced by ‘probably good die’ for very complex systems.”

Not all is lost, however. To address the KGD problem, the industry is developing a new class of probe cards. Chipmakers also are counting on a range of design-for-test (DFT) technologies, such as boundary scan, built-in-self-test (BIST), redundancy and repair, to enable the “probably good die” era.

Live and let die
KGD became a major issue in the 1980s, when the industry began to push multi-chip modules (MCMs) in systems. In MCMs, several unpackaged dies are stacked or assembled side-by-side within a module as a means to create smaller and faster systems.

MCMs met with limited success and a plethora of startups that were pushing the technology folded in the 1980s and 1990s. “The problem (with MCMs) was the dielectrics,” recalled Richard Otte, president and chief executive of Promex Industries, an IC packaging house. “The dielectrics were crummy.”

The other problem with MCMs was (and still is) the ability to obtain KGD. For years, the industry has procured KGD or bare die for use in MCMs, RF modules and system-in-packages (SIPs). Generally, a bare die takes up less space in a system compared with a traditional packaged part. For this reason, a large percentage of RF chips are sold as bare die and then assembled in RF modules. Analog chips, discretes, memories, MCUs and passives also can be sold as bare die.

Still, IC makers prefer to sell packaged parts, which can be tested in conventional ATE to ensure their quality. Bare die are sometimes viewed as a nuisance because they require specialized testing and handling. As a result, they are sold at a premium.

Selling KGD or bare die “is something chipmakers would prefer not to do,” said Raj Pendse, vice president and chief marketing officer at STATS ChipPAC. “It’s hard to guarantee the quality of KGD. It is sometimes not possible to access all of the test vectors at the die level.”

The challenges escalate for 2.5D/3D designs. In chip stacking, the probability of obtaining KGD decreases. For example, the average yield for a memory wafer is around 50% today, said Robert Patti, chief technology officer for Tezzaron Semiconductor, a 3D DRAM supplier. For a four-layer stacked memory device, the average yield could go as low as 6%, he said, which he described as “not economically viable.”

The inadvertent use of a defective die is catastrophic in 2.5D/3D designs. It will result in yield loss. And in many cases, the entire part must be discarded.

There are other challenges, especially as chipmakers move towards heterogeneous 2.5D/3D designs. In one scenario, an IC maker may use an internal part. Then, the company obtains and integrates a separate bare die from another vendor. But if the device fails in the field, it’s unclear who will take responsibility for the faulty part.

Settling for imperfection
To attack the KGD problem, chipmakers will require breakthroughs on two basic fronts: probe cards and DFT. It also requires a different test flow. The flow for conventional packaged chips includes IC manufacturing, wafer sort, packaging and final test. Wafer sort is considered an initial screening process for packaged ICs.

In contrast, a bare die is not tested at final test using conventional ATE. Instead, a die is tested at wafer sort using a wafer prober. In this flow, chipmakers claim they can achieve a reliable KGD, but overall test costs are sometimes higher. Die failure rates are reduced, but they are never totally eliminated in wafer-level testing.

For 2.5D/3D testing, the industry is working on new probe card technology. A wafer prober is incorporated with a custom probe card, which itself has thousands of probing needles that hit the bond pads on a die. In effect, the prober detects defective die, which are eliminated.

In complex designs, the needles may miss some of the tiny bond pads on the die. The contact force of the needles also could damage the die. Concerning KGD in 2.5D/3D designs, the industry requires “improvements in fine-pitch probe technology,” said Rich Rice, senior vice president of sales for North America at Advanced Semiconductor Engineering (ASE). Specifically, the big challenge for the industry is to develop probe cards that can handle greater than 1,000 contacts and pitches below 50um, Rice said.

In probe cards, there are two basic camps. FormFactor and others are working on fine-pitch probe cards using MEMS-based technology. In another camp, IMEC and Cascade Microtech have been working on a “rocking beam interposer” (RBI) probe card technology. RBI is based on Cascade’s membrane technology. “The metal energy doesn’t bend. It rocks,” said Ken Smith, vice president of technology development at Cascade, a supplier of wafer probers and probe cards.

In RBI, the probe tips are 6um square and 15um tall. With tip forces below 1 gram-force, RBI has demonstrated 40um and below pitches with a pad damage less than 100nm deep. “This technology is still in the early stages of the development cycle,” Smith said during a recent presentation at an event sponsored by the Microelectronics Packaging and Test Engineering Council (MEPTEC).

Even with breakthroughs in probe cards, 3D test still remains a challenge. In the flow, 3D devices will require at least four more test steps: a pre-bond test before stacking; a mid-bond test in the partial stacking phase; a post-bond test after final stacking; and a final test. The interposer and TSVs may also require separate testing.

Conventional ATE cannot be used in many, or possibly any, of these steps. So test must start in the design phase with various DFT techniques. In one scenario envisioned by Mentor Graphics, boundary scan can be used to test the bottom die in a 2.5D/3D design. Embedded core test can be used to test the middle or other dies, according to Mentor.

“The bigger challenge is with stacked logic die,” said Steve Pateras, product marketing director at Mentor. “There are a number of issues there. One is the known-good die problem. How do you ensure you’re getting good die when you stack them together? With bare logic die, particularly with heterogeneous parts, the quality of those parts comes into question.”

For years, memory makers have made use of BIST, repair and redundancy in their 2D designs, which may translate in the 2.5D/3D world. “With memory it’s easier, because there’s a robust testing methodology for bare memory die. The JEDEC memories have scan chains in them, which is one way of testing the memories and the SoC. You can use memory BIST,” Pateras said.

Using such techniques, 3D DRAM maker Tezzaron claims to have obtained better yields in 3D over 2D. “You have to change the way you think about design,” said Tezzaron’s Patti. “The secret to KGD is design-for-repair.”

Tezzaron refers to its design-for-repair and BIST solution as “BiSTAR.” Designed to repair bad memory cells and ensure a known good memory stack, BiSTAR includes 256 BIST sequencers, which run independently in parallel.

Besides repair and BIST, Patti said the industry must rethink its definition of KGD and may need to settle for something less. “Will we ever have 100% perfect KGD? It’s probably not practical,” he said. “A ‘kind of a good die’ may be acceptable. We may also have to accept the idea of having ‘not bad die.’”

By Mark LaPedus
Advanced 2.5D/3D chip stacking has a number of challenges and is still a few years away from mass production.

In fact, mass production may not occur until 2015 or 2016. But OEMs can ill afford to sit still and wait for 2.5D/3D technology to mature. So, until 2.5D/3D is ready for prime time, chipmakers and IC-packaging houses are under pressure to innovate and extend current 2D-based technology.

Needless to say, OEMs demand smaller and lower power chips housed in thinner packages. “The silicon is getting more dense. There are also more I/Os on the chip. Packaging is becoming the burden,” said Raj Pendse, vice president and chief marketing officer at STATS ChipPAC.

In fact, IC-packaging houses currently are developing a dizzying array of new package types that promise to extend 2D technology. For example, the subcontractors are working on new packages that could evolve or replace the mainstream mobile technology: package-on-package (PoP). The next-generation PoP candidates include bond via array, embedded PoP, fan-in, fan-out, flip-chip PoP, and even multi-chip modules (MCMs).

“The mobile phone platform is essentially becoming one big package,” said Rich Rice, senior vice president of sales for North America at Advanced Semiconductor Engineering (ASE). “Your cell phone motherboard, in a sense, is becoming a multi-chip module.”

Surprise package
For decades, IC packaging mainly involved low-tech, labor-intensive work with a plethora of simple package types, such as DIPs, PGAs, PLCCs and QFPs. “Packaging used to be an afterthought,” said STATS ChipPAC’s Pendse. “Silicon was once the solution. The main goal of packaging was to encase the silicon so it wouldn’t fall apart.”

In the 1980s and 1990s, the world changed with the emergence of new consumer electronic items and the PC. IC packaging still remained in the shadows despite various innovations like BGA, CSP and flip-chip. More recently, there has been a sea of change in the industry. Chip complexity is increasing, but the geometries are shrinking. The boom in mobile is driving the need for new and thinner packages.

For example, there is a pressing need for a thinner PoP. Introduced several years ago for the mobile space, PoP is used for devices like ASICs, baseband chips and application processors. PoP combines separate logic and memory packages, which are stacked on top of each other. The bottom package is logic and the top is memory. The maximum height of the PoP packages is typically 1.4mm to 1.6mm, but the eventual goal is to drive the dimensions down to 1mm and below.

There are other design considerations. At the 65nm node, a processor had some 400 I/Os and consumed 400mW of power on a die size of 64mm-square, according to a recent presentation from DfR Solutions. But at 28nm, a processor has some 800 I/Os and consumes 1.2 Watts of power on a die size of 50mm-square, according to the firm.

Still, in next-generation mobile designs, the industry may need to shrink the PoP to 0.4mm. One way to boost PoP densities is a technology called fine-pitch copper pillar flip-chip packaging. “Copper pillar can help enable a smaller form factor for the bottom package,” said E. Jan Vardaman, president of TechSearch International, a research firm.

Copper pillar is not a packaging type per se, but it is a manufacturing technique to enable next-generation CSPs, PoPs and even 2.5D/3D chips. The technology moved into the limelight in 2010, when Texas Instruments and Amkor jointly rolled out copper pillar capabilities.

At the time, TI said that traditional wire-bonding technology would hit the wall at the 40nm node, thereby requiring copper-pillar flip-chip. In flip-chip, a device is mounted on a substrate face down. Traditional solder-based flip-chip is limited to 150um pitches. In copper-pillar, however, the pitches can be extended down to 50um in-line and 40um/80um staggered, according to Amkor.

In PoP, the top and bottom chips could be individually packaged using wire bonders. In another configuration, the top package could be wire-bonded, while the bottom package could implement copper-pillar flip-chip. Using copper pillar for the bottom package, PoP may be more expensive, but it enables higher I/O densities and increased thermal conductivity.

Flip-chip took several years to gain traction, but it is widely used for processors and graphics chips today. The lowly wire-bonder continues to have legs, as some 80% of the world’s chips are still assembled using wire-bonding techniques, according to Vardaman. “Wire-bonding will be around for a long, long time,” she said during a recent presentation at an event sponsored by the Microelectronics Packaging and Test Engineering Council (MEPTEC).

For years, the lead wires in wire bonding were based primarily on gold. Gold prices have skyrocketed in recent years, prompting many chipmakers to move to cheaper copper wiring. “Three years ago, the industry said wire bonding would not extend past 40nm,” said Y.S Kim, vice president of engineering at Signetics, an IC packaging house. “We are now qualifying copper wire bonding at 32nm.”

Signetics is also doubling its capacity for flip-chip package assembly within its factory in Paju, South Korea. The company offers standard bumping and copper-pillar flip-chip. The technology is being driven by finer-pitch packages in HDTVs, SSDs and smartphones.

Time for another PoP?
Besides flip-chip PoP, there are other next-generation PoP candidates, such as embedded wafer level ball grid array (eWLB). In typical wafer-level packages, the process steps are performed on the wafer and the interconnects are fit on the chip in a fan-in design. In eWLB, the interconnects are positioned in an arbitrary distance in a fan-out design. Unlike fan-in, eWLB’s package size and I/O count are not limited by the die size.

Infineon, STATS ChipPAC and others are pushing eWLB. With fan out, STATS ChipPAC can reduce the bottom PoP package in height to less than 0.5mm. Using fan out, the total height for a five-die package is less than 1mm. STATS ChipPAC is shipping multi-die versions of fan out packages in a 300mm manufacturing process.

The next step is to bring eWLB into the 2.5D/3D era. With the technology, STATS ChipPAC can embed multiple active and passive components in the same wafer-level package with a vertical 3D interconnection that can be achieved without the use of a TSV. “It is positioned for 2.5D integration. It’s an alternative (to 3D TSV),” said STATS ChipPAC’s Pendse.

Rival ASE is moving in a slightly different direction. Like STATS ChipPAC, ASE was an early licensee of eWLB from Infineon. Fan out requires a different tool and materials infrastructure. “The investment level is much higher,” said ASE’s Rice. “We are manufacturing it on 200mm. For 300mm, we chose not to do it.”

ASE and others are pursuing so-called embedded PoP. In embedded PoP, the die is embedded in the substrate in the bottom of the package. “You may embed a passive or active component in the substrate itself,” Rice said.

The idea is to embed components, such as the capacitors or power management devices, close to the I/O of the processor die. Embedded PoP could reduce the space and power consumption in mobile devices. It also has many of the challenges associated with MCMs. Embedded PoP may require bare die, which is difficult to handle and test. “It disrupts the supply chain on how substrates are made,” he said.

Embedding die into laminated substrates has been in development for years. For example, TI recently rolled out MicroSiP, a miniaturized system-in-package (SiP). MicroSiP is not a PoP package. Instead, it integrates ICs with passive components in a BGA format. The passives are arranged on the top, while BGA balls are arrayed on the bottom.

Then, a separate package, dubbed PicoStar, is embedded in the laminate substrate. All told, the combined MicroSiP/PicoStar package integrates a DC-to-DC converter with inductors and capacitors to provide a stand-alone power supply, said David Heacock, senior vice president of Silicon Valley Analog at TI.

In another PoP effort, Invensas, a subsidiary of Tessera, recently unveiled bond via array (BVA) technology. BVA PoP is a packaging alternative to Wide I/O. It has demonstrated scalability to a 0.2mm pitch and up to 1,400 I/Os. “BVA significantly pushes out the need for 3D TSV. At the same time, it renders solder via obsolete as it is able to cost-effectively scale to ultra-high I/O,” said Simon McElrea, president of Invensas.

Clearly, there are new PoP solutions waiting in the wings. OEMs will need to take a hard look at the new technologies and for good reason: 2.5D/3D technology is still not ready for prime time. “For 2.5D, 2014 will be a very interesting year. By the end of 2013, the capability will be in place. 3D mainly depends on memory standards and memory adoption,” said Sunil Patel, principal member of the technical staff for package technology at GlobalFoundries.

Steve Pateras, product marketing director at Mentor Graphics, added: “From a tapeout point of view, 2.5D is happening this year. We have customers taping out 2.5D. For 3D, we’re seeing design activity for memory on logic. Next year we’ll see some tapeouts. There is no real activity in logic on logic yet.”

In any case, the role of packaging is changing. Packaging is no longer an afterthought. It is becoming an important part of the IC design and manufacturing process. “Today, it is an important part of the solution,” STATS ChipPAC’s Pendse said.

By Mark LaPedus
Mentor Graphics announced that GlobalFoundries Inc. and Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) will use Mentor’s SmartFill technology from its Calibre YieldEnhancer line for 20nm manufacturing. In addition, Mentor recently posted its results and raised its guidance for fiscal year 2013.

At next week’s Design Automation Conference (DAC) in San Francisco, GlobalFoundries plans to demonstrate a design flow for its 28nm technology. The flow provides support for advanced analog and mixed-signal designs. In addition, GlobalFoundries has selected Synopsys‘ Yield Explorer solution as part of its Yield Management System (YMS) for faster yield ramp in production.

The Silicon Integration Initiative (Si2) released the OPDK v1.0 standard as approved by the Open Process Design Kit Coalition. The OPDK v1.0 standard includes the schematic symbol standard and the design parameter and callback specification.

Three silicon foundries, including LFoundry, MagnaChip and TSMC, are expanding their embedded memory intellectual-property (IP) offerings in an effort to reach into new and emerging markets.

Taiwan’s Advanced Semiconductor Engineering (ASE), the world’s largest semiconductor packaging and test company, has opened its phase 3 manufacturing facility in Weihai, Shangdong province, China. The new building is part of ASE’s expansion plans to increase its manufacturing capacity for discrete packaging and test.

Barclays Capital raised its forecast for FormFactor, as the struggling probe-card maker upgraded its own guidance for the quarter. “We continue to expect FormFactor’s cash burn to end in 2H ‘12, though (we) don’t anticipate GAAP profitability through 2013,” said C.J. Muse, an analyst with Barclays.

VLSI Research maintained its semiconductor equipment forecast, which calls for the industry to fall by 7.2% in 2012 over 2011. But business is getting better. Fab equipment makers “are now seeing a strong momentum in order activity carrying over into the second half of the year. This will offset some of the weakness seen in the NAND space where end demand has fallen short of expectations, prompting NAND manufacturers to postpone some capacity additions,” according to VLSI Research.

By Mark LaPedus
The initial round of stacked 2.5D and 3D chips based on through-silicon vias (TSVs) has emerged in the market.

There are other 2.5D/3D chips in the pipeline, but it’s taking longer than expected to bring these devices into production. There are a range of design, manufacturing, supply chain and cost challenges associated with 2.5D/3D designs.

The enormous risk to bring these chips to market means that vendors must develop a sound and cost-effective strategy on all fronts. In one part of the wafer-level packaging flow, for example, chipmakers must choose between one of the three main vertical stacking techniques: die-to-die, die-to-wafer and wafer-to-wafer.

Each stacking technique has its advantages and disadvantages. The decision to go with one technique or another depends on the product type, process flow, and, of course, cost. And it also involves some changes in the interconnect material and wafer bonding methodology.

The early stacking trends are becoming apparent: The 2.5D/3D chip market is currently embracing die-to-die (sometimes called chip-to-chip), with die-to-wafer in the works. Wafer-to-wafer has moved into applications such as image sensors, but the technology is still in the distant future for chip production.

“I think the biggest challenge for the whole process is yields,” said David McCann, senior director of technical business operations for packaging and central engineering at GlobalFoundries.

“Die-to-die is the first implementation. In die-to-die, you can manage the warpage and isolate the yield,” McCann said. “Wafer-to-wafer will take place in the future, but you bring yield issues into your business model.”

Another foundry, Taiwan Semiconductor Manufacturing Co. (TSMC), recently rolled out its Chip-on-Wafer-on-Substrate (CoWoS) offering. This is a turnkey line that includes both the front- and back-end steps for 2.5D/3D production. Technically, CoWoS is a die-to-die scheme, but it could also be classified as die-to-interposer.

Bottleneck in 3D flow
In the overall 2.5D/3D manufacturing flow, there are a number of process steps. There are five main front-end TSV or via creation process steps: etch, chemical-vapor deposition, physical-vapor deposition, electroplating, and chemical mechanical polishing.

The bigger manufacturing bottlenecks reside at the back-end. In this flow, a processed wafer with TSVs goes through the following steps: wafer bumping, thinning, stacking and bonding. Test is conducted at the wafer level and during various points in the flow.

Test and the temporary bonding/debonding steps are still the big challenges. Though not as daunting, there are some challenges in the various stacking techniques, including die-to-die.

One of the first 2.5D chips in the market is Xilinx’s Virtex-7 2000T FPGA. The recently announced 2000T is a 28nm part, in which four FPGA slices are stacked on a 65nm interposer. Technically, Xilinx’ FPGA utilizes chip-to-chip and die-to-interposer stacking.

Emerging 3D memory devices utilizing Wide I/O also will implement die-to-die. Related to stacking, the industry is also moving to an emerging interconnect scheme called fine-pitch copper pillar bumps for 2.5D/3D designs.

For years, many 2D designs have used conventional flip-chip solder bumps. More recently, copper pillar bumps have been implemented in various 2D designs, when there is a need for low-profile and high-connectivity applications.

“Copper pillar gives you a tighter pitch,” said Sesh Ramaswami, senior director of strategy for the TSV program at Applied Materials. Flip-chip solder bumps enable 40-u pitches, compared to 20-u for copper pillar, Ramaswami said.

The transition to copper pillar bumping appears to be rather painless, but there are some issues in the vertical stacking flow. Compared to the other stacking techniques, die-to-die is well understood, and the supply chain is relatively straightforward.

The die-to-die equation becomes more difficult in heterogeneous designs, where the individual parts may come from two or more vendors. This complicates the stacking flow and brings yield into the equation. “That’s where the (importance of a good) supply chain comes in,” Ramaswami said.

The other problem with die-to-die is throughput and cost. In die-to-die, the components are assembled and aligned with traditional pick-and-place tools. The throughputs are slow, sometimes averaging 360 dies an hour. “The problem is more pronounced if the dies are small,” said Thorsten Matthias, head of business development at EV Group, a supplier of semiconductor equipment.

Regarding the assembly flow, Rich Rice, senior vice president of sales for North America at Advanced Semiconductor Engineering (ASE), added: “It’s really a challenge to handle these thin wafers. Warpage is a big challenge.”

3D devices will require ultra-thin wafers of 100 µm and below, but these substrates are less stable and prone to stress in the flow. This will require a manufacturing step called temporary bonding and debonding, which is still a relatively slow and expensive process.

For this and other reasons, the 2.5D/3D devices themselves are expected to remain expensive. “But for very large die, you can still achieve a cost reduction,” Rice said.

Other stacking options
There are even more challenges in die-to-wafer, which appears to be in R&D or the pilot line stage. Die-to-wafer also has many of the same inherit problems as die-to-die. There are supply chain issues. Both flows will implement expensive temporary bonding/debonding steps.

“The question is how you are going to test it? You really need known-good die (KGD) to put these things together. You also need to make sure your interposer is good,” Rice said.

Still, many chip makers have put die-to-wafer on their roadmaps to lower their costs and boost their throughputs, EV Group’s Matthias said. The other advantage is that “you can control or eliminate warpage,” he said.

Meanwhile, for decades, the industry has been talking about wafer-to-wafer stacking. Wafer-to-wafer enables the highest throughput, but it requires that the dies have the exact same size when bonding. But if a defective die is bonded to a good die, it destroys the whole stack. “Wafer-to-wafer is a long ways off,” said E. Jan Vardaman, president of TechSearch International Inc., a research firm.

To accelerate wafer-to-wafer, the industry is exploring new bonding technologies. Today’s 2.5D/3D devices, based on TSVs and copper pillars, are implementing metal-to-metal thermocompression bonding. This methodology has the advantage of forming the mechanical and electrical bonds in one step.

The industry is also looking at copper-to-copper thermocompression bonding. “Copper-to-copper is a must if you are targeting the highest possible electrical performance at less than 10-u,” EV Group’s Matthias said. But this technology is a slower process and not expected to move into volume production for another two to three years.

Another technology, fusion wafer bonding, could one day enable wafer-to-wafer for 3D chip integration. Fusion bonding is a two-step process consisting of a room temperature bonding step and an annealing step at elevated temperature. EV Group and others sell fusion bonders.

Using one form of fusion bonding technology, dubbed direct oxide bonding, Ziptronix Inc. has demonstrated the ability to reduce distortion in backside illuminated (BSI) image sensors. Ziptronix’ ZiBond process can be performed as wafer-to-wafer or die-to-wafer. The process initiates at room temperature without external force required.

The rival bonding solutions “are limited in terms of stress, cost and scalability,” said Paul Enquist, CTO and vice president of R&D at Ziptronix.

Ziptronix’ technology is in production for BSI image sensors. It’s unclear when chipmakers will adopt fusion bonding for wafer-to-wafer 3D integration. The adoption of new technology takes time. “Our technology has been ready for awhile,” he said. “Finally, the market is ready for the technology.”