Applied Materials Inc. has approved a plan to restructure the company’s Energy and Environmental Solutions (EES) segment in light of challenging industry conditions affecting the solar photovoltaic (PV) and light-emitting diode (LED) equipment markets, according to a filing with the U.S. Securities and Exchange Commission (SEC) on Thursday (May 10).

The plan will impact up to approximately 250 positions globally. As part of the effort to cut costs, Applied expects to relocate manufacturing for its Precision Wafering System (PWS) solar business based in Cheseaux, Switzerland to Asia, according to the filing.

PWS business operations and customer support functions will be relocated to Treviso, Italy, the headquarters for Applied’s Baccini Cell Systems, and Xi’an, China, the site of Applied’s Solar Technology Center, according to the filing. PWS’s headquarters and new product development will remain in Switzerland.

The plan also includes reductions in development activities for LED. The total estimated pre-tax cost of implementing the plan is expected to be in the range of approximately $70 million to $100 million, or $0.04 to $0.06 per share, which will be incurred over the next 12 to 18 months beginning in the third quarter of fiscal 2012.

These actions are consistent with the company’s previously-stated goal to reduce the EES segment’s annual revenue breakeven level to $500 million in fiscal 2013, according to the filing.

By Mark LaPedus

The semiconductor equipment market continues to improve in 2012, prompting VLSI Research Inc. to raise its fab tool forecast for the second time in recent weeks.

Citing recent moves by Intel, Samsung and others to raise their respective capital spending this year, VLSI Research now predicts the semiconductor equipment market will reach $49.2 billion in 2012, down 7.1 percent over 2011. And in another positive move, VLSI Research also raised its overall IC forecast from 3.9 percent growth to 4.3 percent in 2012.

Not long ago, the research firm originally projected that the fab tool market would fall by a whopping 20.1 percent in 2012. Then, in February, VLSI Research raised its forecast and predicted the semiconductor equipment market would reach $45.6 billion in 2012, down 9.8 percent over 2011.

“Chip makers are generally optimistic and many of them are seeing positive trends in the market,” according to a new report from VLSI Research. “They expect a healthier business environment in the coming quarters. Foundries are at the forefront and investing aggressively as most of their leading-edge capacity is tapped out. The equipment industry is seeing a nice rebound following a weak Q4.”

There are some troubling signs as well. David Rubenstein, an analyst with Religare Capital Markets, an investment banking firm, sees an uphill battle for fab tool makers in 2012. “We project that capital spending will fall 12 percent year-over-year in 2012,” he said. “We forecast -19 percent FPD capex in 2012 and further declines in 2013.”

One of the problems is the ongoing memory downturn, which is hurting capital spending. “The memory sector remains a drag on the overall activity,” according to VLSI Research. “NAND orders are still soft as the industry burns some excess SDD inventory. DRAM activity remains pretty much frozen.”

Greg Wong, an analyst with Forward Insights, a research firm, sees a rebound in NAND flash. That market is “fairly weak right now due to seasonality. But it should starting improving in the second half with new smartphones, tablets and ultrabook launches,” Wong said.

Total inventories increased nearly 1 percent in February and are projected to jump by another 3 percent in March, according to VLSI Research. Total IC inventories in March will be 7 percent lower than from last year’s levels, according to the firm.

The fab tool vendors are also seeing a mixed picture. At the recent Applied Materials Inc. analyst event, Applied CEO Mike Splinter acknowledged that the company sees a challenging environment.

At the event, Applied guided fiscal 2012 revenues and EPS of $9.1-to-$9.5 billion and $0.85-to-$0.95, respectively, falling short of consensus of $9.6 billion and $0.96. This is “driven primarily by weakness in non-semi segments” like solar and displays, said C.J. Muse, an analyst with Barclays Capital.

“On the positive side, Applied is poised to benefit from several positive trends in semi,” including “increasing process steps in the move to 2Xnm/1Xnm, a move to 3D NAND, sustainability of wafer fab equipment spending, and growing capital intensity in display,” he said.

By Mark LaPedus, SemiMD senior editor

3D chips are moving closer to volume production, but there are still challenges with the technology.

Design issues, test problems, supply chain headaches and cost are still among the challenges to bring 2.5D and 3D chips using through-silicon vias (TSVs) into mass production. But many in the industry blame one set of fab tool technologies — the temporary bonding and debonding gear — as one of the bigger bottlenecks in 3D chip production today.

Cost, immature processes and throughput are among the issues with current temporary bonding and debonding tools. Two leading tool suppliers, EV Group and Suss Microtec, have separately taken steps to solve the problem by rolling out new and high-throughput platforms.

But seeking to change the landscape, Tokyo Electron Ltd. (TEL) has recently entered this tool market. And another new player — Applied Materials Inc. — is looking to shakeup the market and is reportedly readying a new tool, according to sources and analysts.

The temporary bonding/debonding tool business “is still a small market,” said Eric Mounier, an analyst at Yole Développement, a research firm, but “TEL and Applied are willing to enter this market” to get a foothold in the business.

Applied, however, has yet to announce a tool in the arena. A spokeswoman from Applied Materials declined to comment on those reports, saying that “We can’t comment on rumors about entering a market.”

Meanwhile, for some time, MEMS and other niche devices have used temporary bonding/debonding gear. These tools are suitable for the lower-volume MEMS market, but not for semiconductor production, Yole’s Mounier said. “It’s a different business,” he said. Chip makers demand “smaller footprint and higher throughput” tools.

Today’s temporary bonding/debonding steps in the 3D process flow are “very expensive,” added Jerome Baron, business unit manager for advanced packaging at Yole. “It’s a very immature process.”

Leading-edge chip and packaging houses are pushing Applied and TEL to enter the market in hopes of solving these issues. “People say (Applied) is developing a tool,” Baron said. “They are driven by customer demand.”

Needless to say, there is no guarantee that TEL, and reportedly, Applied, will succeed in this tool market. EV Group and Suss are looking to protect their installed base, but the two vendors are under pressure.

Sesh Ramaswami, managing director of strategy for the Silicon Systems Group at Applied, also declined to comment on reports that Applied will enter the business. “It doesn’t mean we’re doing something — or nothing — about it,” Ramaswami said.

Applied is a major player in 3D TSV, where it provides many tools in the arena. Commenting on the current state of the overall 3D chip market, Ramaswami said the business remains in its infancy. “It is still in the early stages. If you look at the players, they are shipping engineering samples. Customer samples are starting at the end of the year. Some production will start in the second half of 2013,” he said.

Changes seen in bonding landscape

There are a number of process steps to make a 3D chip. In the via creation or via processing process, there are five main steps: etch, CVD, PVD, electroplating, and CMP. The overall cost-of-ownership (COO) is declining for the via processing steps, he said.

Temporary bonding/debonding is not ready for prime time (Source: Yole)

In the front-end process, the real bottleneck centers around the temporary bonding/debonding area. Traditional silicon wafers have thicknesses of about 500 µm, which can be used to process most mainstream IC devices in a fab. They do not require temporary bonding/debonding gear.

A new class of 3D devices using TSVs will require ultra-thin wafers of 100 µm and below in the production flow. But in  the traditional IC production flow, ultra-thin wafers “are less stable and more vulnerable to stress,” according to Yole. “To address these challenges, as chip thickness is reduced, new processes including temporary bonding technologies will be required for handling such fragile wafers, especifically to support the wafer during back grinding and subsequent post-thinning processes.”

In the temporary bonding/debonding process, a wafer is processed in a fab. Then, the wafer is flipped. A separate carrier wafer with an intermediate layer is temporarily bonded onto the main wafer. Then, the main wafer undergoes a backside thinning process. At that point, the main wafer is debonded from the carrier wafer and cleaned.

In what is seen as a crowded field, the current bonding/debonding equipment suppliers include DoubleCheck, Dynatex, ERS, EV Group, Nitto Denko, Suss, Sysmelec,  Tazmo, TEL, TOK and Yushin. In total, EV Group and Suss combined have about 75 percent share in the temporary bonding/debonding market, according to the firm. This tool business is expected to grow from $64 million in 2011 to $94 million in 2012, according to Yole.

Source: Yole

The average selling price for a temporary bonding/debonding tool is $4 million to $5 million, with throughputs ranging from 10 to 12 wafers an hour, according to Baron and Mounier. The IC industry wants throughputs from 20 to 30 wafers an hour, they said. Temporary bonding/debonding represents 10 percent to 20 percent of the production costs in a 3D TSV line. The goal is to reduce that to between 5-10 percent, they added.

Providing another insight, Applied’s Ramaswami said temporary bonding/debonding tools are in their infancy. “The bonding equipment is fairly early in their life cycles,” he said. “If you compare 2009 and today, significant progress has been made.”

In any case, the message is clear: The market is screaming for faster machines at a lower cost-of-ownership. “We get the message,” said Paul Lindner, executive technology director for EV Group, a supplier of temporary bonding/debonding and other fab gear. “The price needs to go down. Throughput needs to go up.”

EV Group has installed some tools in various 3D TSV pilot lines, and the company is keeping a close eye on the new entrants in the arena. “In the mainstream 3D chip market, everyone is trying to get a piece of the pie,” Lindner said.

Responding to the throughput issues, EV Group recently rolled out its new equipment platform, dubbed the XT Frame, for its fab tool lines. EV Group’s temporary bonding/debonding system — the EVG 850TB/DB — is the first tool to be built on the XT Frame platform. This enables temporary bonding/debonding at throughputs of 35 to 45 wafers an hour, depending on the application. That’s roughly two to three times faster than previous machines, Lindner said.

Responding to EV Group’s announcement, Suss Microtec last month launched its high-throughput platform, dubbed the XBC300 Gen2. And recently, TEL officially entered the market by rolling out a trio of products. The first product, the Synapse V, uses special-purpose materials to bond wafers to each other. The second tool, Synapse Z, debonds temporarily bonded wafers. And the Synapse S permanently bonds wafers to each other without the use of special materials.

“We can alleviate current throughput bottlenecks and increase productivity,” said Joel Barnett, strategic product manager for surface preparation systems at TEL.

TEL declined to comment on the company’s material suppliers. “There are many competing technology solutions,” Barnett said. “The flexibility of the TEL tool sets allows our customers to utilize almost any material of interest to them.”

Material world

Along with the tools, there are various complex and rival chemistries for temporary bonding. 3M, Brewer Science, Corning, Denka, DuPont, Nitta, Nitto, Schott, SEH, Sumitomo, Thin Materials and TOK provide the chemistries for this application.

“The total number of approaches (in terms of materials) is more than 10 as of today. But this market is still in infancy and no clear temporary bonding technology is emerging,” Yole’s Mounier said in a recent report. “There are numerous collaborations running between tool makers, chemical players and substrate suppliers. Some companies are mastering both process and chemistry, but for others, partnerships are necessary.”

For example, EV Group and Suss have separately announced that they are working with Brewer Science Inc., the inventor of a wafer thinning process called ZoneBOND.  One of the key metrics for temporary bonding/debonding is total thickness variation (TTV) of the wafer, said Jason Neidrich, director of advanced packaging at Brewer Science.

The industry is currently accomplishing TTVs of 5-8 µm. But the industry faces a major challenge: It would really like TTVs of 2 µm or less across the wafer, Neidrich said.

To enable these and other specifications, Brewer Science claims ZoneBOND is the right solution. ZoneBOND defines two distinctive zones on the carrier wafer surface with strong adhesion in the perimeter and minimal adhesion in the center zone. Therefore, only low separation force is required for carrier separation once the polymeric edge adhesive has been removed by solvent dissolution or other means.

In another major alliance, 3M and IBM last year announced they will develop adhesives that can be used for 3D TSVs. 3M makes use of a UV curable adhesive for wafer bonding to glass carriers. After processing, 3M’s “Light-To-Heat Conversion” layer allows low stress, room temperature debonding of the thinned wafer directly to a tape carrier.

Source: Yole

By Mark LaPedus, SemiMD senior editor

Expanding its respective efforts in a hot area, Applied Materials Inc. and the Institute of Microelectronics (IME) have officially opened a 3D chip lab in Singapore at a combined investment of over $100 million.

Applied and Singapore’s IME, a research institute under the Agency for Science, Technology and Research (A*STAR), opened the Centre of Excellence in Advanced Packaging at Singapore’s Science Park II.

In April of 2011, Applied and IME originally announced the research collaboration for advanced packaging in Singapore. As part of the grand opening, announced Wednesday (March 7), Applied said the lab will combine Applied’s equipment and process technology with IME’s research capability in 3D chip packaging. Research activities are already underway with a team of over 50 personnel.

The facility features a 14,000 square foot Class-10 cleanroom and is equipped with an integrated line of 300mm manufacturing systems to support the research and development of 3D chip packaging using through-silicon vias (TSVs). The facility will also allow both parties to pursue independent research initiatives, including process engineering, integration and hardware development.

“Today, we are not only opening the most advanced wafer level packaging lab of its kind in the world, but we are also opening a new product development capability for Applied Materials in Asia,” said Mike Splinter, chairman and chief executive of Applied Materials. “This center will strengthen our ability to advance new technologies and allow us to work more closely with our customers in Asia.”

Applied has a strong presence in Singapore. In 2010, Applied opened its Singapore Operations Center, Applied’s first facility in Asia for manufacturing its advanced semiconductor equipment. The 32,000-square-meter center, located in the Changi North Industrial Park, serves as a hub for Applied’s semiconductor equipment manufacturing around the world, as well as support its worldwide supply chain operations and other corporate functions.

In addition, Applied is a major player in the 3D TSV equipment arena. There are a number of process steps to make a 3D chip. In the via creation or via processing process, there are five main manufacturing steps: etch, chemical-vapor deposition, physical-vapor deposition, electroplating, and chemical mechanical polishing. Applied has an tool offering in these and other segments.

Asked if vertical or 3D memories will boost Applied’s sales, Splinter during a recent conference call said vertical NAND devices will provide the NAND vendors with a renewed ability to cut costs and stay ahead of Moore’s Law. But he said vertical NAND products “are still a few years away.”

For 3D and other areas, Splinter recently said collaboration across the ecosystem will need to be done earlier and at a deeper level. In another example, the Applied CEO recently said tool vendors want more say in the direction of 450mm technology.

Singapore expands in 3D

Meanwhile, Dim-Lee Kwong, executive director of IME, added, “This collaboration will enable the semiconductor industry to accelerate the adoption of 3D chip packaging.”

IME has other alliances in 3D. In 2009, IME launched a 3D chip consortium . The research collaboratively undertaken by members of the 3D TSV Consortium has been carried out in two 18-month phases. Phase one, which is led by IME, serves to establish TSV design and processes for 200mm and 300mm TSV wafer 3D IC assembly. Phase two will demonstrate the integration of functional mobile devices with TSV on a 300mm wafer process line.

Participating companies in phase one of the first 3D TSV Consortium that commenced in September 2009 include GlobalFoundries  Singapore Pte. Ltd., STATS ChipPAC Ltd. and United Test and Assembly Center Ltd.

The 3D TSV Consortium is also supported by 3M, Asahi Glass Co. Ltd., Brewer Science Inc., HD Microsystems, Hitachi Chemical Co. Ltd., Nagase & Co. Ltd., Namics Corporation, Nitto Denko (Singapore) Pte. Ltd., OM Group Ultra Pure Chemicals, Sekisui Chemical Co. Ltd., Shanghai Sinyang Semiconductor Materials Co. Ltd., Sumitomo Bakelite Co. Ltd., The Dow Chemical Company and Thin Materials AG.

Late last year, IME and Tezzaron Semiconductor announced a research collaboration agreement to develop through silicon interposer (TSI) technology. Initial production devices are already in development, based on IME’s TSI technology and incorporating 3D-ICs from Tezzaron. Fabrication will be completed in IME’s 300mm R&D Fab. Tezzaron is having its 3D devices made on a foundry basis by GlobalFoundries.

Directed self-assembly (DSA) technology is expected to take center stage at next week’s SPIE Advanced Lithography conference in San Jose, Calif.

Applied, CEA-LETI, IBM, IMEC, MIT, NIST, Stanford, TEL, the University of Texas at Austin and others will give papers on DSA. And in another major development, R&D organization IMEC (Leuven, Belgium) has announced the implementation of the world’s first 300mm fab-compatible DSA process line.

The process is incorporated within IMEC’s 300mm cleanroom fab. The upgrade of an academic lab-scale DSA process flow to a fab-compatible flow was realized in collaboration with the University of Wisconsin, AZ Electronic Materials and Tokyo Electron Ltd. (TEL).

This research is part of IMEC’s Advanced Lithography Program. IMEC’s key core CMOS partners are GlobalFoundries, Intel, Micron, Panasonic, Samsung, TSMC, Elpida, Hynix, Fujitsu and Sony.

IMEC’s DSA line aims to address the hurdles to bring DSA from the academic lab-scale environment into high-volume manufacturing. DSA is one of the ways to extend optical lithography beyond its current limits, but it is still in the R&D phase.

DSA is an alternative patterning technology that enables frequency multiplication through the use of block copolymers. When used in conjunction with an appropriate pre-pattern that directs the orientation for patterning, DSA can reduce the pitch of the final printed structure.

DSA can be used to repair defects and repair uniformity in the original print. This repair feature is especially useful in combination with EUV lithography.

Source: IMEC

In its DSA efforts, IMEC now has the complete toolset on-site, including a dedicated DSA coater/developer manufactured by TEL with installed DSA materials in gallon-size quantities. IMEC also has a metrology toolkit, including DSA defect inspection, and in-house pattern transfer capabilities all in a representative 300mm cleanroom fab environment.

With established 248nm, 193nm and EUV lithography tool sets on site, IMEC is positioned to study DSA defectivity aiming at increasing the pattern reliability of DSA for semiconductor fab standards. Moreover, IMEC aims at further developing the possibilities of DSA repair in combination with EUV lithography.

“This enables us to expand the scope of our research offering and toolset bringing more value to our partners,” said Kurt Ronse, director of the Lithography Department at IMEC. “The availability of a DSA processing line enables us to further push the limits of 193nm immersion lithography and overcome some of the critical concerns for EUV lithography. This allows us to further push the limits of Moore’s law.”

At SPIE, several entities will give papers on DSA. During the scheduled keynote session on Monday (Feb. 13), Stanford University will give a paper entitled: “Block copolymer directed self-assembly enables sub-lithographic patterning for device fabrication.”

On Tuesday (Feb. 14), TEL will give a paper, entitled: “Pattern scaling with directed self-assembly through lithography and etch process integration.”

On Wednesday (Feb. 15), DSA becomes the hot topic at SPIE. IBM will give a paper entitled, “Measurement of placement error between self-assembled polymer patterns and guiding chemical prepatterns.” On the same day, Applied Materials and IBM are scheduled to give a paper entitled: “Directed self-assembly defectivity assessment.”

In another paper, CEA-LETI will address DSA in a presentation called: “Pattern density multiplication by direct self-assembly of block copolymers: toward 300mm CMOS requirements.”

By Mark LaPedus, SemiMD senior editor

The 450mm era recently celebrated its first milestone with the announcement of a new and major consortium. While the new group — dubbed the Global 450 Consortium or G450C — has gotten the ball rolling in 450mm, the fab tool community has suddenly raised its latest concern about the next-generation wafer size: It wants more participation in the group.

As reported, five major chip makers — Intel, IBM, GlobalFoundries, TSMC and Samsung — in September launched a new consortium in New York aimed at propelling the 450-mm wafer transition. The new group is part of a broad investment among the five chip makers over the next five years.

Today, the running theme in 450mm is not if the technology will happen, but when. But to help make 450mm happen in a timely fashion, Mike Splinter, chairman, chief executive and president of Applied Materials Inc., said the fab tool industry wants more participation in the G450C.

Needless to say, there are no fab tool vendors in the G450C. During a presentation at SEMI’s Industry Strategy Symposium (ISS) at Half Moon Bay, Calif., Splinter urged the industry to create a “forum” in order to “air out the issues” within the G450C.

The fab tool industry “needs representation in the group,” Splinter told SemiMD in a brief interview after the presentation. This in turn would ensure the two factions — the chip and semiconductor equipment industries — “are in lockstep” with each other in 450mm, he said.

He said that the industry trade group — SEMI — is in talks with the G450C to expand the cooperation between chip and fab tool groups. In other words, G. Dan Hutcheson, president of VLSI Research Inc., said the fab tool community would like to move the rhetoric from a “vendor-supplier” relationship to a true “partnership” in 450mm.

Dropping the ball

The industry would also like to avoid past mistakes. In the late 1990s, various chip makers announced plans to build 300mm fabs. The equipment vendors followed suit and developed 300mm tools. Then, the chip makers cancelled or pushed out their 300mm fabs, which caused anger — and losses — among fab tool vendors.

Over time, 300mm fabs were up and running, but the experience left a bad taste in tool vendors’ mouths. In more recent times, leading-edge chip makers, namely Intel, Samsung and TSMC, have pushed for the 450mm wafer size, saying it would provide a 2x to 2.5x productivity gain over 300mm.

At first, tool vendors balked, saying the return-on-investment was questionable, as only a handful of chip makers can afford 450mm fabs. The age-old problem for 450mm is also clear: Who will pay for tool R&D?

Seeking to jumpstart the 450mm efforts, five chip makers in September started the G450C. The G450C demonstration line, to be located in Albany, N.Y., is targeted for 14nm design rules early 2013.

At the same time, there have been some orders for select 450mm gear. So far, however, the industry has spent $500 million on equipment R&D for 450mm, but some $7.6 billion more is needed to finish the work before 2020, Hutcheson warned during a panel discussion at ISS. The other problem is that equipment industry funding has been flat since 2000. “If we assume equipment industry funding will continue to flat line, we have a problem,” he said.

There is also a disconnect between tool vendors and the chip community. For example, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) says it wants a 450mm pilot line by 2013 or so, but one critical tool vendor — ASML Holding NV — won’t devise a lithography system for the technology for 450mm until 2016, he added.

Others also want 450mm sooner than later. “I hope we can do (450mm) in ’14,” said John Chen, vice president of technology at graphics chip maker Nvidia Corp., during a panel discussion at ISS. “Without 450mm, it’s hard to get to 20nm.”

In reality, however, Steve Newberry, vice chairman of Lam Research Corp., believes that 450mm pilot lines will not appear until 2015 or 2016. Production will not occur until 2017, he said.

Still, one G450C member believes the industry is making good progress. The formation of the consortium “is an important milestone,” said Bob Bruck, vice president of Intel’s Technology and Manufacturing Group. “Does it clear the path to 450mm? No.”

Bruck said there are still a number of challenges, but he has been “delighted with the level of interest” and progress with 450mm within the tool community. “Over 95 percent of the (process) requirements have one or more activity developments” within the G450C, he told SemiMD at ISS.

Lithography is the missing piece in 450mm tool development, Bruck said, but he noted that “lithography solutions are in development.” For some time, ASML has stated it would like to finish its work with extreme ultraviolet (EUV) lithography on a 300mm platform before it tackles an EUV-based 450mm project — an event that has slowed overall 450mm development.

“ASML has started research projects” in 450mm, confirmed James Koonmen, senior vice president of ASML and general manager of its Brion unit, during a presentation at ISS. “ASML supports (a) 450 mm post-EUV transition.”

ASML also believes the industry must share in the R&D. “Pre-competitive R&D is a joint semiconductor industry responsibility,” Koonmen said.

There is also a preconceived notion that lithography will have an easier transition to 450mm just by developing a new wafer stage. “It’s not that simple,” said Kazuo Ushida, president of Nikon Corp.’s Precision Equipment Co., during a panel at ISS. Ushida indicated that a 450mm lithography system may require a “more sophisticated lens” and a “redesign in the optics” to accommodate the larger wafers size and exposures.

Regarding the economic issues for 450mm, Applied’s Splinter asked a key question: “How can we get a payback is the question?”

The industry spent $12 billion in terms of fab tool development costs for 300mm, but it took some 14 years to recover the investments. He estimated that the tool development costs for 450mm will run $15 billion to $20 billion, but the return-on-investment remains unclear.

Like many vendors, Applied is quietly developing undisclosed, 450mm tools in-house. The fab tool giant does not want to get burned in 450mm — much like vendors did in the early stages of the 300mm era. “We are trying to pace ourselves properly” in 450mm tool development, he added.

By Mark LaPedus, SemiMD senior editor

Lam Research Corp.’s recent move to buy Novellus Systems Inc. will enable the combined entity to create economies of scale and accelerate its efforts in the fab tool arena, according to a top executive at the firm.

As reported, moving to compete against Applied Materials Inc. and Tokyo Electron Ltd. (TEL) in the broad line fab tool sector, Lam late last year entered into a definitive agreement to acquire Novellus in an all-stock transaction valued at approximately $3.3 billion.

The deal represents a major shift for Lam. For years, Lam focused on primarily one segment — etch — but the company later expanded into the cleaning market by buying SEZ in 2007. With the acquisition of Novellus, Lam has entered into several new and competitive areas, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), electrochemical deposition (ECD) and dry strip.

In a brief interview at SEMI’s Industry Strategy Symposium (ISS), Steve Newberry, vice chairman of Lam, said he did not want to discuss the exact details of the acquisition. In general terms, Newberry said the combined entity will bring economies of scale — and best of breed tools — to the mix. Lam’s claim to fame is providing the best of breed tools in etch, where it is a market leader.

Customers “will still look at best of breed tools,” he told SemiMD, but chip makers also want larger suppliers with a global presence. “Scale matters,” he said. “If you are not globally strong, you will not make the cut.”

During a presentation at ISS, he dropped hints about another motiving factor in the ongoing consolidation among fab tool suppliers. “Equipment company customers are becoming larger with more complexity,” he said. “Spending is consolidating to fewer IC manufacturers and will become more acute as industry moves to 450mm. Fewer dollars need to be concentrated with fewer suppliers.”

Bob Johnson, an analyst with Gartner Inc., said the Lam-Novellus deal makes sense on several levels, including the ability to pool their respective resources in 450mm. “They need size to play in the 450mm area,” he said.

Going forward, look for more consolidation in the fab tool space, as the leading-edge IC makers will require more “scale and scope” with their tool vendors, said Mike Splinter, chief executive of Applied Materials Inc., in a separate presentation at ISS.

C.J. Muse, an analyst with Barclays Capital, said: “The top 5 capex spenders’ proportion of overall industry semi capex has grown from the 40s in the early 2000s to 60 plus percent in 2011.”

On the equipment side, “over the last 10 years the industry has been characterized by increasing concentration. The top 5 equipment players worldwide now control 60 percent of the market, verses the low 50s levels pre-2005,” he said. “And given the recent M&A in the space, we look for this upward trend to continue. Net-net, we see this concentration in the space as normalizing industry profitability across the semi cycle, driven by less duplicated R&D investment, reduced pricing pressure, etc.”

Big fab tool vendors are getting bigger

By Mark LaPedus, SemiMD senior editor

In a major move to diversify its product portfolio, Soitec SA (Bernin, France) has entered into a letter of intent to acquire Altatech Semiconductor, a French semiconductor equipment company.

For the purposes of this transaction, Altatech’s base value was set to 15 million euros ($19.6 million) in stock. With privately-held Altatech, based in Montbonnot Saint Martin near Grenoble, Soitec is entering the fab tool market.

For years, Soitec has sold wafers based on silicon-on-insulator (SOI) technology. The company and its partners are pushing fully depleted silicon-on-insulator (FD-SOI) technology for next-generation devices. More recently, the company moved into the solar space and is selling a photovoltaic concentrator technology.

Now, it is moving into the equipment front. In some respects, Soitec will now compete against the likes of Applied, KLA-Tencor and others.

Formed in 2004, Altatech sells wafer inspection equipment, chemical vapor deposition (CVD) tools and inkjet deposition gear. Altatech recently introduced the AltaSight DarkView product, the company’s first substrate-inspection system to incorporate dark-field detection of defects on unpatterned wafers up to 450mm.

Earlier this month, Altatech entered the light-emitting diode (LED) inspection market by introducing its new AltaSight LEDMax system, the company’s first product designed specifically for detecting, classifying and characterizing defects on wafers used in manufacturing LEDs.

The companies are no strangers to each other.  As a result of the personal interest held by Soitec CEO and Chairman André-Jacques Auberton-Hervé in the capital of Altatech, whose supervisory board he chairs, the transaction was carried out by Soitec’s finance department and the board. The transaction was approved by a decision of the board. Auberton-Hervé neither deliberated nor voted on this transaction.

The acquisition of all of the shares composing the capital of Altatech shall be financed partly in cash and partly using Soitec stock.

Earlier this month, Soitec purchased a manufacturing facility in Rancho Bernardo, Calif., within the San Diego City limits, and will soon begin fitting the factory to produce its concentrator photovoltaic (CPV) modules for the U.S. renewable-energy market.

By Mark LaPedus, SemiMD senior editor

Moving to compete against Applied Materials Inc. and Tokyo Electron Ltd. (TEL) in the broad line fab tool sector, Lam Research Corp. has entered into a definitive agreement to acquire Novellus Systems Inc. in an all-stock transaction valued at approximately $3.3 billion.

The combined enterprise will retain the name of Lam Research Corp. The two companies possess complementary product capabilities, with Lam in etch and single-wafer clean equipment aligning with Novellus in thin-film deposition and surface preparation technologies. The combined company will accelerate their efforts in the 3D and 450mm equipment sectors.

The new and combined Lam will compete in the broad line fab tool market against Applied and TEL. But the blockbuster deal also comes amid a major downturn in the industry. Worldwide semiconductor capital equipment spending is expected to total $51.7 billion in 2012, a 19.5 percent decline from 2011, according to Gartner Inc.

“This strategic combination positions Lam Research to lead the development of next-generation semiconductor manufacturing technology and productivity solutions at a time when growing semiconductor demand and increased device complexity are creating significant business opportunities,” said Steve Newberry, vice chairman and chief executive of Lam Research.

Martin Anstice — who, as previously announced, will assume the position of CEO of Lam Research from Newberry effective Jan. 1, 2012 — will continue as CEO following the close of the transaction. He is currently Lam’s president and chief operating officer.

Timothy Archer, chief operating officer of Novellus, will become chief operating officer of the combined company; and Ernest Maddock, chief financial officer of Lam, will remain chief financial officer. The board of directors of Lam will add four new directors jointly nominated by Lam and Novellus.

Richard Hill, chairman and chief executive of Novellus, does not appear to be part of the equation. He will serve as an adviser for the combined entity. “I will be stepping aside,” he said during a conference call.

The new and combined Lam have “complementary products and technologies,” Anstice said during the call. The deal ”strengthens our position within the industry.”

Founded in 1980, Lam has about 3,750 employees. It had annual revenue of about $3.1 billion. Founded in 1984, Novellus has about 2,700 employees. It had annual revenue of about $1.5 billion.

Lam is the world’s largest plasma etch vendor. In 2007, Lam acquired the SEZ Group, a leading supplier of single wafer clean technology. Meanwhile, Novellus is a supplier of tools in chemical vapor deposition (CVD), physical vapor deposition (PVD), electrochemical deposition (ECD), and dry strip.

Lam has been quietly developing 450mm gear. Novellus has developed alliances in the 3D TSV equipment sector. Both companies have tried but failed in CMP. The combined entity does not have a presence in ion implantation, and, to a large degree, in wafer inspection.

Analysts said the deal makes sense. “While Lam’s shares may come under pressure near-term given the all-stock bid, we like this transaction as we believe it sets the path for meaningful share gains as increasingly more complex semiconductor manufacturing benefits from the combination of the best of breed tools from Lam/Novellus,” said C.J. Muse, an analyst with Barclays Capital.

The deal is “highly complimentary from a customer perspective — Lam is strong at foundry/memory, while Novellus is strong at Intel,” Muse added.

Dean Freeman, semiconductor manufacturing analyst at Gartner Inc., said the deal helps give customers “an alternative to Applied’s TSV process.”  Lam can provide the silicon etch and cleaning processes, while Novellus has the ability to provide the CVD and metallization layers. Customers can turn to Ebara or Applied Materials for the CMP steps in a TSV flow.

Freeman noted that Lam has strengths in customer service and product development, which may help Novellus gain market share in the memory space and with customers Novellus “has shunned in the past.”

On the flip side, Novellus brings its strong presence at Intel to the merger, and opens doors for the expanded Lam Research at Intel in etch and clean. “It is possible that this will now give Lam a better audience at Intel for the etch product.  Lam’s silicon product is superior to both Hitachi and TEL. The dielectric product is on the same level as TEL’s so there is the potential for penetration,” Freeman said.

Also, Lam gains better access to developing etch and deposition processes, creating unit processes, especially for the double and triple patterning that is becoming increasingly common. Potential synergies exist in the etch/strip/clean space as well.

“Novellus is known as the low-cost leader in process efficiency and manufacturing. The merged company can leverage this benefit and create better margins,” he said. However, there are always challenges when different corporate cultures are combined.

The merger could prompt ASM International and Tokyo Electron to step up their own partner searches, perhaps prompting an ASMI/TEL merger, he said. Hitachi HiTech also will need to bolster its silicon position at Intel and other key customers as they are now making equipment decisions at 14nm, Freeman said.

Under the terms of the agreement, Novellus stockholders will receive 1.125 shares of Lam Research common stock for each share of Novellus that they own, in a tax-free exchange. Based on the closing price of Lam’s stock on December 14, 2011, the transaction values Novellus at a price of $44.42 per common share. Upon closing, Lam and Novellus stockholders will own approximately 59 percent and 41 percent, respectively, of the combined company.

Total cost synergies are expected to be approximately $100 million on an annualized basis by the fourth quarter of 2013. In addition, Lam announced a $1.6 billion common stock repurchase program. This new program, which replaces Lam’s existing share repurchase program, is targeted to be executed over the 12 months following the close of the transaction. Lam expects the transaction to be accretive to its non-GAAP earnings within one year after transaction close.

The closing of the transaction is subject to customary conditions, including approval by Lam’s and Novellus’s stockholders and review by U.S. and international regulators. The companies expect the transaction, which has been unanimously approved by both Lam’s and Novellus’s boards of directors, to close in the second calendar quarter of 2012.

By Mark LaPedus, SemiMD senior editor

Semicon Japan kicks off this week amid a flurry of product introductions and mixed signals in the marketplace.

Applied, EV Group, KLA-Tencor, Nikon, Qcept and others have separately announced products at the annual event. On the business front, SEMI projects that worldwide sales of new semiconductor manufacturing equipment will reach $41.8 billion in 2011. The forecast indicates that, following a 151 percent market increase in 2010, the equipment market will expand by 4.7 percent in 2011, according to SEMI.

However, it is forecast to decline about 10.8 percent in 2012 before resuming growth in 2013, according to the industry trade association. “Given the exceptional growth in the market from 2009 to 2010, the lower growth rate in 2011 is expected, not surprising,” said Denny McGuirk, president and CEO of SEMI. “The industry experiences highly cyclical markets, with the rebound likely to occur in 2013.”

Wafer processing equipment, the largest product segment by dollar value, is expected to increase 9.3 percent in 2011 to almost $32.7 billion. The forecast predicts that the market for assembly and packaging equipment will decline by 12.5 percent to $3.4 billion in 2011. The market for semiconductor test equipment is forecasted to decline by 10.3 percent, reaching $3.7 billion this year.

Growth is expected in four regions in 2011— Europe (66.9 percent increase over 2010), North America (53.0 percent), Japan (31.2 percent), and China (2.3 percent). In 2011, North America becomes the largest market for equipment with $8.8 billion, followed by Taiwan ($8.1 billion), South Korea ($8.0 billion) and Japan ($5.8 billion).  Taiwan, South Korea, and Rest of World experienced negative growth rates in 2011.

In 2012, only South Korea is expected to have positive growth (7.5 percent).  In 2013, the market is expected to rebound for all regions except South Korea, due to high growth in 2012.

Novellus Systems Inc. this week gave a mid-quarter update, which was somewhat positive. In a research note regarding the update, C.J. Muse, an analyst with Barclays Capital, said: “Novellus took its 4Q11 order guide to the high end of the range, but kept everything else the same. Management’s tone was more upbeat, with management offering optimistic outlook on capex of roughly flat year-over-year in 2012.”

Muse is slightly bearish for 2012. “We continue to see 2012 WFE tracking -5 percent verses consensus of -10 percent to -15 percent,” he said. ”Orders are trending up in 4Q12 and visibility is improving for 1H12. Optimism around leading edge investments by foundries continues, led by TSMC and Samsung and we expect this spending, plus slightly delayed NAND spending to enable orders to move higher through 1H12, with Cymer suggesting 2H could be better than 1H.”

Meanwhile, at Semicon Japan, vendors rolled out a host of tools:

•Altatech Semiconductor S.A. has entered the light-emitting diode (LED) inspection market by introducing its new AltaSight LEDMax system, the company’s first product designed specifically for detecting, classifying and characterizing defects on wafers used in manufacturing LEDs. Using Altatech’s patented sensor technology that filters out all background noise, the non-contact system generates images of surface imperfections with resolution down to 1 micron and a unique depth-of-focus capability approaching 500 microns.

•Applied Materials Inc. extended its efforts in defect review SEM technology with the launch of its Applied SEMVision G5 system – the first tool that enables chipmakers to image and analyze 20nm yield-limiting defects in a production environment without manual intervention. Uniquely capable of identifying and imaging relevant defects with 1nm pixel size, the SEMVision G5 system allows logic and memory customers to streamline manufacturing, pinpointing the root cause of defects faster and more accurately than ever before.

•EV Group has introduced a new equipment platform, dubbed the XT Frame, that extends process throughput and tool functionality for virtually all of its current volume-manufacturing product offerings.  Specifically designed to address new requirements from its high-volume manufacturing (HVM) customers, the XT Frame can accommodate up to nine process modules-doubling EVG’s previous maximum processing capability for significantly increased throughput.

•KLA-Tencor Corp. introduced new additions to its SensArray portfolio of advanced wireless temperature monitoring wafers. The portfolio implements time-based, in-situ temperature monitoring to capture the effect of the process environment on production wafers. Developed through collaboration with leading IC manufacturers and original equipment manufacturers (OEMs), the EtchTemp-SE (ET-SE), ScannerTemp and WetTemp-LP products enable customers to monitor temperature information across the entire wafer surface under real process conditions.

•Nikon Corp. announced the NSR-S320F scanner delivering productivity and superior overlay accuracy for the most challenging dry 193nm layers. The combination of the Stream Alignment and Five-Eye FIA systems enable throughput capabilities of up to 200 wafers per hour. In addition, the Bird’s Eye Control system uses interferometers in conjunction with encoders to deliver overlay accuracy ≤ 3 nm with optimal stability. The scanners will begin shipping in the fourth quarter of 2011.

•Qcept Technologies Inc.  introduced its ChemetriQ Inspection Services (Q-Services). With Q-Services, customers send their substrates to Qcept, which provides an inspection scan with its patented scanning Surface Potential Difference Imaging (SPDI) sensor technology, and then conducts data analysis and reporting relative to the customer’s experimental studies.

•SUSS MicroTec launched the XBS300 Temporary Bonder, its latest generation of high volume manufacturing temporary bond systems. This Bond Cluster is configured to temporarily bond 200mm and 300mm wafers for 3D integration applications as well as other processes that require thin wafer handling. The XBS300 supports all currently available temporary bonding adhesives.