The last six months have seen several developments concerning 3D memory concepts moving into production, from companies such as Samsung, Micron, Toshiba and Sandisk. What follows are excerpts from a roundtable discussion with SemiMD, Samsung Electronics (SE) in South Korea, which has begun production of its proprietary 3D NAND technology, Bradley Howard, Vice President of Advanced Technology Group, Etch Business Unit, at Applied Materials and Jim Handy from Objective Analysis, which specialises in coverage of the memory industry.
SemiMD: Where does 3D NAND fit into the long-term roadmap for memory technology and is there one technology most likely to dominate?
SE: We successfully came out with the industry’s first 3D NAND (V-NAND) in August 2013, which offers 128 GB on a chip and vertically stacks cell layers that make use of charge trap flash (CTF) technology. The V-NAND has already been used in 960 GB solid state drives (SSDs) for server and enterprise applications.
The V-NAND technology is expected to replace planar NAND market gradually, starting from the high-end enterprise market. We will continue to come up with more advanced V-NAND products with higher density and reliability. The company has also been working on a diversity of next-generation memory technologies including RRAM (or ReRAM) while strengthening its future business competence.
Howard: All major memory customers have 3D NAND transition in their roadmap. We’ll soon see the first generation of 24-layer 3D cell array devices enter the market. RRAM and STT-MRAM technologies are further out from the market as there are still critical process and manufacturing challenges for both the materials and patterning.
Handy: NAND will dominate. 3D NAND is less disruptive than alternative technologies, like RRAM, since it involves the same materials that have been used to produce NAND for its entire lifetime, while RRAM, MRAM, FRAM and so on require new materials that are not as well understood. After 3D NAND has reached a limit and can no longer place increasing numbers of transistors onto a wafer then the door is opened for alternative technologies like RRAM, but that won’t happen until 2023.
How is the semi industry (such as foundries and designers) preparing for the transition to 3D memory?
Handy: The bulk of the semiconductor industry doesn’t need to transition since these technologies are only being used for the highest-density discrete memory chips. The most significant impact should be to the capital equipment market, where a move to 3D could increase materials equipment usage while decreasing spending on lithography tools.
SE: We are working closely with global IT companies in a wide range of fields to expand the market base and application of 3D V-NAND, and we expect that the market will grow rapidly throughout the year. The 3D V-NAND is expected to be adopted in many different applications including SSDs, high-density memory cards and other applications for consumer electronics. While Samsung will work on more V-NAND based applications, the company also will contribute to global IT companies’ development of next-generation IT systems using our 3D V-NAND products.
Are there specific tooling challenges that must be overcome?
SE: The key technologies for V-NAND would be applying 3D CTF structure for individual cells and constructing vertically interconnected cell arrays. We have mastered these technological challenges and will continue to come up with more advanced V-NAND products.
Howard: Fabricating vertically to build multilayer stacks of 3D NAND cells reduces the historical reliance on lithography as the dominant and limiting factor in scaling, and increases the role of materials-enabled deposition and etch to drive vertical scaling. This shift brings formidable device performance and yield challenges for deposition and etch technologies including distortion-free high aspect ratio etching, complex staircase patterning with precise step-width control, and uniform and repeatable deposition.
From a 3D NAND fab perspective, the changing balance of tool types toward significantly more deposition and etch equipment will have a substantial impact on tool footprint and fab layout to enable optimum manufacturing efficiency. Moreover, this new tool balance compromises the capability to adjust manufacturing capacity between NAND and DRAM since planar NAND and DRAM share a high level of commonality with regard to the balance of tool types and lithography.
Handy: For 3D NAND there are significant challenges in putting down layers that have uniform thickness across the entire wafer. There are also issues with pull-back etching for stairsteps that currently increase the lithography load more than was originally anticipated, but this issue should eventually be solved. For alternative technologies there will be issues in bringing new materials into the fab, some of which are antagonistic to the underlying silicon.
To what extent can 3D memory chips be scaled and what challenges does this pose?
Howard: Scaling for the first few generations, from 32 to 48 to 64 and higher cell layer stacks will largely be a matter of adding more vertical layers. The general consensus is that this is sustainable to around 100 device layers, and this will likely require some amount of reduction on the layer thicknesses to control the aspect ratios that must be etched. Even small reductions in thickness are critical, because any reduction gets multiplied by the number of layers. Scaling beyond this will likely require more effort towards thinning the layers through advancements on the device architecture.
Lithographic-based horizontal scaling will continue, but instead of the historical 15-20 percent CD reduction per generation, we expect planar scaling to slow dramatically, equivalent to a CD shrink more on the order of ~5 percent per generation. In addition, layout changes in the peripheral circuits to achieve more efficiency, along with more efficient designs for the complex staircase structure to allow for access to the different layers, are expected. These will all play a role in overall die size efficiency.
For deposition, major challenges to effectively scale vertically are advanced thickness and uniformity controls layer to layer. Any non-uniformity in a film layer will propagate throughout the stack as subsequent layers are deposited on top of it. With more layers in the device stack, this results is more devices potentially impacted by topography.
The challenge for etch is growing high aspect ratios despite a thinning down of individual layers in the stack. Aspect ratios today are already at 60:1. Achieving etch fidelity at such aspect ratios puts pressure on getting higher selectivity to the mask material which already is very thick. In some cases, the aspect ratio for the hard mask is already greater than 20:1, and this is the aspect ratio before even starting the etch into the device stack. While thinning the hard mask layer reduces the overall aspect ratio of the feature, new more resilient patterning films will be required. Higher selectivity will be through a combination of new materials with higher etch resistance and improvements to the etch process chemistry.
SE: We have core technologies to develop more advanced high-density V-NAND devices and are seeking to define manufacturing technologies for stacking more than 24-cell-layer structure which was applied to our first 3D V-NAND device.
The most advanced process technology for conventional NAND using floating gate would be 10 nm-class technology. However, process technology refers to the width of integrated circuitry that is used for NAND on a conventional planar structure. Applying the same considerations to our V-NAND would not be appropriate because the cell array structure has been totally changed.
For example, if we compare the wafer productivity of Samsung’s new 128 GB V-NAND to previous products, it has the approximate chip size of a conventional NAND that was built using approximately mid-10nm-class process technology.
The 3D V-NAND has its strength in scalability. There are plans to continue developing more advanced V-NAND products and applications including 1 TB and higher-density SSDs for servers and enterprise systems and other next-generation memory storage which should lead to the growth of the overall NAND flash market.
Handy: 3D NAND is expected to scale in height, from 16-bit-tall strings to string heights of more than 128 bits. Meanwhile NAND makers will probably find ways of placing these strings closer to each other through more aggressive lithography. There is a lot of room for scaling in 3D.
Everything in 3D is a significant challenge. With vertical scaling the challenges include etching high aspect ratio holes, with the aspect ratio doubling with each doubling of layers. These holes must have absolutely parallel walls or scaling and device operation may be compromised. If the layers are thinned then the atomic layer deposition (ALD) of the layers must be able to apply a constant thickness layer across the entire wafer. This is also true of the layers that are deposited on the walls of the hole. The entire issue of 3D is its phenomenal complexity.