By Mark LaPedus
It’s the worst-kept secret in the industry. Extreme ultraviolet (EUV) lithography has missed the initial stages of the 10nm logic and 1xnm NAND flash nodes.

Chipmakers hope to insert EUV by the latter stages of 10nm or by 7nm, but vendors are not counting on EUV in the near term and are preparing their back-up plans. Barring a breakthrough with EUV or other technology, IC makers will likely use today’s 193nm immersion with multiple patterning at 14nm, 10nm and perhaps beyond. “10nm will be optical,” said Ajit Manocha, chief executive of GlobalFoundries. “We have evidence that we can do 7nm with immersion.”

GlobalFoundries, for one, is laying the groundwork if EUV is ready by 10nm. “We are keeping our ground rules migrate-able to EUV,” added Subramani Kengeri, vice president of advanced technology architecture at GlobalFoundries.

Chipmakers are keeping their options open for good reason—extending optical comes with a penalty. The shift from single patterning at 28nm to multiple patterning at 20nm is projected to increase lithography costs by up to 56%, according to Barclays Capital. Consequently, the overall cost-per-transistor curve is in danger of slowing or derailing.

Lithographers, who seem to achieve miracles when the chips are down, are determined to stay on Moore’s Law. “The cost of processing might go up with multiple patterning, but cost-per-transistor does not,” said Yan Borodovsky, a senior fellow and director of advanced lithography at Intel.

The ability to stay on the critical cost-per-transistor curve puts enormous pressure on the lithographic supply chain, which includes the EDA houses, materials suppliers, mask shops, and tool vendors. In response, Nikon is quietly shipping a faster scanner for 10nm. Lithographers also may resort to some new patterning tricks. The wild card is directed self-assembly (DSA), an alternative lithography technology that makes use of block copolymers to enable fine pitches.

EUV woes
For years, there have been fears that optical lithography would run out of gas, prompting the need for a new next-generation lithography (NGL). EUV emerged as the leading NGL candidate. The other NGLs, maskless and nanoimprint, are also in the hunt.

EUV, a soft X-ray using 13.5nm technology, is attractive because it keeps the industry on a single-exposure path. But EUV has encountered several delays due to the lack of adequate power sources, defect-free photomasks and photoresists.

The current throughput for ASML’s EUV tools is less than 10 wafers an hour (wph). At one time, ASML hoped to ship an EUV scanner with a 150-watt source by mid-2012. A 150-watt source equates to a more acceptable throughput of 69 wph.

Recently, the 150-watt source was delayed again and pushed out to mid-2014. The source is being developed by Cymer, which itself is being acquired by ASML. Separately, Intel, Samsung and TSMC have recently invested in ASML to help fund ASML’s efforts in EUV and 450mm.

ASML is still targeting EUV for mass production in 2014, but the industry isn’t taking any chances and will extend 193nm immersion—at a price. On average, there are 37 lithography layers processed for 32nm/28nm chips, according to Barclays. Of those, there are 14 critical layers processed using 193nm immersion scanners.

In total, there are 38 lithography exposures at 32nm/28nm, 15 of which are immersion exposures, with only one multiple patterning step in the flow, according to Barclays. In terms of lithography equipment costs at 32nm/28nm, a foundry spends an estimated $17 million per 1,000 wafer starts per month (wspm).

In comparison, there are 40 lithography layers for at 22nm/20nm chips, 19 of which are critical layers. In total, there are 52 lithography exposures at 22nm/20nm, 31 of which are immersion exposures with 11 multiple patterning steps. All told, a foundry is expected to spend $27 million per 1,000 wspm in lithography costs, according to the firm.

Lithography steps and costs will soar at 14nm and beyond. In response, chipmakers already are prepared for the dreaded multiple patterning era. NAND flash vendors, for example, are using a multiple patterning technique called sidewall image transfer (SIT), sometimes called self-aligned double patterning.

In logic, vendors have or will implement one of the various flavors of multiple patterning: SIT, litho-etch-litho-etch (LELE) or self-aligned vias. Intel, for one, is embracing a concept called complementary lithography, which involves an SIT flow. Other logic vendors are following a similar path with various nuances.

Today, Intel is using 193nm immersion with multiple patterning at 22nm, with plans to extend that to 14nm. At 22nm, Intel’s processors are based on finFETs. “For the 22nm node, our fin is finer than what can be done with simple patterning. It’s done with pitch division. We still stay on an historical cost-per-transistor trend,” said Intel’s Borodovsky. “Our 14nm technology is also pitch-divided technology. We project our cost-per-transistor will remain on the trend.”

For 11nm, Intel is looking at quintuple exposure. As part of the process, there are two steps, gratings and line cuts, to pattern designs. Using 193nm immersion, the first exposure is used to make the gratings. The remaining four exposures are used to cut the pitch-divided lines.

To perform the cut step, Intel is evaluating several options: 193nm immersion; DSA, EUV; or direct-write e-beam. So far, there is no clear winner—193nm immersion is challenging, but DSA, EUV and maskless are not ready for mass production.

“I believe we can extend (193nm immersion) for many years,” Borodovsky said. “We also have a dual wave lithography roadmap. It means we will extend existing technology as long as possible. And we will bring in new technology when it is available and affordable.”

Using NGL has some advantages over optical. “If we use EUV, we will use one mask to do the gratings and another mask to break those continuities. If we use direct write, we don’t use any masks,” he said.

Another technology, DSA, potentially could extend 193nm lithography beyond 10nm. As before, the challenges for DSA are defects and the lack of a design infrastructure. The new gap for DSA is non-destructive metrology as a means to inspect the morphologies in the patterns.

DSA materials providers have said DSA would be ready at 10nm, but there are signs the technology may get pushed out. For example, IBM is targeting DSA for 7nm, said Gary Patton, vice president of the Semiconductor Research and Development Center at IBM.

“DSA is making progress,” said Intel’s Borodovsky. “But let’s say we use DSA. If you look at a SEM, you look at the top. Everything may appear perfect. But the cylinders could also change their shapes from top to bottom. You have to have a cross section. So, it’s very difficult to do a cross section of 15nm holes or cylinders. You can do complicated X-ray metrology. For this, you need a synchrotron source, which is not practical.”

Etch is another roadblock. Some of the cylinder morphologies in DSA structures are uniform while others are not. “Some would etch to the bottom. You might also have cylinders that are etched in the wrong place. That’s an edge-placement error,” he added.

The solutions
Until NGL is ready, chipmakers are stuck. “I don’t think the industry has given up on EUV. EUV will be in play, but it will be in limited use,” said Hamid Zarringhalam, executive vice president at Nikon Precision. “But for 10nm, almost all logic vendors are looking at immersion technology. Customers are even looking at extending immersion beyond 10nm.”

To keep up with the increase in multiple patterning steps, ASML and Nikon are shipping faster scanners. Nikon, for one, has begun shipping the NSR-622D, a 193nm immersion scanner for the 10nm node. The tool has a throughput of 200 wph. In addition, Nikon is also developing a separate 193nm immersion tool for the 450mm wafer size.

Besides lithography scanners, there is an urgent need for new and faster e-beams in photomask production. Mask making itself is quickly turning into a fine and precise art. In quadruple patterning, for example, the patterns must be split into four masks.

“One mask has to be perfect in terms of CD uniformity, linearity and defects. The other three masks have to be exactly the same,” said Amitabh Sabharwal, general manager for mask etch products at Applied Materials. “When you start going down to the 16nm node, the CD uniformity targets become very, very tight. We’re talking in the range of 1nm. And on top of that, the defect levels might be very tight. Your systematic uniformity has to be zero. Essentially, everything must be flat.”

Looking into his crystal ball, lithography expert Chris Mack predicts that the industry will embrace new design methodologies such as 1D layouts. “We will see more interaction between lithography and design,” Mack said. “The reality of what we can accomplish lithographically will have more influence on the way designs are implemented. In fact, this might not be a bad thing. The switch from arbitrary designs to more (1D-like layouts) is turning out to have less impact on chip area than many people expected. And they are lithographically friendly.”

The industry also will embrace complementary lithography or hybrid approaches. “There is no doubt in my mind that optical will go forever,” he said. “But I do think there is a possibility of hybrid lithographic approaches that are optimized for specific types of patterns. Complementary lithography is a powerful technique and makes the most sense. All of the (NGLs) have a lot of potential, but they are not being developed in the timeline the industry needs.”

By Mark LaPedus
A year ago, chipmakers were reeling from a severe shortage of 28nm foundry capacity, prompting foundries to ramp up their fabs at a staggering pace.

At the time, foundries were unable to keep up with huge and unforeseen demand for mobile chips. The shortfall was also caused by low yields and the overall lack of installed 28nm capacity.

Today, the 28nm crunch is largely over. The foundries have caught up with the demand and customers no longer are feeling the pinch. And as it turns out, 28nm is a sweet spot for many devices and the technology will remain a long-lasting node.

However, the overzealous foundries may have expanded too fast. In fact, there are some signs of a possible foundry glut, and falling fab utilization rates, for 28nm and other processes in 2013. “I don’t see a shortage problem,” said Samuel Wang, an analyst at Gartner. “But overall utilization rates for advanced technologies will go down this year.”

Mobile chipmakers represent the biggest customers for foundries, but pockets of the business are cooling off to some degree. So, unless there is a steep upturn in the near term, the foundry market may quickly turn into a buyers’ market in 2013. Average selling prices for wafers could steadily drop, putting a squeeze on foundry margins.

Besides 28nm, foundries are simultaneously developing 20nm planar and 14nm-class finFETs. In doing so, foundries are moving toward the long-awaited “virtual IDM” model, where vendors and customers collaborate more closely under the same roof.

The shift towards the “virtual IDM” model is easier said than done, however. “The foundries will have some obstacles,” said Robert Bruck, vice president and general manager of the Technology Manufacturing Engineering Group at Intel. “Design, process technology, development and equipment costs are going up.”

As the costs and challenges mount, there are signs that the leading-edge foundry business is ripe for a shakeout. Currently, there are six companies that provide leading-edge foundry services in one form or another: GlobalFoundries, IBM, Intel, Samsung, TSMC and UMC.

28nm glut?
In total, the IC market is expected to increase 6% in 2013, compared to a drop of 1% in 2012, said Bill McClean, president of IC Insights. Capital spending is expected to fall 10% in 2013, but foundry CapEx will remain flat this year, he added.

For 28nm alone, the foundries had a total capacity of 200,000 wafer starts per month (wspm) by the end of 2012, according to Barclays Capital. In 2013, the foundries are expected to add an additional capacity of 75,000 to 100,000 wspm for 28nm, according to Mike Splinter, chairman and chief executive of Applied Materials.

And at 20nm, the foundries are expected to have a total capacity of 25,000 wspm in 2013, Splinter said in a recent conference call. Most of that capacity will be added in the second half of 2013, he said.

Splinter projects that the worldwide wafer fab equipment (WFE) market will be flat to minus 10% in 2013, up from minus 5% to minus 15% from his previous forecast. “We think the foundries will be down, but not as low as we expected,” he said.

CapEx race
Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) is showing no signs of a slowdown. The world’s largest foundry vendor has increased its capital spending from $8.3 billion in 2012 to $9 billion or more in 2013.

For 28nm, TSMC is expanding its capacity threefold in 2013 over 2012, said Morris Chang, chairman and chief executive of TSMC. In 2012, the polysilicon version of 28nm represented 100% of TSMC’s output. TSMC is expanding its 28nm high-k/metal-gate technology, which will reach the crossover point in the third quarter of 2013, he said.

The company also sees strong demand for 20nm. Apple will have its upcoming 20nm A7 application processors made on a foundry basis by TSMC, according to Barclays Capital, which noted that Apple is switching foundry vendors from Samsung to TSMC.

Meanwhile, GlobalFoundries, the world’s second largest foundry vendor, has set its capital spending budget at $3.5 billion in 2013, said Ajit Manocha, chief executive of GlobalFoundries. In 2012, GlobalFoundries’ capital spending hit $3.2 billion, according to Barclays.

The spending will help GlobalFoundries’ efforts to become more of a “virtual IDM.” In January, GlobalFoundries announced plans to build a multi-billion dollar R&D facility at its Fab 8 campus in Saratoga County, N.Y. The company’s new Technology Development Center (TDC) will help accelerate its 10nm and 7nm process development.

The TDC will also house part of GlobalFoundries’ stacked-die packaging and advanced photomask efforts. As photomask complexities soar, “some customers want a turnkey solution,” Manocha said.

Within its new 300mm fab in New York, the company has begun ramping up 28nm and 20nm processes. In 2013, Fab 8 is expected to expand from 10,000 to 30,000 wafers a month. “That’s still on plan,” he said. “We are also expanding our fab production in Dresden and Singapore.”

In total, GlobalFoundries will offer five technology platforms: bulk planar, bulk finFET, super-steep retrograde well (SSRW), FD-SOI (minimum) and FD-SOI (maximum). Customer tapeouts for its 14nm-class finFETs are expected in 2013, with production slated for 2014.

The maximum version of FD-SOI is tuned for specific applications, said Subramani Kengeri, vice president of advanced technology architecture at GlobalFoundries. Meanwhile, the minimum version is a simple and an “out of the box” FD-SOI technology, Kengeri said.

The company will provide FD-SOI wafers on a foundry basis for STMicroelectronics and other customers. GlobalFoundries’ 28nm FD-SOI process will move into risk production in the fourth quarter of 2013, with production slated for the first quarter of 2014.

Meanwhile, amid the apparent loss of a major customer in Apple, Samsung has cut its logic capital spending from 8 trillion Korean won in 2012 to between 4 trillion and 4.5 trillion Korean won in 2013, according to Barclays. Apple accounts for roughly one-third of Samsung’s logic capacity.

Samsung’s main logic/foundry fab is called S1, which is in Korea. S1 is making 28nm devices and is capable of low-volume finFET production. “S1 has more than doubled its size over the last year,” said Ana Hunter, vice president of foundry services at Samsung Semiconductor.

In Austin, Texas, Samsung has two 300mm fabs, plus a copper metallization facility. One fab is a foundry/logic plant. The fab, dubbed S2, has been a dedicated foundry plant for Apple. The other fab in Austin was previously a NAND facility. Last year, Samsung converted that fab from NAND into a 28nm logic/foundry plant.

In 2012, the company put on the brakes on its new S3 fab, a 300mm plant in Korea. “S3 resumed construction at the end of January,” said Christian Gregor Dieseldorff, an analyst at SEMI. “Equipment may begin to move in by mid-year. I think this may be the earliest.”

The S3 fab, which is expected to ramp up in 2014, will manufacture 20nm planar devices and 14nm-class finFETs. With process design kits available today, Samsung is expected to sample finFETs in 2014. In addition, the company has deployed “training teams” to help customers with their finFET designs, Samsung’s Hunter said.

The complexity of new and advanced designs will require more handholding between the foundries and their customers. “The collaboration has to get deeper with customers,” she added.

In moving towards the virtual IDM model, the foundries face some challenges. “There are very large investments that are required,” Intel’s Bruck said. “How do you accelerate the yield learning? What about the IP issues? Another aspect in terms of the foundry model is the delay that we are seeing in terms of revenue on the leading-edge.”

All chipmakers, including Intel, face the same challenge: How to keep up with the soaring R&D costs associated with the new and emerging technologies? “R&D is weighing on every level on the supply chain in this industry,” he added.

Foundry companies are keeping a close eye on Intel. To date, Intel is only providing foundry services to a limited customer base, and shows no signs of expanding the offering to a broader audience. So far, the chip maker is providing its 22nm finFET technology on a foundry basis to flow processor supplier Netronome and two FPGA vendors, Achronix and Tabula. In addition, Intel recently announced capital spending of $13 billion in 2013, including $2 billion for 450mm development.

Meanwhile, Taiwan foundry vendor United Microelectronics Corp. (UMC) continues to fall behind, as the company said it is having yield issues with its 28nm process. In addition, UMC recently said it will move directly from 28nm to 14nm finFETs, thereby skipping the 20nm node.

By Mark LaPedus
The IC industry entered the finFET era in 2011, when Intel leapfrogged the competition and rolled out the newfangled transistor technology at the 22nm node.

Intel hopes to ramp up its second-generation finFET devices at 14nm by year’s end, with plans to debut its 11nm technology by 2015. Hoping to close the gap with Intel, silicon foundries are accelerating their efforts to introduce their initial finFET processes at 14nm. And the foundries are already defining their next-generation finFETs at 10nm.

Chipmakers face numerous challenges in terms of ramping up their first- and next-generation finFETs. But the challenges, and costs, could pale in comparison when vendors extend finFET technology to the 7nm and 5nm nodes—or perhaps beyond.

Starting at 7nm, chipmakers plan to inject finFETs with various and exotic III-V materials in the channels to boost the mobility, which refers to how fast the electrons can move through a device. Currently, the industry has narrowed the options down to about five leading candidates for the high-mobility finFET era: finFETs with germanium (Ge) for the PFET; finFETs with Ge for both PFET and NFET; and finFETs with Ge for PFET and III-V materials for NFET.

The two possible spoilers are tunnel field-effect transistors (TFETs) and nanowire-based gate-all-around finFETs. “Conventional thinking currently suggests that we will see a Ge PFET and an InGaAs NFET at 7nm,” said Dean Freeman, an analyst with Gartner. “If the industry could make a silicon nanowire, and create a transistor using silicon and high-k/metal-gate, then we could see the industry move in that direction.”

The III-V materials themselves exist today, but many of the associated manufacturing techniques are in their infancy or simply don’t exist. Bringing up compound semiconductor materials in silicon fabs is a monumental task. And the ability to design and integrate III-V finFETs in a cost-effective manner is easier said than done. “This is not a straightforward process,” said Luc Van den hove, chief executive of IMEC. “We are talking about materials with different lattice constants.”

The challenges leave some observers wondering whether chipmakers should skip the high-mobility finFET era and move directly to the more exotic technologies like carbon nanotubes and graphene. Perhaps the best avenue is the pursuit of stacked 2.5D/3D devices.

Looking into his crystal ball, Gary Patton, vice president of IBM’s Semiconductor Research and Development Center, predicts the two 3D-like approaches, finFETs and stacked die, will have a long and viable future. “The 3D era should carry us well into the 2020 timeframe,” Patton said. “I expect finFETs will last a decade. But then at some point, we hit the atomic dimension limit. Then, we’re talking about silicon nanowires and carbon nanotubes. And to deal with the interconnect issues, we have to talk about integrating photonics on the chip and stacking multiple chips together. That’s really in the next decade.”

Take III-V
Today, the industry is moving towards an inflexion point. For foundries, 20nm represents the last node in the planar era, because planar is beginning to suffer from undesirable short-channel effects. So, at 14nm, foundries will introduce finFETs, which have better short-channel electrostatic characteristics than planar.

Today’s finFETs will likely scale at least two generations to 10nm, said Subramani Kengeri, vice present of advanced technology architecture at GlobalFoundries. Then, at 7nm, the industry is looking at next-generation finFETs based on III-V materials to provide a mobility boost, Kengeri said.

The next roadblock is that today’s strained-silicon technology is under stress. For some time, chipmakers have used a silicon-germanium (SiGe) alloy stressor in the channel to boost carrier mobility. “Starting from the 90nm and 65nm nodes, the source-drain areas have been grown using a SiGe epi process in order to bring strain into the device,” said IMEC’s Van den hove. “With strain, we can increase the drive current and device mobility. In the finFET structure, we can do that as well. But this space is very limited, because of the [difficulties] to introduce enough strain into those tiny channels. An alternative way to boost the drive current is by using materials that have intrinsically higher mobilities. This will reduce power consumption.”

The first of these high-mobility devices is expected to appear at 7nm, with the emergence of a finFET with Ge in the p channel and tensile silicon in the n channel. Ge has an electron mobility of 3,900cm-square-over-Vs, compared to 1,400cm-square-over-Vs for silicon.

“But germanium in the p channel is not a straightforward process,” said Aaron Thean, director of the logic program at IMEC. “Germanium tends to move around once exposed to temperature. So the challenges are defects and the structural stability of the device. The surface passivation (for the high-k/metal-gate stack) is also very tricky.”

Following this device, the industry will move to a next-generation high-mobility finFET at 7nm. The first option is a finFET with Ge for both the p and n channels. The second option is Ge for the p channel and indium gallium arsenide (InGaAs) for the n channel. InGaAs has an electron mobility of 12,000cm-square-over-Vs.

“Those two options are competing,” Thean said. “The germanium-germanium option requires compressively strained Ge in the p channel and relaxed Ge in n channel. There are issues with the gate stack and dopant activation.”

Intel and others are leaning toward the Ge-InGaAs option. “InGaAs is our front-up option. It can offer mobilities up to 10X and higher. It’s a better-understood III-V material. I wouldn’t say InGaAs is easy in terms of processing, but it is not as challenging of a material to handle,” Thean said.

The other 7nm candidate is the gate-all-around (GAA) finFET, which can have two or more gates that are wrapped around by a nanowire channel. Purdue University, for one, recently demonstrated GAA finFET with 20nm channel lengths and a sub-threshold swing of 63mV/decade. “There are still lots of challenges with GAA,” said Jiangjiang Gu, a Ph.D. candidate at the Department of Electrical and Computer Engineering at Purdue. “We still need to address the source/drain contact issue. The surface roughness needs to be improved and the variability issues need further study.”

Intel and others also have shown interest in the TFET, which may appear at 5nm. In TFET, a tunnel barrier is created at the source-channel contact to increase the drive currents. Using III-V materials, the TFET promises to scale the supply voltage beyond 0.5 volts, said Mark Bohr, senior fellow of the technology and manufacturing group at Intel. “TFETs enable steeper sub-threshold voltages,” he said.

There are other options, such as exotic III-V materials for both NFET and PFET. Other III-V materials, including indium antimonide (InSb), are still in R&D. The Sb materials are promising, but have narrow band gaps.

Tool gaps
All of the futuristic, high-mobility finFET devices suffer from the same problem—they are expensive and difficult to manufacture. The most obvious problem is lithography. It’s still unclear if extreme ultraviolet (EUV) lithography will be ready for the 7nm node, meaning the industry may need to extend 193nm immersion and multiple patterning.

Patterning is only one piece of the finFET puzzle. “Lithography has been the story for at least the last 10 years,” said Mike Splinter, chairman and chief executive of Applied Materials. “Now, we are seeing many of the bottlenecks in interface engineering, precision materials and how are you going to get the low-k values.”

For example, RF chipmakers have been fabricating III-V chips in trailing-edge fabs at smaller wafer sizes. At 7nm, the challenge is to grow III-V materials on 300mm or 450mm silicon wafers with good yields and throughput.

It’s unclear which technology, bulk or FD-SOI, will prevail at 7nm and beyond. STMicroelectronics says FD-SOI can extend to at least 10nm and perhaps beyond. “We are continuing to look at SOI,” said IMEC’s Thean. “The nice thing about fully-depleted devices on SOI is that they have excellent isolation.”

In one emerging SOI effort, Ed Nowak, device chief designer at IBM, recently described a fin-on-oxide (Fox) technology that could scale to 5nm. Fox enables a finFET technology with oxide dielectric isolation. Like SOI, Fox enables the finFET manufacturer to produce a controlled fin height, thereby reducing variability. Silicon wafer maker MEMC recently rolled out SOI substrates based on Fox.

The integration between III-V and silicon is perhaps the biggest issue. “In III-V, for example, we use gold as a contact material,” said Raj Jammy, vice president of emerging technologies at Sematech. “Gold is a poisonous material for silicon. So, you need to come up with a new contact metal scheme.”

There is also a need for new metrology tools to find defects in III-V finFETs. New tools are also are required for GAA finFETs with nanowires. “When it comes to gate all-around, you need selective ALD processes,” Jammy said. “For fin/gate fidelity, this requires selective III-V/Ge epi. For etch, we might not be able to use the processes we have today. We are looking into ALD etch.”

The industry is making progress on one front. “One of the areas we are looking at is a low damage conformal 3D doping technique, which we call monolayer doping,” he said. “This enables selective and very shallow junctions. We have solutions with arsenic and phosphorous. What is exciting about this is that the fins that have monolayer doping don’t have any damage.”

All told, high-mobility finFETs promise to enable chip scaling, but the challenges and costs are steep. “There is no free lunch,” he added.

By Mark LaPedus
Is the cell phone market cooling down? Worldwide mobile phone sales totaled 1.75 billion units in 2012, a 1.7 percent decline from 2011 sales, according to Gartner. The last time the worldwide mobile phone market declined was in 2009. On the bright side, smartphones continued to drive overall mobile phone sales, and the fourth quarter of 2012 saw record smartphone sales of 207.7 million units, up 38.3% from the same period last year.

Egypt’s Si-Ware Systems, a fabless chipmaker, has licensed its MEMS FT-IR spectrometer technology to Hamamatsu Photonics. The FT-IR spectrometer is the world’s first single-chip spectrometer. The technology is based on Si-Ware’s Silicon integrated Micro Optical System Technology (SiMOST). With the technology, multiple optical MEMS structures can be patterned and etched on SOI wafers using deep reactive ion etching. The structures are then wafer-level packaged and diced to create a one-chip optical system. 4

Applied Materials reported its Q1 results for fiscal 2013. Orders grew 44% sequentially led by demand for semiconductor and display equipment.

In its conference call, Mike Splinter, chairman and CEO of Applied, said: “We now believe the 2013 wafer fab equipment will be flat to down 10% relative to 2012 spending of around $30 billion.”

Applied also announced that Charlie Gay, president of Applied’s Solar division, has been elected to the National Academy of Engineering (NAE) for his contributions to the development of the global solar industry.

Worldwide silicon wafer revenues declined by 12% in 2012 compared to 2011 according to SEMI. Worldwide silicon wafer area shipments declined 0.1% in 2012 when compared to 2011 area shipments.

Pure, part of Imagination Technologies, has used Mentor Graphics’ technology and services to create its digital TV recorder 3D user interface.

Cadence announced the election of Young Sohn, president and chief strategy officer of Samsung Electronics, to its board of directors.

2013 has barely started, but various research firms already are making predictions for this year and next. For example, Semiconductor Intelligence has revised its 2013 chip forecast to 7.5% growth. The firm is holding its 2014 forecast at 12%. The firm also compares its predictions with other recent forecasts for 2013 and 2014.

Ten product categories, led by tablet MPUs and cell-phone application MPUs, are forecast to exceed the 6% growth rate forecast for the total IC market this year, according to IC Insights.

OEM spending on semiconductors for wireless applications is set to rise by 13.5% this year to reach a value of $69.6 billion, up from $62.3 billion in 2012, according to the IHS.

Revenue in 2013 for the worldwide outsourced manufacturing industry is forecast to reach $404.5 billion, up 4.5% from $387.0 billion last year, according to the IHS.

By Mark LaPedus

The recent Nano Job Fair in New York exceeded the 800 registrant capacity. Due to the overwhelming response, and the need to fill an additional 300 jobs, another job fair will be scheduled in the next few months. The fair itself filled more than 300 current and future openings at the CNSE, including positions with the Global 450mm Wafer Consortium (G450C).

China’s transition from a low-cost manufacturing hub to an innovation hotspot with growing foreign ambitions represents both a threat and an opportunity, according to Lux Research. Foreign acquisitions worth $28 billion are just the beginning of China’s global ambitions, according to the firm.

The Chinese IC market is forecast to have a 2012 to 2017 compound annual growth rate (CAGR) of 13%, five points higher than the 8% CAGR forecast for the total IC market during this same time period, according to IC Insights. By 2017, China is expected to represent 38% of the worldwide IC market, up from 23% in 2007, according to the firm.

Skyworks announced its results for the quarter. The company has also garnered some RF antenna tuning design wins, some of which are based on silicon-on-insulator (SOI) technology, said David Aldrich, president and CEO of the RF chip maker, on the Seeking Alpha Web site.

STMicroelectronics announced its results for the quarter. During a conference call, Carlo Bozotti, president and CEO of ST, said the company is developing ASICs for various applications using FD-SOI technology. ST also is looking at strategic options for ST-Ericsson, the cell-phone chip venture with Ericsson, he said. The venture recently rolled out a chip based on FD-SOI.

Following the announcement of STMicroelectronics’ intention to exit as a shareholder of ST-Ericsson, Ericsson is also exploring various strategic options for the venture.

Kilopass, a provider of semiconductor intellectual property (IP), will demonstrate its one-time programmable (OTP) memory IP on IBM’s 45nm, silicon-on-insulator (SOI) technology at the Common Platform Technology Forum. The event, which is on Feb. 5, will take place in Santa Clara, Calif.

Mentor Graphics announced the latest release of its HyperLynx product for superior high-speed design and analysis.

Chipmakers must explore, and embrace, new design methodologies to cut costs and boost cycle times. One way to bolster the design flow is to rethink the register-transfer level (RTL) synthesis process.

Applied Materials said that George Davis, executive vice president and chief financial officer, will depart the company effective March 8. The company expects to name a successor in the coming weeks. Davis will become CFO for Qualcomm.

SEMI and the U.S. Photovoltaic Manufacturing Consortium (PVMC) announced the signing of a memorandum of understanding (MOU) to enhance their cooperation in the areas of standards and roadmap activities for the solar thin film industry.

Renesas continues to cut costs. The company has sold its backend operations to J-Devices.

American Semiconductor has a process that transforms standard silicon wafers into flexible wafers. The technology is now available on TowerJazz’ CMOS foundry process.

Worldwide tablet shipments outpaced predictions, reaching a record total of 52.5 million units worldwide in the fourth quarter of 2012, according to IDC. Samsung is gaining ground on Apple, according to the firm.

VLSI Research says the IC industry will grow 10.1% in 2013. “We expect (the IC industry) to be an ASP-driven upturn,” according to the firm. “Even though the Chinese New Year is still weeks away, chipmakers are becoming more optimistic about 2013. This is driven in part by a modest improvement that is taking place at the macro level. The visibility for the U.S. economy has improved considerably. China’s macro data has also been positive and the European debt crisis appears to be fading.”

Chip inventory held by semiconductor suppliers reached alarmingly high levels in the third quarter of 2012 amid weak market conditions, according to IHS iSuppli.

By Mark LaPedus
The first wave of 2.5D chips using silicon interposers are trickling out in the marketplace.
FPGA vendor Xilinx was the first chipmaker to ship a 2.5D device, and Altera, Cisco, Huawei and IBM recently have talked about their respective 2.5D chip developments.

Generally, Altera and Xilinx have taken a somewhat identical and straightforward approach. The two companies are separately developing 2.5D FPGAs, initially based more on homogenous devices. Both are also using Taiwan Semiconductor Manufacturing Co. Ltd.’s turnkey solution to integrate all or part of their 2.5D FPGAs.

Huawei is taking a different avenue, which is arguably more representative of the complex approach that many may take in their 2.5D efforts. The Chinese networking equipment giant is developing a heterogeneous 2.5D device that combines an FPGA from Altera and stacked DRAM from Tezzaron. The interposer comes from Singapore’s Institute of Microelectronics (IME). And fabless ASIC vendor eSilicon is handling the supply chain and integration process.

Putting the pieces together is expected to be a herculean effort. But having explored a multitude of options, Huawei decided to move down an arduous path—and for good reason. “The memory wall is a very serious problem,” said Anwar Mohammed, a senior staff scientist at Huawei. “The gap is becoming wider and wider. And all of the solutions we have for solving the problem are not working anymore.”

For the high-end networking space, Huawei sees a clear but challenging path to solve the problem. “We have to punch a tunnel through the memory wall,” Mohammed said. “For networking applications, 2.5D is the preferred solution.”

The roadblocks
The memory bottleneck and resistivity problems in planar devices have fueled the development of stacked 2.5D and 3D chips using through-silicon vias (TSVs), whether those TSVs run through a die or a separate interposer die in 2.5D designs.

Mike Splinter, chairman and chief executive of Applied Materials, said the 2.5D/3D chip market represents a promising segment for the IC industry, but the business will take some time before it reaches mass production. “We’ve always said there will be a slow deployment of 2.5D,” Splinter said.

The 2.5D chip market is progressing somewhat faster than 3D. Several foundries and IC-packaging houses currently provide interposers and workable manufacturing flows to enable 2.5D designs. There are still some gaps in the technology, however.

“2.5D depends on having a stacked memory solution,” said E. Jan Vardaman, president of TechSearch International, a research firm. “The inability to obtain a memory stack is a gating factor. Some people also say the cost for 2.5D is too expensive.”

Test is also an important but sometimes overlooked part of the flow. “The test challenges for 2.5D are very similar to 3D. For die stacking, it is crucial to have each die pre-tested for KGD,” said Bassilios Petrakis, product marketing director at Cadence Design Systems.

“In the case of the interposer, the question often comes up as to whether it needs to be tested for connectivity upfront prior to bonding with other dies. There is also consideration for how to test partially populated interposers as well as multiple die stacks,” Petrakis said. “An example of that would be a logic die that talks to a Wide I/O DRAM and another logic die on top. If the bottom die of the interposer is the most expensive die, you may only want to attach it to an interposer with all other die attached that have been tested good so far. This may be the most economical way to produce good modules. Finally, all dies on interposers must have some form of a wrapper with boundary scan. We prefer the use of IEEE 1500-style wrappers, but we are also able to accommodate the simpler Wide I/O style boundary scan. Special I/O wrap test before die stacking/bounding can detect possible TSV shorts but not opens.”

Another challenge is to find a suitable manufacturing partner. In general, there are two schools of thought—turnkey versus a hybrid approach. TSMC and Samsung provide a turnkey solution, in which the companies provide both the front- and back-end work. In contrast, GlobalFoundries and UMC are sticking with their hybrid approaches. In that model, the foundries handle the front-end steps, but pass on the back-end work to the IC packaging houses.

Both approaches have their advantages and disadvantages. In the turnkey approach, the foundry can assume the responsibility of the supply chain, thereby keeping costs and quality under strict control. The problem with the turnkey method is that some customers are nervous about handing over their sensitive front-end, assembly and test intellectual-property (IP) to a foundry, said Ajit Manocha, chief executive of GlobalFoundries. “We are not a closed fab,” Manocha said. “Customers prefer to take their proprietary information to the OSATS. We are not going to force customers to do the assembly with us.”

Taking the right path
As it turns out, each customer will choose its own path. To simplify its respective supply chains, Altera and Xilinx are working with a limited set of partners. Most others may end up dealing with a more complex supply chain.

Huawei, for example, is working with separate chipmakers, interposer suppliers, foundries, assembly houses and integrators. At present, Huawei is developing its 2.5D ASIC/FPGA device at IME, a Singapore R&D organization. IME has set up a complete front-end production flow using fab gear from Applied Materials. IME also developed its own interposer technology. IME is a research institute of the Science and Engineering Research Council of the Agency for Science, Technology and Research (A*STAR).

Huawei declined to comment on which foundry it will use once it moves into production, but the challenges are obvious. “This could be a logistics nightmare,” said Ron Leckie, president of Infrastructure Advisors, a consulting firm.

Unfazed by the challenges, Huawei believes it must move in a new and radical direction to address the memory bottleneck in the network. “At one time, when you went to a new node, your gains were pretty sharp,” said Huawei’s Mohammed. “Now, every time we go to the next node, the power becomes a challenge and you have to go with larger and larger die sizes.”

The current line of specialized networking memory chips and other components are unable to keep pace. “Commodity memory cannot handle it,” he said. “Serdes was able to help with the bandwidth at one time. But now, the gains are flatter.”

To solve the problem, the company evaluated several options. “A company like Huawei doesn’t jump into a technology. We have to go through many doors before we decide this is a technology we go after,” he said.

Last year, for example, Huawei looked at combining an ASIC and RLDRAMs in a 64mm x 64mm package, he said. After dropping that idea, the company looked at integrating those devices in larger substrates or smaller packages. Those options were scrapped. Then, it looked at combining a bare die FPGA and packaged memory in a $25 module. “It was not leading-edge technology,” he said. “Any one of our competitors could have picked it up.”

Finally, the company decided on 2.5D. 3D is more suited for mobile applications. “The size of our line cards is constant. We want to put more and more items on the line card to make it more functional and effective. 2.5D is a very powerful enabler for that,” he said. “Initially, this is going to be more expensive. But if you combined enough items, there is a strong potential for cost reduction. It also allows us a faster time to market.”

In Huawei’s proposed design, the FPGA from Altera and the memory stack from Tezzaron are situated on a silicon interposer. “Instead of 10 or 20 DDR DRAMs, all of this can be replaced by one Wide IO memory,” he said. “DDR memory performance is so slow. All of this goes away with Wide IO memory, which is only 12mm x 12mm.”

In total, the company’s proposed 2.5D device occupies less space. The bandwidth per watt is at least 30 times better than conventional approaches, he said.

To realize its design, the world’s largest networking equipment company must overcome some major hurdles, namely the KGD issues, the lack of EDA tools and the supply chain. “Hopefully, we can obtain known good dies and bare dies,” he said. “There is good work going on at Cadence, Mentor and others, but this is still an area of concern. There are also some business concerns like who’s responsible and who’s not responsible?”

Ultimately, to make 2.5D/3D a viable solution in the overall market, Huawei advocates another critical piece to the puzzle–collaboration. “We are advocating pre-competitive collaboration. Let’s makes sure the technology succeeds. When the technology can take care of itself, let’s start competing,” he added.

By Mark LaPedus
In the mid-1990s, IBM announced the world’s first devices using a copper dual damascene process. At the time, the dual damascene manufacturing process was hailed as a major breakthrough. The new copper process enabled IC makers to scale the tiny interconnects in a device, as the previous material, aluminum, faced some major limitations.

Dual damascene remains the workhorse process flow in the fab since its fabled introduction. But more recently, there are questions regarding the extendibility of the trusty dual damascene flow as the IC industry moves towards the 14nm node and beyond.

It all boils down to the interconnect. Copper interconnects—the tiny wiring schemes in devices—are becoming more compact at each node, causing an alarming increase in the resistance-capacitance (RC) delay. “The interconnect scaling roadmap looks like a looming disaster,” said Rob Aitken, an ARM fellow. “We want the materials to save us.”

The problem is that the dual damascene flow may extend to 10nm—and then could promptly run out of steam, according to some experts. Then, at 7nm, the industry may need to switch gears and move to a new flow—the single damascene process.

At 5nm, chip makers may need to switch again and re-visit the subtractive reactive ion etch (RIE) process for copper. Ironically, the industry explored the development of subtractive copper etch a decade ago, but the technology never got off the ground and was shelved.

Still others believe the risk-averse industry would rather extend the current technology as long as possible before moving to a new process. “I think dual damascene will extend to 10nm and probably the 7nm node,” said Daniel Edelstein, a fellow and manager of BEOL technology strategy at IBM. Edelstein was also the original project leader for IBM’s groundbreaking dual damascene efforts in the 1990s.

“I regard single damascene as a backup, not a front-up roadmap point,” he said. “Copper RIE is just one component of a subtractively etched multilevel copper wire and via integration, which I think is unworkable for copper.”

Beyond 7nm, the industry is looking at dual damascene, single damascene and copper RIE. In parallel, the industry is taking a different approach to the RC problem by working on stacked 2.5D and 3D chips. And for the distant future, the industry is looking at new transistor schemes, photonics and other technologies.

The looming crisis
For years, the industry has been grappling with a crisis in the interconnect. The industry averted a disaster in 1997, when IBM rolled out its CMOS 7S process, a 0.22-micron technology using the industry’s first dual damascene flow.

Until then, leading-edge logic devices deployed aluminum interconnects using an aluminum subtractive etch process. But as the industry moved towards 0.25-micron geometries and beyond, aluminum was unable to withstand the higher current densities in logic. And copper was (and still is) about 40% less resistive than aluminum, and it is less vulnerable to electromigration.

More recently, DRAM makers have made the transition from aluminum to copper. The shift towards copper requires a dual damascene process, which takes place at the back-end-of-the-line (BEOL) in the manufacturing flow. The process enables the formation of two main parts of the interconnect: metallization and low-k dielectrics.

In the dual damascene process, a structure undergoes a diffusion barrier etch step. Then, a via dielectric is deposited. An etch step then forms a gap, where the lines and vias are formed.

Then, a thin layer of barrier of tantalum (Ta) and tantalum nitride (TaN) materials are deposited using physical vapor deposition (PVD). Ta is used to form the liner and TaN is for the barrier in a structure. The barrier layer is coated over by a copper seed barrier via PVD. And finally, the structure is electroplated with copper and ground flat using chemical mechanical polishing (CMP).

In the single damascene process, the trenches and vias are formed one step at a time. In contrast, they are formed simultaneously in dual damascene. Fewer steps make dual damascene a less expensive approach. And in a completely different flow, the copper subtractive process makes use of RIE tools.

Dual damascene, meanwhile, continues to extend and evolve. PVD, the workhorse tool technology for the metallization process in dual damascene, may extend to at least 10nm. But if PVD should stumble, the industry is evaluating rival tool technologies like chemical-vapor deposition (CVD) and atomic-layer deposition (ALD).

In the low-k part of the equation, however, the technology remains stuck. “The RC delay is increasing,” said Dean Freeman, an analyst with Gartner. “To improve the RC delay, you need lower k materials. But to get lower k, you need to add more porosity or air to the dielectric material. That compromises the structural integrity of the dielectric. It also makes it more difficult to keep the copper from diffusing into the dielectric and causing shorts, or leakage between metal lines.”

There are also challenges in the metallization process. “The resistance of the copper is also increasing. As you get smaller and smaller vias and lines, you get smaller and smaller grains. A smaller grain/crystal means that you have more electron scatter, which increases the resistance and the heat in the device. This is why the device manufacturers are trying to keep the metal lines as wide as possible where they can,” Freeman said.

At 14nm, in fact, the interconnect is headed toward an “inflection point,” in which copper resistivity increases exponentially, said Mehul Naik, a distinguished member of the technical staff at Applied Materials.

“The question is how long you can extend copper damascene,” Naik said. “From a resistive perspective, how can you get more and more copper inside the trenches and how can you design your materials so you get rid of scattering issues that increase the copper resistivity. It’s maximizing the volume and minimizing the scattering of copper. If we can achieve that, we can extend damascene as far as possible. But that goes back into how you pattern the copper and get the fine pitch, and what kinds of issues you run into when you get a fine pitch.”

If dual damascene runs out of steam, the industry is looking at single damascene technology and subtractive copper etch. In theory, the single damascene approach could potentially enable smaller gaps with higher aspect ratios, but it is more expensive, Naik said.

Unlike single damascene, which may use existing tool technologies and materials, the industry may need to start from scratch in subtractive copper etch. “There are no tools (in the market),” he said. “So, you would need to develop a copper etch process.”

What’s next?
Looking into his crystal ball, IBM’s Edelstein sees dual damascene extending to at least 7nm and predicts a cloudy future for copper RIE. “Single damascene would be the backup with penalties if dual damascene breaks irreparably,” he said.

“Copper RIE discussions always seem to neglect the classic copper integration problems that would come with it.  These problems were circumvented by going to damascene in the first place,” he said. “Why would bringing those unsolved problems back be any easier at vastly smaller dimensions? How would you propose to make a viable subtractive-etched multilevel copper BEOL line/via integration at competitive pitches, with all the needs for copper passivation, via contact, electrical and corrosion insulation, while at the same time retaining competitive cost, performance and reliability?”

Beyond 7nm, there are new and conventional approaches on the table. Even before 7nm, the industry is developing 2.5D/3D stacked chips to circumvent the RC delay problem. But advanced chip stacking has a number of challenges and is still a few years away from mass production

There are other and more futuristic technologies in R&D, many of which are exotic and expensive. The candidates include carbon nanotubes contacts, graphene, photonics, network-on-a-chip architectures, smart interconnects and others, said Jon Candelaria director of interconnect and packaging sciences at the Semiconductor Research Corp. (SRC).

For example, using a single damascene process, IMEC, TEL and others recently described 150nm diameter contacts filled with carbon nanotubes and a copper top metal. Carbon nanotubes before metallization reduced the single contact hole resistance from 4.8 kΩ down to 2.8 kΩ.

In a separate effort, Japan’s AIST recently fabricated multi-layer graphene interconnects directly on silicon dioxide by annealing sputtered amorphous carbon with a cobalt catalyst layer. A resistivity of around 500 μΩcm was obtained after cobalt removal.

And for years, the industry has been talking about the use of optical interconnects. “The bottom line is that the RC delay is increasing and there are no great solutions on the horizon other than copper and low-k,” said Gartner’s Freeman. “Ideally, the industry would like to go to a material with lower resistance, such as gold or carbon nanotubes for the interconnect. Unfortunately, gold is a bit too expensive and does not provide significant improvement over copper.”

Graphene is also expensive and involves some tough integration problems. “While nanotubes have demonstrated great promise, they have high resistance where they make contact to the metal lines. But IMEC has suggested that we are further along than people think on this topic,” Freeman said. “Optical interconnects are still a ways out. The big issue here is creating the laser and the collector in silicon, or on silicon. Intel continues to research this and I think they are getting close on chip-to-chip, but we are still a ways away from the technology.”

By Mark LaPedus
Boeing should have chosen a safer type of lithium-ion battery chemistry for its new 787, according to Lux Research. At present, Boeing uses high-energy technology from GS Yuasa that suffers from thermal runaway. It should switch to an alternate type of lithium-ion battery, says the analyst firm.

At this week’s SEMI Industry Strategy Symposium (ISS), Samsung disclosed plans that it will offer 2.5D/3D foundry services. Like TSMC, Samsung will provide a turnkey solution, meaning it will offer the front- and back-end work for customers. “To start with, we will do it all in-house,” said Ana Hunter, vice president of foundry services at Samsung Semiconductor. “If everything comes from the same company, it’s going to save cost (and ensure quality).”

Also at ISS, Intel demonstrated the world’s first patterned 450mm wafer. The wafer was supplied by Sumco and the patterning was conducted on a nano-imprint tool from Molecular Imprints, said Robert Bruck, vice president of the Technology and Manufacturing Group at Intel. Now, the goal is to get “a thousand” wafers out to the equipment companies for 450mm development, he said.

Separately, Intel posted mixed results in the quarter. The chipmaker also issued guidance “for $13 billion in CapEx for 2013 as a meaningful surprise. Now, this includes $2 billion for 450mm development,” said C.J. Muse, an analyst at Barclays. The 450mm CapEx figure is non-equipment related. So, Intel’s real CapEx is $11 billion, flat from 2012 he said.

GlobalFoundries’ recent decision to build a new R&D center will accelerate its efforts to bring technologies from the lab to the fab, according to Ajit Manocha, chief executive of the company, at ISS.

The semiconductor industry is undergoing massive transformation, according to industry leaders speaking at ISS.

At ISS, Bill McClean, president of IC Insights, provided his forecast. The IC market is expected to grow 6% in 2013, following a 2% decline in 2012, he said. CapEx is expected to fall 10% in 2013, following another 10% drop last year, he said.

The Semiconductor Research Corp. (SRC) and the Defense Advanced Research Projects Agency (DARPA) announced that $194 million will be dedicated during the next five years to six university microelectronics research centers to support the continued growth of the U.S. semiconductor industry. The program, dubbed the Semiconductor Technology Advanced Research network (STARnet), includes several industry partners: Applied Materials, GlobalFoundries, IBM, Intel, Micron, Raytheon, Texas Instruments and United Technologies.

Applied Materials has been honored with the 2013 IEEE Corporate Innovation Recognition award for its contributions to PECVD technology for flat panel display manufacturing.

GlobalFoundries announced Alexie Lee, general counsel and executive vice president of legal and corporate affairs, was recognized by The Manufacturing Institute, Deloitte, University of Phoenix, and the Society of Manufacturing Engineers with a Women in Manufacturing STEP (Science, Technology, Engineering and Production) Award.

Troubled Japanese chip maker Renesas continues to restructure. As part of the moves, the company will consolidate more design units and fabs.

Micron Technology has entered into agreements with Nanya to amend their Taiwan DRAM joint venture involving Inotera Memories. Micron is transitioning to purchase all of Inotera’s manufacturing output. Under the prior agreements, Nanya and Micron were obligated to purchase half of Inotera’s output.

Intel’s recent introduction of a new Atom processor platform is designed to target the fast-growing market for low-end smartphones in emerging economies. It represents a shrewd strategy that could allow the company to expand its currently minimal market share in the industry, according to IHS iSuppli.

Worldwide revenues for microprocessors designed for mobile PCs, desktop PCs, and PC servers will grow a mere 1.6% to $40.7 billion in 2013, according to IDC.

By Mark LaPedus
Lux Research has released its top 10 emerging companies in 2012. It features leaders in bio-based materials, 3D-printing, photovoltaics, drug delivery, energy efficiency and a fabless chip maker.

Soitec announced the grand opening of its North American solar manufacturing facility in San Diego. The concentrator photovoltaic (CPV) modules produced in San Diego will support hundreds of MWp of contracts for utility-scale projects in California.

IHS has released its top 10 predictions for the solar industry in 2013. Here’s one prediction: Many integrated players, particularly those based in China, will fold up shop in 2013.

Ericsson will take a non-cash charge related to its 50% stake in ST-Ericsson. Ericsson continues to believe that the modem technology has a strategic value for the wireless industry. ST-Ericsson is working on a technology based on SOI. Ericsson will continue to explore various strategic options for the future of ST-Ericsson assets. To acquire the full majority of ST-Ericsson is, however, not an option.

In a blog, Gold Standard Simulations has offered some advice to the SOI community: Metal-gate-first FD-SOI is good but gate-last could be spectacular.

Strain technology has been a key enabler for improving transistor performance. But there is a question whether stressors will maintain their effectiveness in IC scaling. Also which stressors will be most effective as the industry moves from planar to finFETs? According to a paper from Applied Materials and Synopsys at IEDM, the answer is clear: “S/D epitaxy remains an effective source of strain engineering for both aggressively and conservatively scaled finFETs. Not merging the S/D epitaxy between adjacent fins and recess etch into the fin before S/D epitaxy is recommended for maximizing the gain. With high active P concentration Si:C becomes an effective stressor for NMOS. Contact and gate metal fills provide new knobs for engineering strain in finFET devices for the 22nm node and remain effective with conservative scaling of contact/gate CD only.”

Worldwide wafer fab equipment (WFE) spending is forecast to total $27 billion in 2013, a 9.7% decline from 2012, according to Gartner. In 2012, WFE spending is on pace to reach $29.9 billion, a decrease of 17.4% from 2011 spending. The market is projected to return to growth in 2014.

North America-based manufacturers of semiconductor equipment posted a book-to-bill ratio of 0.79 in November, according to SEMI. This compares to a ratio of 0.75 in October.

Hewlett-Packard’s Inkjet and Printing Solutions division has reaffirmed its use of Mentor Graphics’ Pyxis Custom IC Design Platform as HP’s standard solution for custom IC design and verification. In addition, HP has selected Mentor’s Questa CDC as its standard solution for clock-domain crossing (CDC) verification.

Mentor announced comprehensive design, manufacturing, and post tapeout enabling support for Samsung’s 14nm IC manufacturing processes. In addition, Mentor announced advances in its T3Ster+TeraLED measurement and characterization hardware.

Ultratech has acquired the assets of Cambridge Nanotech. Based in Cambridge, Mass., Cambridge is a supplier of atomic layer deposition (ALD) systems.

ASML Holding and Cymer provided a status update regarding ASML’s previously announced pending acquisition of all of the outstanding shares of Cymer. ASML is responding to a request for additional information from the Antitrust Division of the U.S. Department of Justice regarding the transaction. This second request is part of the regulatory review process under the Hart-Scott-Rodino Antitrust Improvements Act of 1976. ASML and Cymer continue to anticipate completion of the transaction in the first half of 2013.

In a rare move, the Federal Trade Commission (FTC) is blocking a semiconductor acquisition. The FTC issued an administrative complaint seeking to stop Integrated Device Technology’s proposed $330 million acquisition of PLX Technology. The deal allegedly would give the combined firm a near-monopoly in the market for a type of integrated computer circuits called PCIe switches. In response, IDT and PLX have mutually agreed to terminate their merger agreement.

Micron posted a loss. “Unit shipments in both segments were impacted by unspecified manufacturing issues, although we do not believe these related to yields and more about execution on the back-end. Without these issues, we believe Micro would have beat consensus forecasts,” said Hans Mosesmann, an analyst with Raymond James. “Management provided a brief update on the Elpida acquisition, reiterating its expectation for the close sometime in 1H 2013. We also see positive strategic merits from the deal, including a significant addition to the company’s mobile DRAM portfolio (mobile DRAM share goes from ~4% to ~21%), with Elpida having a supply agreement with Apple.”

For the first time in 14 years, Nokia will not sit atop the global cellphone business on an annual basis at the end of 2012. Samsung is set to seize the mobile handset market’s top rank, according to IHS iSuppli.

Driven by continued demand for smartphones, tablet PCs, and other personal media devices, the total flash memory market (NAND and NOR) is forecast to grow 2% to $30.4 billion in 2012, surpassing the $28.0 billion DRAM market in sales for the first time, according to IC Insights.

IMS Research recently released its fourth annual video surveillance trends for the year ahead. Here’s one trend: The increased popularity of HD and megapixel resolution security cameras has been a hot topic in the video surveillance industry.

VLSI Research is raising its 2013 IC forecast to a +10% jump. “We are much more bullish and expect this to be an ASP-driven upturn due to the constraints in the capacity that the industry will face next year, especially in the memory market. As a result, we project IC units to increase 7% and ASPs to rise 3%. We’re seeing plenty of positive ‘Christmas black-hole’ indicators that the first half will be much hotter than thought before Thanksgiving.”

The semi equipment market has been downgraded to -16% in 4Q ’12, according to VLSI. The fab tool market in 2012 is expected to be minus 12.5%. 2013 is unchanged at -5.3%.

By Mark LaPedus
Apple apparently is switching foundry vendors from Samsung to TSMC. Still, Samsung is moving forward with its U.S. fab plans. The company announced that a $4 billion fab investment at its Austin, Texas, site is on schedule for production of mobile application processors within the second half of 2013. The remodeled fab line will produce mobile application processors on 300mm wafers at the 28nm node. C.J. Muse, an analyst with Barclays, said Samsung will cut its capex by 50% in 2012 over 2011. “The actual range is likely to be down 30%-50% year-over-year, with a bigger cut on the logic side (due to the likely loss of the Apple business) and a more muted cut on the memory side.”

In a decision that will support nearly 10,000 high-tech jobs, the Export-Import Bank of the United States (Ex-Im Bank) has approved a $1.03 billion loan to GlobalFoundries to finance the export of American-made semiconductor manufacturing equipment to Germany. Applied Materials is one of the exporters involved in the transaction. “The ability of our customer GlobalFoundries to access this financing benefits Applied Materials’ manufacturing and R&D in the United States, as well as our supply chain, at a time of tremendous global competition for high-tech jobs,” said Mike Splinter, chairman and CEO of Applied, in a statement.

GlobalFoundries has added a 10nm finFET process to its roadmap and expanded its technology platform offerings. The foundry vendor plans to go from 20nm planar in 2013, to 14nm finFET in 2014, to 10nm finFET in 2015, and 7nm finFET in 2017.

At the SOI Consortium’s event at IEDM, Jeff Watt, a fellow at Altera, presented an evaluation and benchmark of planar fully depleted SOI technology. A simulation showed that 20nm FD-SOI provided a 5X reduction in power over 28nm bulk, Watt said. However, Altera has not made a commitment to SOI for FPGAs and is currently evaluating the technology, he said. “We are looking at all options,” he said. For 20nm, Altera plans to use a bulk technology at TSMC. At 14nm, the FPGA house will likely go with bulk finFETs at TSMC. However, Altera is also exploring SOI.

STMicroelectronics unveiled the results of its 28nm production silicon chips using FD-SOI technology, which it claims offers a 30% improvement in speed over bulk CMOS while using less power.

STMicroelectronics took another step towards the availability of its 28nm FD-SOI technology platform. The technology is now open for pre-production from its Crolles 300mm manufacturing facility.

SEMI praised Congressional leadership as the U.S. Senate passed legislation (92-4 vote) to normalize trade relations with Russia. This allows American companies to receive the full benefits of Russia’s recent accession to the World Trade Organization (WTO) by wavering an outdated, Cold War-era amendment that restricted trade.

SEMI reported that worldwide semiconductor manufacturing equipment billings reached $9.06 billion in the third quarter of 2012. The billings figure is 12% lower than the second quarter of 2012 and 15% lower than the same quarter a year ago.

Mentor Graphics announced the new T3Ster DynTIM tester, a method of measuring thermal characteristics of thermal interface materials.

MIPS determined that a new proposal from CEVA to acquire the company constitutes a “superior proposal” to the merger agreement with Imagination Technologies. MIPS is prepared to continue negotiations with Imagination if it adjusts the terms of the merger agreement.

Rudolph Technologies has acquired Azores. The move will enable Rudolph to enter the back-end advanced packaging lithography market.

Test handler specialist Cohu has agreed to acquire Ismeca Semiconductor from Schweiter Technologies for $54.5 million, plus acquired cash, to be funded out of Cohu’s existing cash reserves.

Worldwide semiconductor revenue is projected to total $311 billion in 2013, a 4.5 percent increase from 2012 revenue, according to Gartner.

The solar industry is reeling from overcapacity and supply outstrips demand by two to one. It needs to drive costs lower in order to overcome diminished subsidies and regain profitability, according to Lux Research. Module prices have fallen precipitously over the past four years to a low of $0.70/W but the cost of goods sold (COGS) for modules has not reached this level, resulting in massive losses for most module manufacturers. Solar modules production costs could fall as low as $0.48/W in 2017, according to the firm.