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Blog review December 16, 2013

Monday, December 16th, 2013

Randhir Thakur of Applied Materials wishes the transistor a happy 66th birthday, noting that the transistor is truly one of the most amazing technological innovations of all time! He says it’s estimated that more than 1200 quintillion transistors will be manufactured in 2015, making the transistor the most ubiquitous man-made device on the planet.

Phil Garrou writes that 3DIC memory, and therefore all of 2.5/3D technology, took one step closer to full commercialization last week with the High Bandwidth Memory HBM joint development announcement from AMD and Hynix at the RTI 3D ASIP meeting in Burlingame CA.

Zhihong Liu, Executive Chairman of ProPlus Design Solutions is celebrating 20 years of BSIM3v3 SPICE models. He notes that with continuous geometry down-scaling in CMOS devices, compact models became more complicated as they needed to cover more physical effects, such as gate tunneling current, shallow trench isolation (STI) stress and well proximity effect (WPE).

Applied Materials and Tokyo Electron held a media roundtable in Japan to discuss the merger of equals announced on September 24, 2013. Tetsuro Higashi, Chairman, President and CEO of Tokyo Electron, who will become Chairman of the new company, and Mike Splinter, Executive Chairman of Applied Materials, who will serve as Vice-Chairman, addressed the audience of more than 20 members of the Japanese media. Kevin Winston blogs about the event.

Pete Singer is freshly back from the International Electron Devices Meeting (IEDM). “A dream for the device engineer could be a nightmare for a process integration engineer,” said Frederic Boeuf of ST Microelectronics in the opening talk. That seemed to be echoed throughout the conference, where the potential of new devices such as tunnel FETs or materials such as graphene were always tempered with a dose of reality that materials had to be deposited, patterned, annealed to create devices, and those devices had to be connected.

Solid State Watch: Nov. 8-14, 2013

Friday, November 15th, 2013
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Design for Yield Trends

Tuesday, November 12th, 2013

By Sara Ver-Bruggen

Should foundries establish and share best practices to manage sub-nanometer effects to improve yield and also manufacturability?

Team effort

Design for yield (DFY) has been referred to previously on this site as the gap between what the designers assume they need in order to guarantee a reliable design and what the manufacturer or foundry thinks they need from the designer to be able to manufacture the product in a reliable fashion. Achieving and managing this two-way flow of information becomes more challenging as devices in high volume manufacturing have 28 nm dimensions and the focus is on even smaller dimension next-generation technologies. So is the onus on the foundries to implement DFY and establish and share best practices and techniques to manage sub-nanometer effects to improve yield and also manufacturability?

Read more: Experts At The Table: Design For Yield Moves Closer to the Foundry/Manufacturing Side

‘Certainly it is in the vital interest of foundries to do what it takes to enable their customers to be successful,’ says Mentor Graphics’ Senior Marketing Director, Calibre Design Solutions, Michael Buehler, adding, ‘Since success requires addressing co-optimization issues during the design phase, they must reach out to all the ecosystem players that enable their customers.’

Mentor refers to the trend of DFY moving closer to the manufacturing/foundry side as ‘design-manufacturing co-optimization’, which entails improving the design both to achieve higher yield and to increase the performance of the devices that can be achieved for a given process.

But foundries can’t do it alone. ‘The electronic design automation (EDA) providers, especially ones that enable the critical customer-to-foundry interface, have a vital part in transferring knowledge and automating the co-optimization process,’ says Buehler. IP suppliers must also have a greater appreciation for and involvement in co-optimization issues so their IP will implement the needed design enhancements required to achieve successful manufacturing in the context of a full chip design.

As they own the framework of DFY solutions, foundries that will work effectively with both the fabless and the equipment vendors will benefit from getting more tailored DFY solutions that can lead to shorter time-to-yield, says Amiad Conley, Applied Materials’ Technical Marketing Manager, Process Diagnostics and Control. But according to Ya-Chieh Lai, Engineering Director, Silicon and Signoff Verification, at Cadence, the onus and responsibility is on the entire ecosystem to establish and share best practices and techniques. ‘We will only achieve advanced nodes through a partnership between foundries, EDA, and the design community,’ says Ya-Chieh.

But whereas foundries are still taking the lead when it comes to design for manufacturability (DFM), for DFY the designer is intimately involved so he is able to account for optimal trade-off in yield versus PPA that result in choices for specific design parameters, including transistor widths and lengths.

For DFM, foundries are driving design database adjustments required to make a particular design manufacturable with good yield. ‘DFM modifications to a design database often happen at the end of a designer’s task. DFM takes the “ideal” design database and manipulates it to account for the manufacturing process,’ explains Dr Bruce McGaughy, Chief Technology Officer and Senior Vice President of Engineering at ProPlus Design Solutions.

The design database that a designer delivers must have DFY considerations to be able to yield. ‘The practices and techniques used by different design teams based on heuristics related to their specific application are therefore less centralized. Foundries recommend DFY reference flows but these are only guidelines. DFY practices and techniques are often deeply ingrained within a design team and can be considered a core competence and, with time, a key requirement,’ says McGaughy.

In the spirit of collaboration

Ultimately, as the industry continues to progress requiring manufacturing solutions that increasingly tailored and more and more device specific, this requires earlier and deeper collaboration between equipment vendors and foundry customers in defining and developing the tailored solutions that will maximize the performance of equipment in the fab. ‘It will also potentially require more three-way collaboration between the designers from fabless companies, foundries, and equipment vendors with the appropriate IP protection,’ says Conley.

A collaborative and open approach between the designer and the foundry is critical and beneficial for many reasons. ‘Designers are under tight pressures schedule-wise and any new steps in the design flow will be under intense scrutiny. The advantages of any additional steps must be very clear in terms of the improvement in yield and manufacturability and these additional steps must be in a form that designers can act on,’ says Ya-Chieh. The recent trend towards putting DFM/DFY directly into the design flow is a good example of this. ‘Instead of purely a sign-off step, DFM/DFY is accounted for in the router during place and route. The router is able to find and fix hotspots during design and, critically, to account for DFM/DFY issues during timing closure,’ he says. Similarly, Ya-Chieh refers to DFM/DFY flows that are now in place for custom design and library analysis. ‘Cases of poor transistor matching due to DFM/DFY issues can be flagged along with corresponding fixing guidelines. In terms of library analysis, standard cells that exhibit too much variability can be systematically identified and the cost associated with using such a cell can be explicitly accounted for (or that cell removed entirely).’

‘The ability to do “design-manufacturing co-optimization” is dependent on the quality of information available and an effective feedback loop that involves all the stakeholders in the entire supply chain: design customers, IP suppliers, foundries, EDA suppliers, test vendors, and so on,’ says Buehler. ‘This starts with test chips built during process development, but it must continue through risk manufacturing, early adopter experiences and volume production ramping. This means sharing design data, process data, test failure diagnosis data and field failure data,’ he adds.

A pioneer of this type of collaboration was the Common Platform Consortium initiated by IBM. Over time, foundries have assumed more of the load for enabling and coordinating the ecosystem. ‘GLOBALFOUNDRIES has identified collaboration as a key factor in its overall success since its inception and been particularly open about sharing foundry process data,’ says Buehler.

TSMC has also been a leader in establishing a well-defined program among ecosystem players, starting with the design tool reference flows it established over a decade ago. Through its Open Innovation Platform program TSMC is helping to drive compatibility among design tools and provides interfaces from its core analysis engines and third party EDA providers.

In terms of standards Si2 organizes industry stakeholders to drive adoption of collaborative technology for silicon design integration and improved IC design capability. Buehler adds: ‘Si2 working groups define and ratify standards related to design rule definitions, DFM specifications, design database facilities and process design kits.’

Open and trusting collaboration helps understand the thriving ecosystem programs that top-tier foundries have put together. McGaughy says: ‘Foundry customers, EDA and IP partners closely align during early process development and integration of tools into workable flows. One clear example is the rollout of a new process technology. From early in the process lifecycle, foundries release 0.x versions of their PDK. Customers and partners expend significant amounts of time, effort and resources to ensure the design ecosystem is ready when the process is, so that design tapeouts can start as soon as possible.’

DFY is even more critically involved in this ramp-up phase, as only when there is confidence in hitting yield targets will a process volume ramp follow. ‘As DFY directly ties into the foundation SPICE models, every new update in PDK means a new characterization or validation step. Only a close and sustained relationship can make the development and release of DFY methodologies a success,’ he states.

Experts At The Table: Design For Yield (DFY) moves closer to the foundry/manufacturing side

Friday, November 8th, 2013

By Sara Verbruggen

SemiMD discussed the trend for design for yield (DFY) moving closer to the foundry/manufacturing side with Dr Bruce McGaughy, Chief Technology Officer and Senior Vice President of Engineering, ProPlus Design Solutions, Ya-Chieh Lai, Engineering Director, Silicon and Signoff Verification, Cadence and Michael Buehler, Senior Marketing Director, Calibre Design Solutions, Mentor Graphics, and Amiad Conley, Technical Marketing Manager, Process Diagnostics and Control, Applied Materials. What follows are excerpts of that conversation.

SemiMD: What are the main advantages for design for yield (DFY) moving closer to the manufacturing/foundry side, and is it a trend with further potential?

Forte: Mentor refers to this trend as ‘design-manufacturing co-optimization’ because in the best scenario it involves improving the design both to achieve higher yield and to increase the performance of the devices that can be achieved for a given process. Companies embrace this opportunity in different ways. At one end of the scale, some fabless IC companies do the minimum they have to do to pass the foundry sign-off requirements. However, some companies embrace co-optimization as a way to compete, both by decreasing their manufacturing cost (higher yield means lower wafer costs), and by increasing the performance of their products at a given process node compared to their competition. Having a strong DFY discipline also enables fabless companies to have more portability across foundries, giving them alternate sources and purchasing power.

Ya-Chieh: Broadly speaking there are three typical insertion points for design for manufacturability (DFM)/DFY techniques. The first is in the design flow as design is being done. The second is as part of design sign-off. The last is done by the foundry as part of chip finishing.

The obvious advantage of DFY/DFM moving closer to the manufacturing/foundry side is in terms of ‘access’ to real fab data. This information is closely guarded by the fab and access is still only in terms of either encrypted data or models that closely correlate to silicon data but that have been carefully scrubbed of too many details.

However, the complexity of modern designs requires that DFM/DFY techniques need to be as far upstream in the design flows as possible/practicable. Any DFM/DFY technique that requires a modification to the design must be comprehended by designers so that any design impact can be properly accounted for so as to prevent the possibility of design re-spins late in the design cycle.

What we are seeing is not that DFM/DFY is moving closer to the manufacturing, or foundry, side, but that different techniques have been needed over the years to address the need of the designer for information as early as possible. Initially much of DFM/DFY was in the form of complex rule-based extensions to DRC, but much of this has since moved to include model-based and, in many cases, pattern-based checks (or some combination thereof).  More recently, the trend has been towards deeper integration with design tools and more automated fixing or optimization. DFM/DFY techniques that merely highlight a “hotspot” is insufficient. Designers need to know how to fix the problem and in the event there is a large number of fixes designers need to know how to automatically fix the problem. In other words the trend is about progressing towards better techniques for providing this information upstream and in ways that can be actionable by designers.

Conley: The key benefit in DFY approach is the ability to provide tailored solutions to the relevant manufacturing steps in a way that optimize performance based on device specific characteristics. This trend will definitely evolve further. We definitely see the trend in the defect inspection and review loops in foundries, which are targeted to generate paretos of the representative killer defects at major process steps. Due to the defects becoming smaller and the optical limitation of the detection tools, design information is used today to enable smarter sampling and defect classification in the foundries. To accelerate yield ramp going forward, robust infrastructure development is needed as an enabler to extract relevant information from chip design to the defect inspection, defect review and metrology equipment.

McGaughy: The foundation information used by designers in DFY analysis comes from the fab/foundry. This information is encapsulated in the form of statistical device models provided to the design community as part of the process design kit (PDK). Statistical models and, more recently, layout-dependent effect information is used by designers to determine the margin their design has for a particular process. This allows the designers to optimize their design to achieve the desired yield versus power, performance, area (PPA) trade-off. Without visibility into process variability via the foundry-provided Simulation Program with Integrated Circuit Emphasis (SPICE) models, DFY would not be viable. Hence, foundries are clearly at the epicenter of DFY. As process complexity increases and more detailed information of process variation effects are captured into SPICE models and made available to designers, it can be expected that the role of the foundry will continue to be more important in this respect over time.

SemiMD: So does this place a challenge on the EDA industry, or, how are EDA companies, such as ProPlus, helping to enable this trend?

McGaughy: The DFY challenge that designers face creates an opportunity for the EDA industry. As process complexity increases, there is less ‘margin’. Tighter physical geometries, lower single supply voltage (Vdd) and threshold voltage (Vth), new device structures, new process techniques and more complex designs all push margins. Margins refer to the slack that designers may have to ensure they can create a robust design. That not only works at nominal conditions, but under real-world variability.

Tighter margins mean a greater need to carefully asses the yield versus PPA trade-off that creates the need for DFY tools. This is where companies such as ProPlus come in. ProPlus helps designers use the foundry-provided process variation information effectively and designers can validate and even customize foundry models for specific application needs with the industry’s de-facto golden modeling tool from ProPlus.

SemiMD: Is this trend for DFY moving closer to the foundry/manufacturing side the only way to improve yields, as the industry continues to push towards further scaling, and all of the challenges that this entails?

Ya-Chieh: Actually we believe the trend is actually towards tighter integration with design, not less!

Conley: DFY solutions alone are not sufficient and they need to be developed in conjunction with wafer fabrication equipment enhancements. Looking at the wafer inspection and review (I&R) segment, the need to detect smaller defects and effectively separate yield killer defects from false and nuisance defects leads to an increased usage of SEM-based defect inspection tools that have higher sensitivity. At Applied Materials, we are very focused on improving core capabilities in imaging and classification. In our other technology segments there are also a lot of innovations on deposition and removal chamber architecture and process technologies that are focused on yield improvement. DPY schemes, as well as advancement in wafer fabrication equipment, are needed to improve yields as the industry advances scaling.

Forte: Strategies aside, the fact is that beyond about 40nm, IC designs must be optimized for the target manufacturing process. At each progressive node, the design rules become more complex and the yield becomes more specific to an individual design. For example, layouts now have to be checked to make sure they do not contain specific patterns that cannot be accurately fabricated by the process. This is mainly due to the fact that we are imaging features that are much smaller than the wavelength of the light currently used in production steppers. But there are many other complexities at advanced nodes associated with etch characteristics, via structures, fill patterns, electrical checks, chemical-mechanical polishing, double patterning, FinFET transistor nuances, and many others.

These issues are too numerous and too complex to deal with after tapeout. The foundries simply cannot remove all yield limiters by adjusting their process. For one thing, some of the issues are simply beyond the control of the process engineers. For example some layout patterns simply cannot be imaged by state-of-the-art steppers, so they must be eliminated from the design. Another problem, or challenge, is that foundries need to run designs from many customers. In most cases, very large consumer designs aside, foundries cannot afford to optimize their process flow for one customer’s design. Bottom line, design-manufacturing co-optimization issues must be taken into consideration during the physical design process.

McGaughy: More and more yield is a shared responsibility. At older nodes when defect density limits were responsible for optimal yields, the foundries took on most of the responsibility. At deep nanometer nodes, this is no longer the case. Now, the design yield must be optimized via trade-offs. Foundries are pushed to provide ever better performance at each new node and this means that they too have less process margin. Rather than guard band for process variation, foundries now provide the designer with detailed visibility into how the process variation will behave. Designers in turn can now make the choices they need to make, such as whether they need performance to be competitive or how best to achieve optimal performance with lowest yield risk. This shared responsibility for yield has pushed the DFY trend to the forefront. It serves to bridge the gap between design and manufacturing and will continue to do so as process technology scales.

Applied Materials rolls out new CVD and PVD systems for IGZO-based displays

Thursday, October 17th, 2013

By Pete Singer, Editor-in-Chief, Solid State Technology

Applied Materials introduced three new tools for the display market aimed at metal oxide thin film transistors. The tools, one of which is CVD and the other two PVD, employ new hardware designs and process technology that enable better film uniformity with fewer defects, and are designed for use with next generation IGZO-based thin film transistors (TFTs). The display industry is quickly switching to metal oxide TFTs and IGZO (indium gallium zinc oxide) is the material of choice.

Higher resolution LCD displays, greater than 300 dpi, require a switch from amorphous silicon designs to either metal oxide transistors or low-temperature polysilicon (LTPS), which offer higher-mobility in a smaller area (Figure 1). They also operate at lower power levels, which is important in mobile devices. Another problem with larger transistors is that they block too much of the light in the display.

LG has already begun shipping 55-inch OLED TVs using metal oxide backplanes and by 2014, all major LCD and LED display makers will have begun the switch over to metal oxide TFTs.

The advantage of metal oxide transistors over LTPS transistors is that they consume less power and are more easily scaled.

The layers in an IGZO transistor are deposited by both PVD and CVD, according to Max McDaniel, Applied Materials’ director and chief marketing officer for its display business. Figure 2 shows a cross-section of the device. “You use PVD to deposit the metal gate material (on the glass substrate), then you have an insulator over the top of the gate (GI = gate insulator in the figure). That’s deposited by PECVD. On top of that, you’ve got the active layer, which is the IGZO. This is deposited by PVD. Then you’ve an etch stop layer (ESTL in the figure) and that’s a PVD layer. Then you’ve got the source/drain, which is a metal deposited by CVD. Finally, you’ve got the passivation on the top which is a CVD layer,” McDaniel said. He noted that these interfaces between the CVD layers and the IGZO are critical. “We want to reduce the hydrogen as much as we can, so that’s what our technology helps the customer to do,” he said, adding that Applied Materials has the capability to build transistors in house and test them. “We’re able to solve some of these integration challenges before we deliver it to the customer.”

This time last year, Applied Materials introduced two new products. One offers a new design for depositing IGZO films for TFTs; the other handles bigger substrates of low temperature polysilicon (LTPS) films to help lower manufacturing costs.

The three new products now being introduced are the Applied AKT-PiVot 55K DT PVD, Applied AKT-PiVot 25K DT PVD and Applied AKT 55KS PECVD. The 55k nomenclature is a reference to the Gen 8.5 size panesl the system can handle, which are 2.2m x 2.5 m, or 55,000 cm2. DT stands for “dual track” which is new.

The AKT-55KS

The AKT-PiVot DT PVD system.

One of the key changes in the 55KS PECVD system include is related to how process gas is distributed the substrate surface. “The hundreds of thousands of holes that the gas is distributed out of – you have to customize them across the whole area of the chamber to compensate for the shape of the plasma,” McDaniel said. “It’s not just the diameter of the holes, it’s the depth of them.” A new gas deflector pre-distributes the gas before it goes into the diffuser, and support structures were added to achieve a higher degree of flatness over the 2.5 wide area.

New hardware provide better gas distribution and better uniformity.

On the PVD side, the new systems are designed specifically for IGZO. “Unlike our prior Pivot PVD system, where you want to have lots of chambers and be able to run multiple materials in different chambers, customers really want a system that just deposited the IGZO,” McDanield said. “It gets the substrates in and out quickly, so this is a compact, efficient platform that’s designed for depositing the IGZO.” The 25K system is targets displays for mobile applications. “We’re entering a whole new segment,” McDanield added.

The Pivot employs a set of rotary cathodes and targets, which act quite differently than conventional planar targets. Planar targets don’t get consumed uniformly and there can be redeposition of the material back onto the target. This redeposited material can spall off as particles. “Our technology is different,” McDaniel said. “The target is an array of rotating targets/cathodes. As they are being bombarded and consumed, you’re actually rotating the tubes in a circle and consuming them evenly throughout the deposition. The other benefit is this is a reactive process so you also have to introduce oxygen gas into the reaction. With the planar cathode, you have to introduce the gas from around the sides of the planar target. It’s hard to get it evenly over the substrate. With this array of tubes, you can introduce the process gas in between the tubes and get it uniformly distributed over the substrate,” he said. The rotary cathode employ magnets inside the tubes for uniformity enhancement.

Old-style planar (left) vs new-style rotary (right).

Material can redeposit onto planar cathodes (left) but that doesn't happen on rotray cathodes (right).

McDaniel added that presently everyone who is doing metal oxide IGZO use the etch stop (ES) structure (Figure, right), but would like to eliminate the etch stop and use a back channel etch (BCD) directly (Figure, left). “The IGZO material is very sensitive to hydrogen. What you’re trying to do is not expose it to the etching chemistry,” he said. “You put an etch stop layer on top of the IGZO, which is a CVD SiO2 process, and that protects it while you’re etching the source and drain. That adds an extra mask and extra process step. The panel makers would like to get rid of that etch stop layer and go to a back channel etch (BCE). This is where you etch the source drain directly down all the way to the IGZO and it’s unprotected. We’re not there yet, but the industry would like to see that structure developed. That’s on the roadmap for the industry.”

The display industry hopes to use a back channel etch (left), but presently uses an etch stop layer (right), which adds an extra mask and process step.

Looking forward, the holy grail for the display industry might just be the flexible display. McDaniel said flex displays will not likely be based on LCDs, but OLEDs. “For flexible OLED, you want to deposit on a flexible, non-glass substrate and then you need to encapsulate the OLEDs with something other than rigid glass.” This could require numerous thin films, which is good news for a supplier of tool deposition systems. He added that they would probably require an alternative to ITO (a commonly used transparent conductor). “There are a number of ITO replacement materials that are being looked at now, so as metal mesh, nanowires and even carbon nanotubes,” he said.

Marrying diversification, innovation with high-volume manufacturing – the MEMS puzzle

Tuesday, October 8th, 2013

By Sara Verbruggen

Initiated by Apple’s launch of the iPhone, the subsequent explosive growth of the smartphone market has provided the MEMS industry with one of its biggest opportunities to supply high-volume demand. But if motion sensing in our portable electronics – enabled by accelerometer and gyroscope MEMS applications for example – is the tip of the iceberg for MEMS technology how can the semiconductor industry ensure that high volume markets like consumer electronics benefit from all that MEMS potentially has to offer.

As the MEMS industry evolves, in terms of further diversification of device applications in higher volumes, this creates manufacturing challenges.

‘Organizations like MIG are helping to set standards across classes of devices in terms of specifications, rating, test interfaces, and system interfaces, and this is a great advancement in helping the industry to grow. On the manufacturing side though it is unlikely that a “standard” MEMS flow will emerge even within individual foundries except for very specific and limited types of MEMS – Invensense NF Process is an example of an attempt at this,’ comments Silex Microsystems’ VP of marketing and strategic alliances Peter Himes.

The emergence of MEMS technology over the last decade into high volume markets – consumer electronics especially – has presented the semiconductor industry with the challenge of designing and fabricating devices with different functionalities (as opposed to focusing on scaling down while ramping performance). This has paved the way for electronics in industries as diverse as healthcare, energy, security and environment. The long-term growth of MEMS depends on functional diversification but also being able to manufacture devices for these various applications in significant volumes and bringing down cost.

More than Moore techniques and processes

Wafer-scaling fabrication and process technologies, to enable these ‘More than Moore architectures’ are beginning to become established in MEMS manufacturing, for high volume markets.

SEMI’s chief marketing officer Tom Morrow says: ‘To be competitive in high-volume MEMs markets, 8” production equipment and economies will be, if not already, needed. Deep reactive ion etch (DRIE) “tuned” for MEMs technologies are also required, coupled with advanced cleaning solutions such as plasma. Bonding is, with DRIE, the other key MEMS-specific technology, used for wafer level capping and wafer level packaging.’ Critical concerns include providing good hermetic solutions to maintain performance of sensitive moving parts like gyros, while taking up less area on the wafer with bond lines. ‘The bonding process tends to take time, so throughput is typically low. Room temperature bonding and temporary bonding are areas of major improvement,’ adds Morrow.

DRIE and wafer bonding are the technologies subject to significant process improvement as both technologies are increasingly used in the mainstream semiconductor industry for 3D-TSV. In addition packaging and bonding technologies today support increasing standardization.

‘While contact and proximity aligners remain prominent lithography tools for MEMs, there is some movement towards projection steppers for better CD uniformity and automated 8” volume production,’ according to Morrow. Tools also need to be able to handle thin wafers and manufacturers also demand better overlay precision.

TSV is a critical technology, agrees Silex Microsystems’ Peter Himes. The company has specialised in TSV integration into MEMS since 2005 when its Sil-Via technology went into first production. This process, developed for the mobile industry, consisted of an all-silicon interposer for 2.5D integration of a MEMS microphone and ASIC onto a silicon substrate which was then solder- bumped and mounted directly onto the PCB.

‘Since then, we have been developing more TSV options for our customers, including TSV for buried cavity MEMS, TSV for capping solutions of either MEMS or CMOS, and both metal TSV and TGV through glass substrates for RF and power applications,’ says Himes.

As MEMS companies increasingly move beyond competing on manufacturing technology to competing on functionality, more of TSV/WLP packaging solutions will become widely-used platforms, predicts Yole Développement. This would also make more use of the outsourced infrastructure to reduce costs and speed-up development time.

‘Today, a few MEMS companies such as VTI, STMicroelectronics, Robert Bosch or MEMSIC have successfully implemented 3D wafer-level packaging concepts by using TSV/TGV vertical feedthrough, redistribution layers, and bumping processes to directly connect the silicon part of the MEMS/sensor to the final motherboard but without using a ceramic, leadframe, or plastic package. We believe this trend will be accelerated even further with the shift to 200mm wafer manufacturing for MEMS: it just makes sense to use wafer-level packaging, because as soon as you can add more dies on a wafer, it is more cost-effective,’ says Eric Mounier from Yole.

AMAT’s Mike Rosa points out that wafer-scale integration techniques, to enable more device functionality on a per die area basis, in combination with system-on-chip technologies to enable greater intelligence on die is becoming a standard requirement for more advanced MEMS.  ‘The end-users (system integrators – like Apple or Samsung for example) now require the MEMS device to do a lot more of the signal processing than has traditionally been the case – hence MEMS designers have to include more signal processing (CMOS) capability on die,’ says Rosa.

Fabless model

The fabless approach in the MEMS industry is now well-established, where, in order to speed up MEMS development device cycles, foundry companies partner with designers to provide them with process modules around which designers can develop MEMS devices.

But for the fabless model to facilitate the development of more differentiated and disruptive MEMS and to ensure companies remain competitive manufacturers need to be able to embrace and adopt new manufacturing processes and material technologies – which accompany disruptive new MEMS devices. ‘In the foundry space, it’s the foundry partner who is strongest in technology development that will win market share – this there is already a clear ‘pecking order’ with the big three foundries today and that is for a very good reason,’ says Rosa.

Silex is an example of a successful business servicing the fabless segment, through its program with AMFitzgerald. ‘The fact is that new companies cannot afford the cost of building a MEMS manufacturing line, and need a foundry infrastructure to get their products to market,’ says Himes.

Several key factors point to a strengthening fabless market in the long term, he observes. These include an ongoing reduction in overall development times for MEMS over the past two decades, lowering the time to market for new MEMS devices ‘though Yole is correct in saying that it needs to come down further,’ he adds. Increasingly fabless start-ups are driving innovation in MEMS-based functionality. ‘The percentage of MEMS revenues which comes from components not on the market before 2006 has been steadily growing, pointing to increased diversity and expansion of the MEMS- enabled market,’ says Himes pointing to a recent iSuppli presentation.

‘In terms of what works, Silex’s systematic SmartBlock-based approach toward process integration coupled with our defined new product introduction (NPI) process has proven to be the best way for us to manage the risk and uncertainty which comes with any process development. While customers always want shorter time to full production, an early focus of our customer programs is to get the customer fully functional samples as early as possible so that the rest of the component or system can be developed,’ Himes explains.

According to Mounier a successful fabless model relies on a MEMS designer, or similar business, finding a reliable foundry working on the long term. ‘Depending on the application, the foundry will have to be competitive on cost (consumer, automotive) or performances (defense, industrial applications). However, as many new MEMS devices are emerging in for new applications, such as touchscreens and flat speakers, MEMS foundries must be able to think about adapting the customer design to their own process flow.’

The RocketMEMS program run by AMFitzgerald & Associates is a good example. The company has defined a product design platform for rapidly commercializing semi-custom MEMS devices (pressure sensors is the first area) based on a pre-qualified manufacturing flow at Silex. ‘We think that this is an efficient path toward design enablement that can avoid the “one product, one process” paradigm in the long term,’ says Himes. Customers would be prioritizing time to market and customized form-fit-function over fully customized and optimized MEMS process flow. ‘We can envision many more such programs being set up worldwide, and thereby expanding the capability of doing MEMS design from the PhD level down to a broader class of component design engineers,’ he adds.

There are various challenges in the MEMs industry, owing to both the required process craftsmanship seen in advanced devices and the sheer proliferation of device types. Morrow observes: ‘Foundries continue to address these challenges through process capability improvement, and are benefitting from a maturing design process ecosystem that understands the need for integration with manufacturing, particularly in high-volume segments such as inertial sensors, microphones, and optical MEMs. Lower volume products, highly specialized device types, unique packaging or ASIC integration requirements seem to support IDM-type manufacturing.’

The Week In Review: Sept. 30

Monday, September 30th, 2013

Applied Materials Inc. and Tokyo Electron Limited this week announced Applied Materials agreed to merge with Tokyo Electron in a deal valuing the Japanese semiconductor production equipment maker at $9.3 billion, creating a giant in the chip and display manufacturing-tools sector.

Micron Technology, Inc. announced that it is shipping 2GB Hybrid Memory Cube (HMC) engineering samples. Micron expects future generations of HMC to migrate to consumer applications within three to five years.

The Fraunhofer Institute for Solar Energy Systems ISE, Soitec, CEA-Leti and the Helmholtz Center Berlin jointly announced this week having achieved a new world record for the conversion of sunlight into electricity using a new solar cell structure with four solar subcells.

Fujifilm and imec have developed a new photoresist technology for organic semiconductors that enables the realization of submicron patterns.

Mentor Graphics announced the latest release of its a FloEFD concurrent computational fluid dynamics (CFD) product.

Applied Materials – Tokyo Electron Merger Hastens EDA Changes

Monday, September 30th, 2013

Paradoxically, the merger of equipment manufacturers AMAT and TEL may shrink the Electronic Design Automation (EDA) tool market while improving IP security.

In the last several days, much has been written about the proposed merger of Applied Materials (AMAT) and Tokyo Electron (TEL). Desired by both, this merger would create a company worth $29B that would be the largest semiconductor equipment company in the world by sales. In comparison, the EDA tool market is roughly valued at $1.1B.

This merger of capital equipment giants represents an ongoing consolidation of the semiconductor supply chain, from chip/component developers through the IDM/foundries and manufacturing space. One reason for this consolidation is the increasingly high costs of making chips smaller and smaller – e.g., at the leading edge process nodes.

At first glance, it would appear that the merger will have little impact on the world of semiconductor intellectual property (IP). Still, one of the stated goals of the merged companies is to extract costs, “from all layers of the supply chain,” according to a recent report from Canaccord Genuity’s analyst Josh Baribeau (see, “Size Matters: Our First Take on AMAT’s Proposed Merger with Tel.”)

While admittedly far down on the supply chain relative to capital equipment, the Electronic Design Automation (EDA) tool market – heavy dependent on design and verification IP – might feel the effects of this merger in several ways.

First, equipment manufactures use EDA tools and related processes to qualify new manufacturing systems. For example, last year Applied Materials supplied critical film properties (new materials) and device characterization data from its advanced process systems to Synopsys. This allowed the EDA vendor to create more accurate chip design and verification models.

Such new materials and processes are necessary to keep Moore’s Law on track, in contrast to the ever increasing lithographic costs at lower and lower nodes. Several new technologies and process node shrinks are also driving up the cost of manufacturing leading edge chips – such things as 3D NAND devices, 450mm wafers, finFET structures, stacked dies and more.

Still, the cost of EDA tools are low in relationship to other costs. According to long-time EDA analyst Gary Smith, the cost of EDA tools is analogous to lunch money. The real costs in SoC development are related to the cost of engineers to do the design. Greater level of chip design-verification tool automation will reduce these costs, as will, “the reuse of software, the reuse of verifiable design IP, and by reducing SoC core blocks below the typical five blocks.” (see, “Gary Smith’s Sunday Night, Pre-DAC Forecast”)

It may well be that consolidation by the equipment manufactures will result in accelerated consolidation of the lower part of the semiconductor supply chain, e.g., EDA tool vendors. Judging from the furry of acquisitions in the EDA community over the last several years, this scenario is hardly surprising.

On the other hand, this merger of equipment giants might be a good thing for the development of soft IP standards. As Warren Savage pointed out a few months ago (see, “Long Standards, Twinkie IP, Macro Trends, and Patent Trolls“), the semiconductor equipment companies need to approve any IP design standards since it will be their systems that must read the soft IP.

Consolidation of the equipment market should mean fewer companies that need to approve any such standards, thus (in theory) hastening the approval process.

Will the end result of the AMAT and TEL merger mean further consolidation of EDA tools and hence the IP markets? Will the merger lead to greater IP protection at the lower process nodes? The answer will probably be revealed in the next installment of Moore’s Law, i.e., the next process node advancement.

Experts Roundtable: More than Moore – manufacturing challenges for MEMS

Friday, September 27th, 2013

By Sara Verbruggen

Semiconductor Design & Manufacturing discussed ‘More than Moore‘ (MtM) standardization topics and challenges with Peter Himes, VP of marketing and strategic alliances at Silex Microsystems, Dr Eric Mounier, senior analyst, MEMS devices and technologies at Yole Développement, Tom Morrow, chief marketing officer at SEMI and Mike Rosa, senior global product strategic marketing manager – emerging technologies, 200mm components and systems group at Applied Materials. What follows are excerpts of that conversation.

SemiMD: What is the scope and potential for further standardization in MEMS fabrication – for example, consumer markets such as handheld/portable electronics demand MEMS that are smaller and lower in cost, but to what extent does the diversity in MEMS devices in terms of their functionality, applications and manufacturing defy standardization and how can this be overcome?

Peter Himes: In the MEMS industry I would say that the opportunity for standardization today is limited, but the potential for more standardization in certain areas is sure to develop. Think about the mechanical goods and products you use each day. Are all corkscrews identical? Do all blenders look the same? Are they manufactured exactly the same? Yet they all perform the same function. This is where MEMS is today, with differentiation through MEMS design. You can say that for all blenders the motor element can be the same and products can differentiate with functionality and product design, and maybe that is a model for certain classes of MEMS moving forward.

Eric Mounier: Standardization is definitively an issue for MEMS manufacturing. However, standardization can occur at two levels; packaging standardization and front-end process standardization. Both are underway in the MEMS industry.

Referring to packaging standardization, MEMS types of packaging are more complex than most standard IC packages because they require a System-in-Package type of assembly. Additionally, sensor packages are generally quite bulky and can have very specific constraints like a module with a cavity, a hole in the substrate or metal lead for pressure sensors and microphones, an optical window for optical MEMS, or a full vacuum hermeticity at the die level. As a result, standardization is becoming increasingly critical to support the massive volume grow in unit shipments along with decreasing overall costs associated with MEMS and sensor content, in particular related to their packaging. If we look at one specific MEMS example, a microphone for instance, these are all packaged the same way: BGA/LGA laminate PCB substrate + SiP module assembly with wire bonding + metal lid or PCB cap with integrated shielding + “hole” for air access.

Tom Morrow: The history and dynamics of the MEMs industry has not facilitated MEMs manufacturing standardization as we have seen in the semiconductor industry.  This is partly due to the diversity of devices where rapid adoption of some early products  — such as tire pressure monitoring, air bag deployment sensors, ink jet printing heads, and others — initially encouraged the “one product, one process” character of today’s industry.

Early on, the need for advanced and integrated process expertise as a requirement for product development challenged the development of fabless MEMS companies. It also challenged foundries whose expertise and business model depended on a “many products, one process” approach to serve multiple customers necessary to amortize their capital investment. Accelerometers, microphones and optical components are extremely diverse products requiring unique process capabilities, application “know-how” and design tools. MEMs companies were forced to develop new products with their own custom process expertise and/or depend on a manufacturing partner for joint development of new products. Also, as most MEMs manufacturing was on 6” and less wafers with secondary equipment, there was no compelling reason to standardize key equipment types and their supporting integration requirements, as there are in leading-edge semiconductors.

Mike Rosa: Today, the bulk of all high volume MEMS are built on 200mm wafers in order to satisfy the volume/price requirement – this wafer size is currently under a lot of pressure due to ASP erosion 3-5% per quarter on MEMS devices.  This has led a number of segment leaders to explore MEMS development on fully depreciated 300mm toolsets, not for the advanced line width capabilities of 300mm but simply because they can fit more devices per wafer. This combined with advanced packaging techniques will increase the number of die per wafer and reduce the per die footprint. This is currently considered the final incarnation of MEMS on wafer based technologies – beyond this, other manufacturing techniques such as roll-to-roll or large area substrate (akin to glass panel for flat screen TV) are being explored at the R&D level in an effort to support the latest drivers of mega-volume MEMS, such as wearable computing, trillion sensor vision and so on, which will require around two orders of magnitude price reduction over current MEMS devices with equivalent or increased device capability. With specific regard to the diversity in MEMS design/fabrication and its impact on their manufacturability and cost, the segment as a whole is now past this, to a large extent, with all participating vendors now owning the requisite manufacturing tools to make a variety of MEMS devices. Because of this the basic problem has reduced to number of die on a wafer and techniques used to make MEMS smaller (which means due to their requirement for minimum mass, either vertical integration of wafers/die or new sensing materials/techniques to replace current MEMS functions).

How are MEMS foundries standardizing MEMS fabrication processes to deliver faster turnaround, lower costs and reducing time to market for new MEMS device designs?
Mike Rosa: While there is, of course, a lot of discussion around standardization of MEMS processes, the reality is that very little can and is being done in this area. The foundries are usually followers in this space and work to adopt processes that can support the highest volume MEMS devices in the hope that they obtain work orders by second tier suppliers, fabless companies or overflow orders from IDMs. In recent times some of the ‘bright spots’ in standardization have occurred around the licensing of successful MEMS design architectures – fabless company Invensense is an example here, which licensed its fabrication process for Ge/Si integrated devices based on an advanced packaging technique.

Tom Morrow: As the MEMs market has grown, foundries have increasingly improved their processes, IP and technology necessary to support economical, high-volume production. Many MEM foundries have invested millions of dollars over the past several years in preparation for the emergence of a fabless MEMs market and are seeing the benefits of their efforts come to fruition.  They have invested in process capabilities, PDK and design support, are moving from custom manufacturing to platform manufacturing flows, and have leveraged their relationships with packaging and test houses to compete with MEMs IDMs.  Their standardization efforts are focused on internal or proprietary standards — how to move from custom flows to platform flows — to achieve economies of scale and work with their package and test partners on standard, repeatable, back-end business. MEMs process technology is also being increasing licensed further facilitating advanced MEMs capabilities by foundries.

Eric Mounier: We expect that as MEMS companies increasingly move beyond competing on manufacturing technology to competing on functionality, thus more of TSV / WLP packaging solutions will become widely-used platforms. A good example of an “in-house” front-end process standardization is the MIDIS platform from Teledyne Dalsa. Depending on the customer’s request, MIDIS has been developed to have a minimal change of design and process to answer the customer request. But Teledyne Dalsa is not the only one having such a standardized solution. Silex Microsystems and MEMScap have technology platforms. Other MEMS foundries with product platforms include Tronics and XFab.

Peter Himes: Today each foundry has their own efforts in this area. Some offer “standard platforms” but being able to use it depends on an exact fit of the intended design to the process flow. However, even these standard platforms should not imply they are standard across different fabs or foundries.

At Silex we have a methodology of standardizing at the block level which we call the SmartBlock approach. A process flow can be built out of two or three SmartBlock elements, plus product specific processing, to create the final process flow. This does not eliminate the process integration work or need to prove the process flow concept with actual silicon before starting any production qualification, but it does help substantially in de-risking the development, which translates in the long run to lower costs, faster time to market, and fewer unique process development efforts.

Solid State Watch: September 20-26

Friday, September 27th, 2013
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