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Posts Tagged ‘ALD’

Picosun and Hitachi MECRALD Process

Friday, February 24th, 2017


By Ed Korczynski, Sr. Technical Editor

A new microwave electron cyclotron resonance (MECR) atomic layer deposition (ALD) process technology has been co-developed by Hitachi High-Technologies Corporation and Picosun Oy to provide commercial semiconductor IC fabs with the ability to form dielectric films at lower temperatures. Silicon oxide and silicon nitride, aluminum oxide and aluminum nitride films have been deposited in the temperature range of 150-200 degrees C in the new 300-mm single-wafer plasma-enhanced ALD (PEALD) processing chamber.

With the device features within both logic and memory chips having been scaled to atomic dimensions, ALD technology has been increasingly enabling cost-effective high volume manufacturing (HVM) of the most advanced ICs. While the deposition rate will always be an important process parameter for HVM, the quality of the material deposited is far more important in ALD. The MECR plasma source provides a means of tunable energy to alter the reactivity of ALD precursors, thereby allowing for new degrees of freedom in controlling final film properties.

The Figure shows the MECRALD chamber— Hitachi High-Tech’s ECR plasma generator is integrated with Picosun’s digitally controlled ALD system—from an online video ( describing the process sequence:

1.  first precursor gas/vapor flows from a circumferential ring near the wafer chuck,

2.  first vacuum purge,

3.  second precursor gas/vapor is ionized as it flows down through the ECR zone above the circumferential ring, and

4.  second vacuum purge to complete one ALD cycle (which may be repeated).

Cross-sectional schematic of a new Microwave Electron Cyclotron Resonance (MECR) plasma source from Hitachi High-Technologies connected to a single-wafer Atomic Layer Deposition (ALD) processing chamber from Picosun. (Source: Picosun)

The development team claims that MECRALD films are superior to other PEALD films in terms of higher density, lower contamination of carbon and oxygen (in non-oxides), and also show excellent step-coverage as would be expected from a surface-driven ALD process. The relatively density of these films has been confirmed by lower wet etch rates. The single-wafer process non-uniformity on 300mm wafers is claimed at ~1% (1 sigma). The team is now exploring processes and precursors to be able to deposit additional films such as titanium nitride (TiN), tantalum nitride (TaN), and hafnium oxide (HfO). In an interview with Solid State Technology, a spokesperson from Hitachi High-Technologies explained that, “We are now at the development stage, and the final specifications mainly depend on future achievements.”

The MECR source has been used in Hitachi High-Tech’s plasma chamber for IC conductor etch for many years, and is able to generate a stable high-density plasma at very low pressure (< 0.1 Pa). MECR plasmas provide wide process windows through accurate plasma parameter management, such as plasma distribution or plasma position control. The same plasma technology is also used to control ions and radicals in the company’s dry cleaning chambers.

“I’m really impressed by the continuous development of ALD technology, after more than 40 years since the invention,” commented Dr. Tuomo Suntola, and the famous inventor and patentor of the Atomic Layer Deposition method in Finland in 1974, and member of the Picosun board of directors. “Now combining Hitachi and Picosun technologies means (there is) again a major breakthrough in advanced semiconductor manufacturing.”

MECRALD chambers can be clustered on a Picosun platform that features a Brooks robot handler. This technology is still under development, so it’s too soon to discuss manufacturing parameters such as tool cost and wafer throughput.


Applied Materials’ Olympia ALD Spins Powerful New Capabilities

Monday, July 13th, 2015


By Ed Korczynski, Sr. Technical Editor

Applied Materials today unveiled the Applied Olympia ALD system, using thermal sequential-ALD technology for the high-volume manufacturing (HVM) of leading-edge 3D memory and logic chips. Strictly speaking this is a mini-batch tool, since four 300mm wafers are loaded onto a turn-table in the chamber that continuously rotates through four gas-isolated modular processing zones. Each zone can be configured to flow any arbitrary ALD precursor or to exposure the surface to Rapid-Thermal-Processing (RTP) illumination, so an extraordinary combination of ALD processes can be run in the tool. “What are the applications that will result from this? We don’t know yet because the world has never before had a tool which could provide these capabilities,” said David Chu, Strategic Marketing, Applied’s Dielectric Systems and Modules group.

Fig.1: The four zones within the Olympia sequential-ALD chamber can be configured to use any combination of precursors or treatments. (Source: Applied Materials)

Figure 1 shows that in addition to a high-throughput simple ALD process such that wafers would rotate through A-B-A-B precursors in sequence, or zones configured in an A-B-C-B sequence to produce a nano-laminate such as Zirconia-Alumina-Zirconia (ZAZ), almost any combination of pre- and post-treatments can be used. The gas-panel and chemical source sub-systems in the tool allow for the use up to 4 precursors. Consequently, Olympia opens the way to depositing the widest spectrum of next-generation atomic-scale conformal films including advanced patterning films, higher- and lower-k dielectrics, low-temperature films, and nano-laminates.

“The Olympia system overcomes fundamental limitations chipmakers are experiencing with conventional ALD technologies, such as reduced chemistry control of single-wafer solutions and long cycle times of furnaces,” Dr. Mukund Srinivasan, vice president and general manager of Applied’s Dielectric Systems and Modules group. “Because of this, we’re seeing strong market response, with Olympia systems installed at multiple customers to support their move to 10nm and beyond.” Future device structures will need more and more conformal ALD, as new materials will have to coat new 3D features.

When engineering even-smaller structures using ALD, thermal budgets inherently decrease to prevent atomic inter-diffusion. Compared to thermal ALD, Plasma-Enhanced ALD (PEALD) functions at reduced temperatures but tend to induce impurities in the film because of excess energy in the chamber. The ability of Olympia to do RTP for each sequentially deposited atomic-layer leads to final film properties that are inherently superior in defectivity levels to PEALD films at the same thermal budget:  alumina, silica, silicon-nitride, titania, and titanium-nitride depositions into high aspect-ratio structures have been shown.

Purging (from the tool) pump-purge

Fab engineers who have to deal with ALD technology—from process to facilities—should be very happy working with Olympia because the precursors flow through the chamber continuously instead of having to use the pump-purge sequences typical of single-wafer and mini-batch ALD tools used for IC fabrication. Pump-purge sequences in ALD tools result in the following wastes:

*   Wasted chemistry since tools generally shunt precursor-A past the chamber directly to the pump-line when precursor-B is flowing and vice-versa,

*   More wasted chemistry because the entire chamber gets coated along with the wafer,

*   Wasted cleaning chemistry during routine chamber and pump preventative-maintenance,

*   Wasted downtime to clean the chamber and pump, and

*   Wasted device yield because precursors flowing in the same space at different times can accidentally overlap and create defects.

“Today there are chemistries that are more or less compatible with tools,” reminded Chu. “When you try to use less-compatible chemistries, the purge times in single-wafer tools really begin to reduce the productivity of the process. There are chemistries out there today that would be desirable to use that are not pursued due to the limitations of pump-purge chambers.”


3DIC Technology Drivers and Roadmaps

Monday, June 22nd, 2015


By Ed Korczynski, Sr. Technical Editor

After 15 years of targeted R&D, through-silicon via (TSV) formation technology has been established for various applications. Figure 1 shows that there are now detailed roadmaps for different types of 3-dimensional (3D) ICs well established in industry—first-order segmentation based on the wiring-level/partitioning—with all of the unit-processes and integration needed for reliable functionality shown. Using block-to-block integration with 5 micron lines at leading international IC foundries such as GlobalFoundries, systems stacking logic and memory such as the Hybrid Memory Cube (HMC) are now in production.

Fig. 1: Today’s 3D technology landscape segmented by wiring-level, showing cross-sections of typical 2-tier circuit stacks, and indicating planned reductions in contact pitches. (Source: imec)

“There are interposers for high-end complex SOC design with good yield,” informed Eric Beyne, Scientific Director Advanced Packaging & Interconnect for imec in an exclusive interview with Solid State Technology. ““For a systems company, once you’ve made the decision to go 3D there’s no way back,” said Beyne. “If you need high-bandwidth memory, for example, then you’re committed to some sort of 3D. The process is happening today.” Beyne is scheduled to talk about 3D technology driven by 3D application requirements in the imec Technology Forum to be held July 13 in San Francisco.

Adaptation of TSV for stacking of components into a complete functional system is key to high-volume demand. Phil Garrou, packaging technologist and SemiMD blogger, reported from the recent ConFab that Hynix is readying a second generation of high-bandwidth memory (HBM 2) for use in high performance computing (HPC) such as graphics, with products already announced like Pascal from Nvidia and Greenland from AMD.

For a normalized 1 cm2 of silicon area, wide-IO memory needs 1600 signal pins (not counting additional power and ground pins) so several thousand TSV are needed for high-performance stacked DRAM today, while in more advanced memory architectures it could go up by another factor of 10. For wide-IO HVM-2 (or Wide-IO2) the silicon consumed by IO circuitry is maybe 6 cm2 today, such that a 3D stack with shorter vertical connections would eliminate many of the drivers on the chip and would allow scaling of the micro-bumps to perhaps save a total of 4 cm2 in silicon area. 3D stacks provide such trade-offs between design and performance, so the best results are predicted for 3DICs where the partitioning can be re-done at the gate or transistor level. For example, a modern 8-core microprocessor could have over 50% of the silicon area consumed by L3-cache-memory and IO circuitry, and moving from 2D to 3D would reduce total wire-lengths and interconnect power consumptions by >50%.

There are inherent thresholds based on the High:Width ratio (H:W) that determine costs and challenges in process integration of TSV:

-    10:1 ratio is the limit for the use of relatively inexpensive physical vapor deposition (PVD) for the Cu barrier/seed (B/S),

-    20:1 ratio is the limit for the use of atomic-layer deposition (ALD) for B/S and electroless deposition (ELD) for Cu fill with 1.5 x 30 micron vias on the roadmap for the far future,

-    30:1 ratio and greater is unproven as manufacturable, though novel deposition technologies continue to be explored.

TSV Processing Results

The researchers at imec have evaluated different ways of connecting TSV to underlying silicon, and have determined that direct connections to micro-bumps are inherently superior to use of any re-distribution layer (RDL) metal. Consequently, there is renewed effort on scaling of micro-bump pitches to be able to match up with TSV. The standard minimum micro-bump pitch today of 40 micron has been shrunk to 20, and imec is now working on 10 micron with plans to go to 5 micron. While it may not help with TSV connections, an RDL layer may still be needed in the final stack and the Cu metal over-burden from TSV filling has been shown by imec to be sufficiently reproducible to be used as the RDL metal. The silicon surface area covered by TSV today is a few percents not 10s of percents, since the wiring level is global or semi-global.

Regarding the trade-offs between die-to-wafer (D2W) and wafer-to-wafer (W2W) stacking, D2W seems advantageous for most near-term solutions because of easier design and superior yield. D2W design is easier because the top die can be arbitrarily smaller silicon, instead of the identically sized chips needed in W2W stacks. Assuming the same defectivity levels in stacking, D2W yield will almost always be superior to W2W because of the ability to use strictly known-good-die. Still, there are high-density integration concepts out on the horizon that call for W2W stacking. Monolithic 3D (M3D) integration using re-grown active silicon instead of TSV may still be used in the future, but design and yield issues will be at least comparable to those of W2W stacking.

Beyne mentioned that during the recent ECTC 2015, EV Group showed impressive 250nm overlay accuracy on 450mm wafers, proving that W2W alignment at the next wafer size will be sufficient for 3D stacking. Beyne is also excited by the fact the at this year’s ECTC there was, “strong interest in thermo-compression bonding, with 18 papers from leading companies. It’s something that we’ve been working on for many years for die-to-wafer stacking, while people had mistakenly thought that it might be too slow or too expensive.”

Thermal issues for high-performance circuitry remain a potential issue for 3D stacking, particularly when working with finFETs. In 2D transistors the excellent thermal conductivity of the underlying silicon crystal acts like a built-in heat-sink to diffuse heat away from active regions. However, when 3D finFETs protrude from the silicon surface the main path for thermal dissipation is through the metal lines of the local interconnect stack, and so finFETs in general and stacks of finFETs in particular tend to induce more electro-migration (EM) failures in copper interconnects compared to 2D devices built on bulk silicon.

3D Designs and Cost Modeling

At a recent North California Chapter of the American Vacuum Society (NCCAVS) PAG-CMPUG-TFUG Joint Users Group Meeting discussing 3D chip technology held at Semi Global Headquarters in San Jose, Jun-Ho Choy of Mentor Graphics Corp. presented on “Electromigration Simulation Flow For Chip-Scale Parametric Failure Analysis.” Figure 2 shows the results from use of a physics-based model for temperature- and residual-stress-aware void nucleation and growth. Mentor has identified new failure mechanisms in TSV that are based on coefficient of thermal expansion (CTE) mismatch stresses. Large stresses can develop in lines near TSV during subsequent thermal processing, and the stress levels are layout dependent. In the worst cases the combined total stress can exceed the critical level required for void nucleation before any electrical stressing is applied. During electrical stress, EM voids were observed to initially nucleate under the TSV centers at the landing-pad interfaces even though these are the locations of minimal current-crowding, which requires proper modeling of CTE-mismatch induced stresses to explain.

Fig. 2: Calibration of an Electronic Design Automation (EDA) tool allows for accurate prediction of transistor performance depending on distance from a TSV. (Source: Mentor Graphics)

Planned for July 16, 2015 at SEMICON West in San Francisco, a presentation on “3DIC Technology Past, Present and Future” will be part of one of the side Semiconductor Technology Sessions (STS). Ramakanth Alapati, Director of Packaging Strategy and Marketing, GLOBALFOUNDRIES, will discuss the underlying economic, supply chain and technology factors that will drive productization of 3DIC technology as we know it today. Key to understanding the dynamic of technology adaptation is using performance/$ as a metric.

Experts at the Table: Focus on Semiconductor Materials

Monday, November 3rd, 2014

By Jeff Dorsch

The cutting edge in semiconductor manufacturing has meant not only big changes in IC design and process technology, but also in semiconductor materials. What follows are responses from Linde Electronics; Kate Wilson of Edwards Vacuum; David Thompson, Technology Director, Process Chemistries, Silicon Systems Group, Applied Materials; and Ed Shober, General Manager, Advanced Materials, Air Products and Chemicals.

1. What changes are being made in materials in fabrication of FinFETs, gate-all-around transistors, vertical NAND and fully-depleted silicon-on-insulator processes? Are there other new developments and trends in semiconductor materials (in interconnects, for example)?

Kate Wilson: We are seeing an increase in MOCVD precursors, low-temperature precursors and switching of process gases for ALD and multilayer films.

Linde Electronics: These devices will be implemented at aggressive nodes, e.g., 14/16 nm and below. Due to the unavailability of EUV lithography in HVM for at least the next 2—3 years, chip makers are forced to use multiple patterning techniques, which have led to several additional deposition and etch steps being incorporated relative to previous generations.

Of the devices mentioned, FinFETs and vertical NAND are becoming or will soon become mainstream in leading-edge logic and NAND fabs. Given that key parts of the device structures are approaching dimensions that are tens of atoms across, the tolerance for variability in the manufacturing process is significantly reduced, which in turn imposes special demands on materials suppliers to control variation in the quality of the electronic materials (EM) products supplied to a fab. This requires additional metrology and quality control techniques to be used across the EM supply chain, from incoming raw material to in-process material to finished product.

In addition, these advanced devices are more sensitive to any unspecified species in the EM products, and it is crucial to measure trace levels of unspecified impurities and understand their potential interactions with the thin films and interfaces involved in these devices. Collaboration across all the supply chain participants is thus key. Looking ahead, novel channel materials such as germanium and III-V compound semiconductors will be required, which bring their own set of challenges in deposition and etch.

David Thompson: For all these architectures the big trends are the introduction of new materials to enable scaling and the increasing criticality of interfacial materials. Consistently meeting new material innovation and interface engineering requirements is what we call precision materials engineering. Numerous new materials are being used today to enable low-power, high-performance foundry/logic devices. Selective epitaxy and metal gate films deliver >2 nodes of performance scaling with no litho-scaling. The introduction of CVD Cobalt liner and selective Cobalt cap layers in interconnect improves device reliability by 80x by completely encapsulating interconnect with Cobalt. More potential new materials are being evaluated at 10nm and beyond in transistors and interconnect. In 3D NAND, SiN film is used to store electrons using charge trap storage technology, compared to planar NAND where polycrystalline Si film is used using floating-gate MOSFET technology.

Interface engineering is also becoming increasingly critical. Whether it’s the transistor metal films, the interconnect cladding, or 3D NAND, there are essential enabling films that require sub-angstrom uniformity control across the wafer that have thicknesses between 10 and 40 angstroms – that’s less than the diameter of an atom. Additionally, while the bulk properties of materials are a useful roadmap, developing an understanding of how barrier, electrical, and other properties are impacted when the material is so thin that it doesn’t exhibit bulk properties is the challenge of the day. In many cases, a very particular pretreatment is required to enable the specific material interface to tune these properties. We’re finding that increasingly these steps need to be carried out sequentially within a vacuum environment with no air breaks.

Ed Shober: For logic devices and the adoption of 3D transistors, such as FinFETs, there are many needs for new chemical precursors to deposit — for example, silicon nitride and silicon oxide at temperatures far lower than previously required. In earlier nodes the thermal budget was in the 450 to 600C range, now the budget has been reduced to the 250 to 400C range, and the expectation is that it will go lower in the future. The shallow dopant profiles around the fin structure is one of the reasons for this drive to lower temperatures. Atomic layer deposition (ALD) is playing a greater role in depositing films. Thus, the chemistries employed must adsorb and react on the surface quickly and allow for deposition of highly conformal films over high aspect ratio features. More metal precursors are being employed in the FEOL for logic in order to tune the work function of the transistors. In the BEOL the biggest metal change has been the adoption of cobalt as a copper capping film and as a barrier liner film.

Needs for CMP are also increasing with 3D transistor structures. There are at least three new CMP steps that need to be performed to fabricate the fin. Finally, cleaning continues to play a major role in preparing the structures for the next deposition step.

Vertical NAND is moving memory off the lithography road map and onto a track that is driven by number of SiO/SiN films in a stack. The material needs here are again ALD-based precursors for lining and filling the channels etches into these film stacks. A major driver in cleans is products that limit particles left on the wafer and the scale of these particles must be in the nm size range.

For all devices, but especially DRAM and logic, the delays in adopting EUV are driving the need for self-aligned double, triple and quadruple patterning. These patterning strategies require new materials for forming the structures needed to reduce the pattern dimensions.
2. What changes are necessary in pumps and abatement?

Wilson: Increased variety of precursors requires flexible product operating range and tailored set-ups by process. Collaboration with semiconductor tool manufacturers, collaborative research organizations and end-customer development facilities is becoming more critical to ensure best known methods are applied.

Shober: Compatibility with the chemical precursors which can be highly reactive is one necessary requirement. Particle generation by the components is also a major concern and must be addressed by the suppliers to the same scales as discussed in the above answer around semi materials.

3.  What are the risks involved with certain materials? Can they be disposed of safely? What about EPA regulation of these materials?

Wilson: Metal byproducts can be very toxic and containment of them can be challenging. Special care needs to be applied to their capture and disposal.  Many of the new precursors are flammable and pyrophoric as well as being highly toxic so abatement is essential. Safe handling of new flammable or pyrophoric deposition precursors puts additional challenges on the process equipment and its maintenance – leaks of material out of, and air leaks into, process equipment can have serious consequences and therefore have to be diligently avoided to prevent accidents. It’s essential that sub-fab equipment designed to support advanced CVD processes should be designed from the outset with safe operation and servicing in mind. Better yet, an integrated sub-fab system design and a single point of ownership for the whole sub-fab system provide some assurance that the system can be operated with the minimum risk of accidents due to inadequate maintenance. Advanced integrated dry-pump/exhaust system/abatement/thermal management systems are available from at least one reputable equipment supplier to support such advanced processes, and have been widely adopted by several top-tier device manufacturers to provide exactly such assurance of maximized risk reduction in their advanced CVD processes.

Shober: With the drive to lower thermal budget there is a trend to using chemical precursors that are more reactive and stable. Thus, how they are produced, packaged, shipped and used by the customers are risks that we must address as new products are introduced. Shipping is especially a concern because there are more limitations on what materials can be flown from one point to another. This is driving for more localization of production/purification to shorten supply chains. BCP is of course another concern. Customers are looking for multiple and secure supply of materials.

4. How can semi materials be made “greener”?

Wilson: Once upon a time there was a concerted effort by a number of companies to find greener alternatives to persistent PFC gases used in etching processes to address the “green problem” at source – in general they weren’t very successful and attention switched to abating the PFCs effectively instead. In the current environment, where increasingly exotic CVD precursors are being introduced into advanced device node manufacturing, it’s also likely that “greenness” will be more a result of diligent treatment of the waste precursors, their decomposition products and the solid residues left behind in the process equipment than efforts to make the materials themselves “green.” That puts the onus on abatement and waste treatment system manufacturers to develop suitable products to meet the emerging challenges, and the end-user community to accept responsibility for installing suitable waste treatment facilities.

In some instances, careful consideration has to be given to the balance between risk of gas release and cost to the environment of treating it – abatement of nitrous oxide (N2O) being a case in point. N2O is a greenhouse gas widely used in oxide CVD processes, and device manufacturers would prefer to abate it to reduce their GHG emissions. However, combustion of N2O consumes natural gas, generates carbon dioxide (CO2) and under adverse conditions can generate significant quantities of nitrogen oxides (NOx); so the question arises – which is the least bad situation?

Linde Electronics: Materials suppliers can contribute to greening of semi materials by:

  • Limiting emissions and waste over product life cycle

This includes material production, delivery and return/reclamation/disposal.

  • Substituting

Sometimes, despite the material selection constraints, direct, process-compatible substitutions can be made such as F2 (fluorine). See reference to this in the article “Material Support: Helping Displays Deliver Higher Performance” in the September, 2012 issue of Solid State Technology.

  • Packaging and processing for efficient use

Often headspaces are exhausted and heels are unused to prevent light and heavy contaminants. Better purification, quality control, packaging, and material property knowledge can reduce the amount of material lost to safeguarding quality.

  • Recovering material from waste streams

Examples of this are He (Helium), Ar (Argon), Xe (Xenon), H2SO4 (Sulphuric Acid). See reference to this in the blog post “Sustainability through Materials Recovery” at

Thompson: In many respects, semi materials are the greenest materials known and need to be taken in the context of not just as the materials in the chip but in what they end up consuming, for instance, power. A good example is the UNIVAC that ran at 1,905 floating point operations-per-second on 125 kW, while processors like today’s Tegra K1 run at 326 GFLOPS on 10 W – which uses a number of different materials that in effect reduce the power required per floating point operation by a factor of 1 trillion. Net reduced environmental impact will almost always favor choices that continue the power scaling trajectory. That being said, we need to be vigilant in managing the dangers and impact of some of the more hazardous materials that are being used which provide this net green benefit.

Shober: The industry made a major step to become greener when NF3 was adopted rather than fluorocarbons for cleaning CVD reactors. Solvent recovery and re-purposing for other use in either the fab or other industries is now being adopted. More and more cleaning processes are employing water-based formulations which reduces solvent usage at the fab. In the future IDMs will be looking for more ways to recapture and purify, recycle and/or re-purpose wastes into other uses at the site or outside into other industries.

5.  How are advanced processes, such as atomic-level deposition, affecting materials use?

Wilson: Diverting precursor and low utilization rates in the process cause higher unreacted material and waste.

Linde Electronics: Both atomic layer deposition (ALD) and atomic layer etch (ALEt) are key new processes required in leading-edge device manufacture because of the new elements being incorporated and the aggressive geometries being adopted to keep Moore’s Law on track. Several new EM products are now used in ALD, e.g. organometallic molecules. For ALEt, quite a few traditionally used EM products (e.g. chlorinated gases) are currently being evaluated. The selection of process materials becomes very challenging when multiple films are in close proximity, e.g. requiring high selectivity for etching one thin film without affecting two or more nearby materials.

Thompson: What we find is that the deposition technique or specific chemistries employed strongly impact material properties. There are almost no situations where when we migrate from one technology to another – say PVD to ALD – where we don’t see significant change in materials properties associated with the technique.

Additionally, in many cases the materials that the industry is accustomed to using are no longer available for a new technique. Usually, there’s a ripple effect on retuning other materials or processes to enable the new material. It’s an exciting time – there’s a renaissance of metallurgy in both the front end and back end.

Shober: ALD does have a tendency to reduce material consumption, but not to the degree one may expect as a result of the process itself. The biggest impact ALD is having is on chemical costs. Materials capable of being deposited by ALD are oftentimes novel and there only use is within the semi industry. Thus, the cost on a gram basis can be much higher than what the industry has come to expect from use of materials like TEOS.

Wrap-up: SEMI’s Strategic Materials Conference

Tuesday, October 7th, 2014

SEMI’s Strategic Materials Conference was held September 30-October 1, 2014, in Santa Clara, CA at the Biltmore hotel.

By Karey Holland, Techcet Group

The 2014 Strategic Materials Conference was very well attended.  There were people from several of the leading IC makers as well as suppliers of equipment and materials to the fabs.  Unfortunately, the audio and video systems were not stellar, so we had to endure some ear shattering system noise, and any light image was not visible on the screens.  Otherwise, the venue was good.  Throughout the conference, several themes were repeated.

Focus on the stability we hope for in post 2013 times, but concern about volatility and uncertainty of the world economics, esp. the recession-like growth numbers in Europe and Japan expected for the next few years. While forecasters (Gartner, IC Insights, VLSI Research, Linx, Techcet Group and others) anticipate IC wafer starts growing at ≥6% CAGR over the next 5 years, there is concern that any number of geo political world problems could throw us back into a global recession.  Attendees had a greater concern than the presenters over the possibility of a future recession, and that the impact would be greater to IC industry now due to the entrenchment of mobile platforms.

Focus on cost of lithography as a driver for increased cost of leading edge MCUs/MPUs … with current nodes, multi-patterning requires many more expose/develop/dep/etch steps than EUV, but EUV has not yet met the requirements for manufacturing implementation.  It is likely that EUV will first be used for only a few critical layers.  DSA (directed self-assembly) may be used also for a few selected critical layers, but issues of defects will likely keep it from use in many layers.

Focus on the expected (and currently numerous options) for advanced devices and implications for materials.  This includes advanced packaging technologies.

450mm wafers may continue to slip, if the other large IC makers (e.g. TSMC, Samsung, GlobalFoundries) don’t agree with Intel on first implementation date/node. Collaboration across the entire ecosystem was stressed for 450mm to become a reality.

Below are things I found particularly interesting in the presentations and/or at the end of day panel discussions.

The key note presentation, “Materials Innovation for the Digital 6th Sense Era,” was by Matt Nowak of Qualcomm.  He discussed both the vision of the Internet of Things (IoT), the required IC devices (including analog & sensors) and implications to materials (and cost to manufacture) from these new IC devices; a perfect start to SMC 2014.  Qualcomm defines the Digital 6th Sense Era is “the augmentation of human ability”, or as Sue Davis put it “intelligent data based extension of our 5 senses ==>to a 6th“. Essentially this is where the ability of the IoT/IoE data feedback can act as our 6th sense by capturing data about one & one’s environment which results in  prediction/information being shared based on data collection and/or user selections regarding the environment around us (or about us, e.g., tele-health).”  Because the smartphone is the “most pervasive platform ever” (US Android users average 106 Apps launched/day), it can serve as a remote connection to the IoT world … be that monitoring our health, schedules, honey-do lists, and improving our understanding and enjoyment of the world around us.  For advanced logic one might expect, lithography for advanced ICs (quad patterning vs EUV) were discussed as key cost drivers.  Other required/expected advanced materials include high mobility channel materials and thin barrier metals (likely Co). Beyond CMOS, new structures and materials may be required to support sensors (bio, chemical, fluidic), nano batteries, piezo, thermal, and solar harvesters.

Mark Thirsk, Linx-Consulting, reviewed IC growth and lack thereof for past years, and observed that 2014 will be “first good year in 8 years” (since 2006), and forecast 6-8% CAGR for the next few years – strongly dependent on the success of the IoT.  IC market growth since 2010 correlates strongly to GDP since 2010, and thus regional GDP differences (e.g. the current European recession) are reflected in IC demand.  Technology challenges & opportunities in for the next 5+ years include advanced logic (3D NAND, and new memory method after 2018), numerous AL (atomic layer) processes, 3D / advanced packaging, patterning efficiency, and complexity.  The electronic materials landscape is changing: the supply chain is merging, and there are new entrants (esp. from Korea, Taiwan & China) in advanced materials such as photoresists. Interestingly, China appears to be focusing more on investing in fabless than fabs.

Duncan Meldrum, Hilltop Economics, said that the current subdued market growth (3% 2013-16) is due to more fiscal responsible people. China & Asia are growing 4 to 7.7%, US & Latin America about 2.1 to 3.1, Euro <2%, and Japan ~1.5%.  The tax increase in Japan is having a very negative impact. He expects the US to see a 5% year over year improvement (very good news) with our investments finally growing in 2nd half of 2014.  He anticipates healthy, but not stellar consumer spending through 2016.

Patrick Ho, Stifel Nicolas, initially discussed that for companies that follow Moore’s Law, that it is increasingly Fab capital intensity (Capex) with addition of FinFETs, new materials (e.g. High k), 3D NAND, and Multi-Patterning (from delayed EUV).  One can assume this will continue to be the case as CMOS devices moves from Si channel to replacement channel filled with SiGe, Ge, or III-V and memories move to new technologies such as ReRAM, STTRAM, etc.  His observation is that only Intel is pulling for 450mm, and if TSMC & Samsung don’t exert more pull, 450mm may not happen (esp. in light of the negative impact to equipment revenue per square inch of silicon).  The top 4 OEMs (ASML, KLA-T, Lam, AMAT) are large enough to push back on the top 3 IC makers, and that consolidation is continuing.  Patrick noted that all 4 top OEMs have dividends, and he anticipates that they will eventually get better valuations.  He showed a nice list of companies he thinks are acquisition candidates (CMC, Nanometrics, Nikon, Nova, Axcelis, Rudolph, Veeco, FormFactor, and Ultratech).  Other comments:  Moore’s law lives, but is under stress.  Innovation w/ or w/o EUV will bring industry back to Moore’s Law.  Changing landscape will help economics of leading players.

Ross Kozarsky, who leads Lux Research’s advanced materials team, discussed the longer range materials he investigates such as graphene, 3D printing, and Meta-materials. Graphene film sheets are of interest for transparent conductive materials (e.g. touchscreens), possibly moving to FETs & sensors.  3D printing has been around 30 yrs; today it’s used mostly for prototyping, but manufacturing use makes sense and could really increase total growth.  Multifunctional and multi-materials printers will be needed.  Autonomous cars are now a big growth opportunity, opening great opportunity for chemical and material companies to innovate.

Geraud Duboix, IBM Almaden, develops porous low k materials for interconnect passivation and their integration (esp. plasma damage).  In the 0.65 to 0.1um timeframe, interconnect RC delay was slowing devices even though the transistors were getting faster, and thus began the drive for lower k insulators.  The ITRS has been showing the need for lower k since its inception, but it also has pushed out the date of the more aggressive low ks.  Initially to achieve lower k, C and F were added to SiO2 to break-up network structure.  Today, they are driving low k down by adding porosity.  Once a big concern, Geraud said that ULK mechanical properties are now no longer a concern with UV treatment, the lowest k being integrated is 2.3-2.4, and new low k materials are emerging. Geraud is working on porous low k materials, to achieve lower k, and larger pores deliver lower k.  He discussed the various pore-sizes in evaluation, the importance of porogens (material in the low k deposition that is later removed to create pores) and methods being used to seal the created pores (especially before conformal barrier metal deposition).  Interestingly, he commented that creating and sealing the larger pores is somewhat easier, although he’s being asked to work on the smaller pores for now.  During the panel discussion Mansour Moinpour (Intel) asked why Geraud was working on smaller pores that are more difficult to fill. Geraud responded that for the designers insulators with 2.0 or 1.8 k would be too big a change and they want 2.4 and 2.2 first.

Todd Younkin, from Intel’s central research (components) novel materials group, discussed that the industry will continue CMOS Scaling through 7nm. As stated by others, lithography is a challenge and using several methods to accomplish patterning, while productivity and pattern placement (alignment) are concerns.  Intel is working on devices with channels of higher mobility materials that Si (III-V or MoS2) as well as beyond CMOS (e.g., GAA) devices.  Todd said that early in device research development, Intel works to make sure manufacturing should be capable of meeting cost expectations. These include the cost of multi-patterning versus EUV, ultra-low k interconnect materials, etc.

Angela Franklin, of TriQuint (recently renamed Qorvo) discussed the challenges of supply management (and unlike others, she projects well when talking, so we could avoid the audio system problems … thanks Angela!).  Angela educated the audience about Qorvo devices (some look more like MEMS with permanent epoxy “cavity” structures that resonate w/ the RF) which are significantly different from the leading edge logic and non-volatile most of us follow.  Unlike the device manufactures that use Si, Qorvo uses smaller substrates of III-V and GaN.  Many films are already on the substrates when purchased.  The fab process is very solvent intensive, and only 1/3 aqueous.  Unlike others, Qorvo uses significant eBeam lithography with up to 28 different resists and many negative resists, as well as metal lift-off (my first job at IBM >30 yrs ago).

Prof. Philip Wong of Stanford gave his typical dynamic and mind-stretching presentation. His discussion was focused on the single digit nodes, and the possible new channel materials for logic (III-V or 2D MoS2, MoSe2, WSe2, WTe2 or ??) and possible new devices, including carbon nanotube FET (CNFET), STTRAM, CBRAM, ReRAM (using HfOx, TaOx, TiOx).  He said that memory chips will hold 32Tbits.  He then smiled and said “none of this before the next 10 years”.  He showed some exciting interleaved memory and logic ideas using a base of 2D or 3D FETs, topped by STTRAM, then 2D or 3D FETs, and then 3D RRAM.  Because the interconnects of the bottom device are present, all processing for the others must be at low temperature (<400C).

Discussion Panel.  When asked about collaboration with materials suppliers, Intel and IBM research had significantly different responses.  Intel invests dollars and works with graduate students on advanced projects and hopefully a “lucky accident” brings advances.  IBM research mentioned that legal issues often get in the way of collaboration with suppliers.

Notes for SMC Day 2 2014 Blog

Tim Hendry, from Intel’s supply management team started off day 2.  A large concern he brought up was what he described as the widening connections between fab, material suppliers, and sub-suppliers.  He then discussed the concerns and possible ways to improve connections, as well as the importance of metrology and verification of chemical quality.  Unfortunately, some of the sub-suppliers are very big chemical companies that have difficulty getting excited about the low volume materials used to make ICs.  He finished up by saying that Intel is focused on controlling the costs of manufacturing that require close partnerships with materials suppliers. Intel is driving for unprecedented collaboration among the materials and sub tier suppliers to achieve cost, performance and defect targets.  The cost of packaging and shipping materials globally is driving investigation into new operating models to cut costs.

Dennis Hausmann of LamRC/NVLS discussed ALD/CVD in more details than others.  For Each CVD/ALD step, an average of $2-$3/wafer is added to manufacturing cost, while only about $1/wafer of this is for chemistry+power+exhaust management.  He reviewed at least 4 versions of ALD tools (furnaces to single wafer) and said that there is a “right ALD tool” for the right deposition job.  He said that single wafer tools with proper development can meet same throughput as batch furnaces.  However, if you look at the development cost, single wafer tools are much better in cost.  For depositions that improve with plasma ALD, single wafer tools also make sense.  An important observation by Dennis was that for ALD, sometimes it is the unknown contaminant that “makes it go”.  This is something that has been observed in the past of copper plating chemistries, as well as some CMP slurries.

James ONeil, CTO Entegris had an interesting title, which should fit most suppliers “Accelerating yield in a disruptive environment”.  James emphasized that suppliers need meaningful process discussions, insights & collaboration with their customers.

Adrienne Pierce of Edwards introduced SCIS collaboration to most of us.  This is a supply chain collaboration working group.  Some topics are tracing defects origins and BKMs for specific process (e.g. ALD).

There were then two parallel sessions; one on advanced memories and the other on 3D packaging.  In the memory session, Norma Sosa of IBM talked about PCRAM (phase change memory, which Micron has been shipping for a few years now), Mark Raynor, Matheson, discussed RRAM for Non-Volatile, and Suresh Upa, SanDisk, discussed packaging implications.

After the breakout, we had presentations from four materials supplier companies.  The four same very similar things.  Dave Bern of Dow Chemical discussed using the “right tool” for collaboration and the importance of making sure suppliers agree to work in areas that fit their “core competencies”.  Wayne Mitchel of Air Products noted that ICs are only 2% of GDP.  He agreed with Dave Bern that suppliers should only agree to work (partner) with customer on areas within expertise, otherwise it takes too much time and money to execute successfully. Jean Marc Girard, Air Liquide discussed the numerous risks of supply chain, from the sub-supplier, the environment (e.g. earthquakes), and materials stability (or lack thereof). Kevin O’Shea of SAFC Hitech emphasized that taking materials from a catalog of low volume and ramping to IC manufacturing needs is not trivial, and may also not be consistent with the materials manufacturer (the sub-supplier, or company that is “primary” in the materials).

The day 2 Panel discussion had more audience participation.  Some discussions I found particularly interesting are discussed below.

Tim (Intel) said the gap is getting wider between Intel, suppliers, sub-suppliers (esp. customs for IC industry). The large sub-supplier that doesn’t have an interest in moving forward – there is no motivation to increase metrology, metrics, etc.  The shrinking sub-supplier base isn’t good for our industry – reduction in cost per bit comes from shrinks and reuse of capital, not only lower cost materials..

Kurt Carlson said that sub suppliers don’t think IC fabrication is the best industry – the IC industry wants more and more, yet wants to pay less and less.  It’s not worth it to us (good sub-suppliers leave because it’s too costly for the small volumes).

Jean Marc said they don’t want to duplicate development costs, if they don’t need to; they would rather use universities and share on things like toxicology.

Dave said it costs millions of dollars to test materials, like EUV.

Mansour Moinpour asked about collaboration on liquid particle, GCMS, and similar – can we have joint & consistent measurements across the industry?  James Entegris responded that end user need to be drivers.  Jean Marc suggested that maybe SEMI standards could drive a standard of industrial analytics.

The value of roadmaps was very different to the various participants, however the idea of regulatory alignment and a roadmap related to this was generally thought to be useful.

The question of cost and logistics … there are some materials that require shipping a lot of water, which adds cost.  Intel said that they are getting into more cost sensitive mobile market and they may be driven to this rather than exact materials copy in near future.  Tim said the Intel CEO is “hell bent” that Intel will make money in the mobile market.  “Intel will pull it off.”

Atomic Layer Etch now in Fab Evaluations

Monday, August 4th, 2014


By Ed Korczynski, Sr. Technical Editor

Atomic-Layer Etch (ALE) technology from Lam Research Corp. is now in beta-site evaluations with IC fabrication (fab) customers pursuing next generation manufacturing capabilities. So said Dr. David Hemker, Lam’s senior vice president and chief technical officer, in an exclusive interview with Solid State Technology and SemiMD during this year’s SEMICON West trade-show in San Francisco. Hemker discussed the reasons why ALE is now under evaluation as a critically enabling technology for next generation IC manufacturing, and forecast widespread adoption in the industry by 2017.

As detailed in the feature article “Moving atomic layer etch from lab to fab” in last December’s issue of Solid State Technology, ALE can be plasma enhanced with minor modifications to a continuous plasma etch chamber. The lab aspects including the science behind the process were discussed in a TechXPOT during SEMICON West this year in a presentation titled “Plasma Etch in the Era of Atomic Scale Fidelity” by Lam’s Thorsten Lill based on work done in collaboration with KU Leuven and imec. In that presentation, Lill reminded the attendees that the process has been explored in labs under a wide variety of names:  ALET, atomistic etching, digital etch, layer-by-layer etch, PALE, PE-ALE, single layer etch, and thin layer etching.

ALE can be seen as a logic counter-part to atomic-layer deposition (ALD), with the commonality that both processes become cost-effective when the amount of material being either added or removed are readily measured in atomic layers. It’s comforting that when the industry needs control to the atomic-level we are dealing with such tiny structures that ALD and ALE can provide acceptable throughputs. “By 2017, we see able 15% of the opportunity for us could be addressed by atomic processing,” projected Hemker.

However, ALE as promoted by Lam differs from ALD, because etch processes generally need directionality. “That’s where it diverges from ALD,” explained Hemker. “Using ions we get all the benefits of directionality and selectivity. Likewise, if we design the process correctly, we could theoretically have infinite selectivity with under layers.” Figure 1 shows a trench formed in single-crystal silicon using ALE, with vertical side-walls and a bottom surface smooth at the atomic scale. Such process capability is based on the pulsing of both energy and chemistry into the reaction chamber.

Fig. 1: (Left) Schematic cross-section of Atomic-Layer Etch (ALE) of silicon using a silicon-oxide top mask, (Middle) SEM cross-section of nominal 40-nm silicon trench, and (Right) TEM close-up of the silicon surface showing atomic-scale smoothness.

“We need to be able to pulse multiple things at the same time,” explained Hemker. “So we can absorb a reactant, and then switch over to a plasma. The breakthrough in this is being able to pulse everything correctly.” Labs have been doing this but on a timescale of minutes per atomic layer removed. Lam productized the principle to run on a time-scale of seconds on the 2300 Kiyo tool, which is the current leading-edge hardware for conductor etch from the company.

Pulsing of energy into a reaction chamber has been used in the company’s high aspect-ratio etch process for 3D NAND which runs on the 2300 Flex tool for dielectrics. In this process flow, vias through alternating layers of oxide and nitride in a stack must be etched at 40:1 aspect-ratio today, with 60:1 and even 100:1 aspect-ratio specifications from Samsung for device evaluations. “You see it coming in with pulsing the plasma, allowing us to get ions in and reactants out,” explained Hemker. So the ALE process can be seen as an extension of this pulsing plasma approach, with the extra sophistication of pulsing the chemical precursors into the chamber. “The trick is how to do it repeatably and reliably so that it’s production worthy,” reminded Hemker.

When the ALE precursor adsorbs as a single-layer on surfaces, the connection to the surface could be merely van der Waals forces, or depending upon the application could include some reaction with underlying atoms. “The process conditions have to tailored for flows and gases, but it does open up the possibility of using less expensive process gases. There’s no new gases needed,” declared Hemker. “The real message is not that this is just a new process, but this shares a common background with ALD in pulsing things and having sophisticated enough control of the process.”

Such commonalities would seemingly extend to some chamber hardware and the vacuum and effluent abatement systems, such that it would be very straightforward to cluster single-wafer processing chambers for ALD with ALE with plasma pre-treat and possibly even with annealing. Such a cluster would allow for sophisticated “dep/etch” recipes to be developed for atomic-scale device fabrication.

Fig. 2: Commonality in the need for ALD and ALE process technologies when IC device dimensions scale to atomic levels.

Figure 2 shows the comparison between ALD and ALE processes for a trench structure, and why both are needed when device geometries reach atomic-scales. When trench aspect ratios (AR) are ~1:1 continuous deposition and etch processes can be fairly easily developed to provide uniform results. However, as the AR increases, reaction byproducts tend to non-uniformly deposit on sidewalls and especially at the corners of structures. Eventually, the top of high AR trenches “pinch-off” to create an open in IC circuitry, even when slowing down continuous processes to allow more time for byproducts to escape reaction areas.

Lam expects ALE to be used on the leading-edge of IC manufacturing within a few years, with increasing applications as more critical layers in a device must be patterned to smaller than 22nm half-pitch. “It’s not that you can’t do some of these processes with continuous etch, but ALE really opens up the process window,” explained Hemker. Now is the time for ALE, since the minimum variability of continuous etching consumes more and more of the critical dimension with ever smaller feature sizes.

“If you look at ALD as the for-runner of this, it was first adopted for capacitor deposition in a batch process, then it migrated to single-wafer for high-k metal-gate formation where greater control was needed,” reminded Hemker. “It was used but somewhat niche, and now we’re seeing traction on ALD for many more applications such as quadruple-patterning. The spacers themselves have to be perfectly conformal, because any thickness variation will be a CD variation and it compounds with quadruple patterning.”

Control of pattern fidelity at the atomic-scale will be needed as the commercial IC fab industry integrates new materials for improved device functionalities. ALE and other technologies that can control processing of individual atomic layers should be used to pattern ICs for the indefinite future.