Posts Tagged ‘450mm wafers’
If you’ve ever gone to the grocery store and forgotten that one essential item, the question you face is how quickly can you run back in the store, get that necessary item, and be on your way home? Jeff Wilson of Mentor Graphics says that design teams often feel this way as they approach tapeout, only to be confronted with engineering change orders (ECOs). One major factor—the challenge of re-filling designs.
Phil Garrou provides his analysis of the presentations given at this year’s ISS meeting, focusing on those from IBM, Linx, imec, IHS and IBS. IBM’s Jon Casey, for example, notes that silicon performance advancement is becoming more challenging as scaling is becoming more costly and that we need to look beyond CMOS for cost effective technology solutions. He proposes integrated co-development of Silicon and packaging solutions to achieve new technologies with superior cost/performance metrics.
Pete Singer hasn’t toasted to cheap silicon for a while. Why? Because that mission has been accomplished. At SEMI’s ISS, Paul Farrar, manager of the G450C consortium put the industry progress over the last 40+ years in perspective. “1 Megabyte of memory in 1970 was $750,000. It was sold as an IBM add-on,” he said. “The great technology was made of 57mm wafers, five masking levels, and one level of metal. Today, it’s is less than a penny. That is a 100 million X improvement.”
SEMI Standards task forces are working on encouraging the industry to collaborate on key issues like the technical parameters for 450mm silicon wafers, physical interfaces, carriers, assembly and packaging. To date, SEMI has 13 task forces working on 450mm and has published nineteen (19) 450mm standards with 14 more in the pipeline. Here’s an update on the newly-published SEMI 450mm specifications as well as the other 450mm SEMI Standards.
Xilinx announced first customer shipment of the semiconductor industry’s first 20nm product manufactured by TSMC, and the PLD industry’s first 20nm All Programmable device. Xilinx UltraScale devices deliver an ASIC-class advantage with the industry’s only ASIC-class programmable architecture coupled with the Vivado ASIC-strength design suite and recently introduced UltraFast design methodology. The UltraScale devices enable 1.5X – 2X more realizable system-level performance and integration for customers, equivalent to a generation ahead of the competition.
SEMI also announced this that the deadline for presenters to submit an abstract for the 25th annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) is extended to November 28. ASMC, which takes place May 19-21, 2014 in Saratoga Springs, New York, will feature technical presentations of more than 80 peer-reviewed manuscripts covering critical process technologies and fab productivity.
FlipChip International announced the 100% acquisition of Millennium Microtech (Shanghai) – (MMS), a provider of fully integrated semiconductor packaging and testing services situated in the Zhang Jiang Hi- Tech Park, Pudong New Area, Shanghai, China. The MMS name will be changed to FlipChip International.
Tosoh Corporation announced today that Tosoh Group company Tosoh SMD, Inc., will implement a major expansion at its Grove City, Ohio, operations to develop, produce, and support physical vapor deposition (PVD) sputtering targets for the new 450mm wafer semiconductor market. The expansion is the biggest investment in Tosoh SMD’s history and is meant to position the company for the next generation products and technologies. It will include facilities, novel equipment and tools for manufacturing, and a sputter deposition tool for R&D and evaluation purposes. The first stage is slated to be ready by December 2014.
The readiness of EUV lithography is later than hoped, but appears to be on time for insertion into the 10nm node, which is slated to go into production in late 2015/early 2016. “I’m very convinced that very soon EUV will be ready to enter manufacturing,” said Luc Van den hove, president and CEO of imec, as reported by Pete Singer.
In an earlier blog, Veeco’s Tim Pratt, Senior Director, Marketing, said that indeed the next major roadblock to progress in the ongoing push to develop EUV lithography for volume production is the availability of defect-free mask blanks. He said that the tools in place today are not capable of producing mask blanks with the kind of yield necessary to support a ramp in EUV.
Meanwhile, results from early work into directed self-assembly (DSA) is quite promising. DSA could be used in conjunction with EUV for the 7nm node, scheduled to go into production in the 2017/2018 timeframe. Work at imec has shown that the polymers, with a hard mask on top, are robust enough to enable the etching of the patterns into silicon. “That’s fairly new data and very promising,” said An Steegen, senior vice president of process technology at imec.
EUV readiness also been the focus of several blogs by Vivek Bakshi. Earlier this year, he predicted that 50 W sources will be ready and working in NXE3300B sometime in 2014, corresponding to 43 WPH throughput. 100 W sources will be ready in 2015 or 2016 corresponding to 73 WPH. “The readiness of 250 W EUV sources cannot be safely predicted, unless we see 100 W sources ready and have identified the issues to ensure that they are no showstoppers. I am not convinced that present approaches can get to 500 W sources. It is easy to put them on roadmaps, but delivering them is another question,” he said.
Intel is far ahead of anyone else when it comes to putting 14nm devices into production. However, even Intel finds it challenging. Speaking on a quarterly call with analysts, newly elected CEO Brian Krzanich said 14nm rollout was “about a quarter behind our projections.” He said defects were the problem. “As a result, we are now planning to begin production in the first quarter of next year,” as Pete Singer reported.
Intel already has 3D finFETs in production, and FinFETs will likely become the logic technology of choice for the upcoming generations, with high mobility channels coming into play for the 7 and 5nm generation (2017 and 2019).
Brian Krzanich also said that Intel remained committed to the transition to 450mm wafers, saying: “We have not changed our timing. We are still targeting the second, latter half of this decade.” At Semicon Europa week, Paul Farrar, general manager of G450C, provided an update on the consortium’s progress in demonstrating 450mm process capability. He said 25 tools will be installed in the Albany cleanroom by the end of 2013, progress has been made on notchless wafers with a 1.5mm edge exclusion zone, they have seen significant progress in wafer quality, and automation and wafer carriers are working.
Phil Garrou reports on developments from Semicon Taiwan 2013 of interest to the IC packaging community. The Market Trends Forum chaired by Dr. Burn Lin of TSMC, included a report on DRAM Status (continued consolidation) by Charlie Chan of Morgan Stanley; Nicolas Gaudois Managing Director of UBS Investment Research looked at the “The End of the High End Smartphones Run,” and Dan Tracy of SEMI provided the Packaging Materials Outlook.
The Semiconductor Industry Association (SIA) announced that worldwide sales of semiconductors reached $25.87 billion for the month of August 2013, an increase of 6.4 percent compared to August 2012, marking the industry’s largest year-over-year growth since March 2011. Sales in the Americas increased by 23.3 percent compared to August 2012, while global sales in August were 1.3 percent higher than the previous month’s total of $25.53 billion.
ASML and imec announced the next major step in their extensive collaboration, with the launch of the Advanced Patterning Center. Together, they plan to tackle upcoming scaling challenges due to the chip industry’s move towards single digit nanometer dimensions. The Center will be located at the imec campus in Leuven and is expected to grow to close to 100 engineers over the next couple of years.
At the International Electron Devices Meeting (IEDM) in December, IBM researchers will describe a silicon nanowire (SiNW)-based MOSFET fabrication process that produced gate-all-around (GAA) SiNW devices at sizes compatible with the scaling needs of 10nm CMOS technology. They built a range of GAA SiNW MOSFETs, some of which featured a 30nm SiNW pitch with a gate pitch of 60 nm.
EV Group introduced the EVG 570R2R—the industry’s first roll-to-roll thermal nanoimprint lithography (NIL) tool. Jointly developed with the Industrial Consortium on Nanoimprint (ICON), helmed by A*STAR’s Institute of Materials Research and Engineering (IMRE), the EVG570R2R utilizes hot embossing to mass-produce films and surfaces with micro- and nanometer-scale structures for a variety of medical, consumer and industrial applications, including micro-fluidics, plastic electronics and photovoltaics.
Noel Technologies, a Silicon Valley specialty foundry offering process development and substrate fabrication, has increased its capabilities by offering 450mm wafer services. Noel now jumps into the R&D transition to the larger wafer size as toolmakers and customers prepare for the 450mm generation.
Customers in the Americas region (primarily the U.S.) are expected to account for nearly two-thirds of pure-play foundry sales in 2013, a slight increase from 2012. IC Insights forecasts that Americas region will represent 70 percent of TSMC’s sales, 67 percent of sales from GlobalFoundries, and 47 percent of sales from both UMC and SMIC (Figure 1). The Americas region is forecast to account for $22.4 billion of the $36.3 billion worldwide pure-play foundry market in 2013, which is up from $19.2 billion (61 percent) of the total $31.7 billion pure-play foundry market in 2012.
Paradoxically, the merger of equipment manufacturers AMAT and TEL may shrink the Electronic Design Automation (EDA) tool market while improving IP security.
In the last several days, much has been written about the proposed merger of Applied Materials (AMAT) and Tokyo Electron (TEL). Desired by both, this merger would create a company worth $29B that would be the largest semiconductor equipment company in the world by sales. In comparison, the EDA tool market is roughly valued at $1.1B.
This merger of capital equipment giants represents an ongoing consolidation of the semiconductor supply chain, from chip/component developers through the IDM/foundries and manufacturing space. One reason for this consolidation is the increasingly high costs of making chips smaller and smaller – e.g., at the leading edge process nodes.
At first glance, it would appear that the merger will have little impact on the world of semiconductor intellectual property (IP). Still, one of the stated goals of the merged companies is to extract costs, “from all layers of the supply chain,” according to a recent report from Canaccord Genuity’s analyst Josh Baribeau (see, “Size Matters: Our First Take on AMAT’s Proposed Merger with Tel.”)
While admittedly far down on the supply chain relative to capital equipment, the Electronic Design Automation (EDA) tool market – heavy dependent on design and verification IP – might feel the effects of this merger in several ways.
First, equipment manufactures use EDA tools and related processes to qualify new manufacturing systems. For example, last year Applied Materials supplied critical film properties (new materials) and device characterization data from its advanced process systems to Synopsys. This allowed the EDA vendor to create more accurate chip design and verification models.
Such new materials and processes are necessary to keep Moore’s Law on track, in contrast to the ever increasing lithographic costs at lower and lower nodes. Several new technologies and process node shrinks are also driving up the cost of manufacturing leading edge chips – such things as 3D NAND devices, 450mm wafers, finFET structures, stacked dies and more.
Still, the cost of EDA tools are low in relationship to other costs. According to long-time EDA analyst Gary Smith, the cost of EDA tools is analogous to lunch money. The real costs in SoC development are related to the cost of engineers to do the design. Greater level of chip design-verification tool automation will reduce these costs, as will, “the reuse of software, the reuse of verifiable design IP, and by reducing SoC core blocks below the typical five blocks.” (see, “Gary Smith’s Sunday Night, Pre-DAC Forecast”)
It may well be that consolidation by the equipment manufactures will result in accelerated consolidation of the lower part of the semiconductor supply chain, e.g., EDA tool vendors. Judging from the furry of acquisitions in the EDA community over the last several years, this scenario is hardly surprising.
On the other hand, this merger of equipment giants might be a good thing for the development of soft IP standards. As Warren Savage pointed out a few months ago (see, “Long Standards, Twinkie IP, Macro Trends, and Patent Trolls“), the semiconductor equipment companies need to approve any IP design standards since it will be their systems that must read the soft IP.
Consolidation of the equipment market should mean fewer companies that need to approve any such standards, thus (in theory) hastening the approval process.
Will the end result of the AMAT and TEL merger mean further consolidation of EDA tools and hence the IP markets? Will the merger lead to greater IP protection at the lower process nodes? The answer will probably be revealed in the next installment of Moore’s Law, i.e., the next process node advancement.
By Pete Singer
The switch to 450mm will likely be the largest, most expensive retooling the semiconductor industry has ever experienced. 450mm fabs, which will give an unbeatable competitive advantage to the largest semiconductor manufacturers, are likely to cost $10 billion and come on-line in 2017, with production ramp in 2018.
Unprecedented technical challenges still need to be overcome, but work is well underway at an R&D center in upstate New York, at the Global 450mm Consortium, G450C. Paul Farrar Jr., the G450C General Manager, recently spoke on the current status of activities, key milestones and schedules during a webcast produced by Solid State Technology.
“At this point, we have contracts with 12 major suppliers, and we have tools that are being delivered to the consortium starting in April and continuing through 2015,” Farrar said.
The G450C team now has over 60 engineers and assignees from the member companies. The goal is to have more than 150 engineers by 2014, with approximately 60 supplier engineers on site. “2013 and early 2014 will be about getting tools installed and up and running. Then the integration and unit process scientists will continue from there,” Farrar said.
Farrar said G450C has commitments for 112 process levels. For 45 processes, two suppliers are developing products (which equates to 90 process levels). A few have three suppliers, and about 10 process steps have one supplier. Farrar said that he sees 300mm and 450mm development continuing simultaneously. “We certainly know that for the next six or seven years, the industry will be developing and bringing capability to both 300mm and 450mm. A key goal here is to make sure that we do not slow down the scaling required for Moore’s Law to go from say 20nm to 15 to 12 to 10, etc. versus the cost reduction you get from going to a larger wafer size. We need to both of these things simultaneously as an industry,” he said. “A rough target is to get to 10nm, and then in 2016 we want to be ready for IC makers to make their decisions on when they will ramp to 450mm.”
By Pete Singer
One of the highlights of SEMI’s Industry Strategy Symposium held in January in Half Moon Bay, California was the first public presentation of a fully patterned 450mm silicon wafer.
Intel’s Robert E. Bruck, corporate vice president and general manager of Technology Manufacturing Engineering asked Mario Abravanel, Intel 450mm Equipment Program Manager, to join him on stage. Abravanel appeared from behind the stage, carrying the wafer with gloved hands. “It’s real,” Bruck said, noting that the wafer was patterned with 26nm features using nano imprint lithography. Bruck singled out wafer-supplier SUMCO, Dai Nippon Printing for partnering in the mask area, and Molecular Imprints for imprint technology. “It shows that a true partnership can move this thing forward,” he said. Bruck said that Intel will be producing thousands of 450mm wafers in the next few quarters for their equipment partners to use in their own equipment development.
Bruck, during his presentation, noted that fewer companies are capable of delivering Moore’s Law — and fewer capable of 450mm production. He showed that about 20 semiconductor companies have the $3-5 billion revenue “threshold” (measured in 2011 dollars) to build a 200mm fab. Only nine have revenue, in the $9-12 billion range, which is the threshold for a 300mm fab (those being Intel, Samsung, TSMC, Toshiba, TI, Renesas, ST Micro, Qualcomm and Hynix). “In 300mm configurations, there’s a much smaller group that can afford a reasonable capital cost as a percentage of revenue,” Bruck said. “If you extend this 300mm model out a few more years, anticipating the next few nodes that come, the list of participants who can afford to build these factories gets even smaller. Somewhere beyond 2015 will be a 450 number which suggests even further concentration.”
The exact timing of 450mm production was explored at ISS in a panel session hosted by Alix Partners. Chris Danely, Managing Director, Semiconductor Equity Research, JP Morgan, said: “From the Wall Street perspective, the triumvirate of Intel, Samsung and TSMC is telling us 2017. 2018 is when it starts to ramp.”
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.