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Posts Tagged ‘3D NAND’

What is Your China Strategy?

Wednesday, September 7th, 2016

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By Dave Lammers, Contributing Editor

Equipment vendors have a lot on their plates now, with memory customers pushing 3D NAND, foundries advancing to the 7 nm node, and 200mm fabs clamoring to come up with hard-to-find tools.

China, which has renewed its investments in displays, packaging, and both 200mm and 300mm front-end fab capacity, is another challenge.

“All the managers in my company are scrambling to adjust their budgets so they can support China. I can tell you people are booking lots of flights to Shanghai,” said one engineer at a major equipment supplier.

Bill McClean, president of IC Insights (Scottsdale, AZ), said China is fast becoming a center for 3D NAND production, as several companies expand production in China. Intel is converting its Dalian, China fab partly to 3D NAND, and Toshiba might very well make a deal in China to build a 3D NAND fab there, he said.

“China could be the 3D NAND capital of the world,” McClean said at The ConFab conference in Las Vegas. While the U.S. government limits exports of leading-edge technologies on national security concerns, 3D NAND relies more on overlay and etch techniques at relaxed (40nm) design rules, he noted.

“Since the 3D NAND makers are not pushing feature sizes, it doesn’t raise red flags like if Chinese companies wanted FinFET technology. That is when the alarms go off,” McClean said.

However, McClean said the 3D NAND market is not immune to the oversupply issues that now face the DRAM makers. “I’ve seen this rodeo before,” McClean said.

China’s domestic IC market is slightly more than $100 billion, McClean said, while chip production in China was about $13 billion last year, representing just under 5 percent of worldwide production (Figure 1).

Figure 1. Source: IC Insights.

The difference between consumption and domestic production, referred to as the delta, is made up by imports. “This 13 percent (from domestic suppliers) drives the Chinese government crazy. Yes, they will close that gap a little bit, but not to the extent that they think,” McClean told The ConFab audience in mid-June.

Robert Maire, who consulted for SMIC on its initial public offering in the United States, spoke at length about China at the SEMI Advanced Semiconductor Manufacturing Conference (ASMC) in Saratoga Springs, N.Y. Amid the mergers and acquisition frenzy of last year, China managed to pull off the acquisitions of CMOS image sensor vendor Omnivision, memory maker ISSI, the RF business of NXP, Pericom Semiconductor, and Mattson Technology. (McClean said he believes that if the Omnivision acquisition were attempted in today’s more China-wary environment that Washington would block the deal).

Maire, principal at Semiconductor Advisors (New York), said China is far behind in its domestic semiconductor production equipment business. “If China has 14nm production capacity, but buys all of its equipment from abroad, it doesn’t really help them that much. China is getting started in equipment, but it has a lot of catching up to do.”

Scott Foster, a partner in market intelligence firm TAP Japan (Tokyo), said China must have an international scope in the equipment sector if it hopes to compete with the likes of Applied, Lam, and other well-established vendors. A few of Japan’s equipment suppliers are succeeding while operating in relatively narrow niches, but overall, competing globally is a challenge for mid-sized Japanese equipment companies. “If this is what is happening to Japanese equipment vendors, what chance do Chinese companies have?” Foster said.

Packaging may prove to be key

Skeptics of China’s prospects might take a long look at China’s success in packaging, an area where China is succeeding, in part by acquisitions of Asia-based companies, notably STATS ChipPAC (Singapore), which was acquired by Jiangsu Changjiang Electronics Technology Co. (JCET) last year. Separately, SMIC and JCET formed a joint venture to focus on chip scale packaging, wafer bumping, and fan-out wafer level packaging. The packaging joint venture is located 90 minutes from Shanghai, said Sonny Hui, senior vice president of worldwide marketing at SMIC.

Jim Walker, the packaging analyst at market research firm Gartner, said China-based packaging is now valued at nearly half (43 percent) of all worldwide packaging value by IDMs and OSATs. While the packaging industry overall is dealing with price pressures, the advent of wafer level packaging, and other forms of multi-chip integration, bodes well for the higher end of the back-end industry.

“As the semiconductor industry matures and Moore’s Law scaling slows, multi-chip integration via packaging is providing system vendors with a faster time-to-market, and a lower-cost means, of solving system-level challenges,” Walker said.

Packaging multiple chips in a module is likely to play a key role in the Internet of Things (IoT) markets, Walker said. Automotive, medical, home, and consumer solutions are all “heavily reliant on packaging,” he said.

Sam Wang, a Gartner analyst who focuses on foundries, pointed out at Semicon West that China’s semiconductor industry faces continued challenges in a hotly contested foundry market. Few China-based foundries have enjoyed the strong growth that SMIC has demonstrated, he said. (SMIC has been “running at very high utilizations, and we are working very hard to solve the problem,” said SMIC’s Hui.)

While SMIC has enjoyed double-digit growth for several years, the five second-tier Chinese foundries – — Shanghai Huahong Grace, CSMC, HuaLi, XMC, and ASMC — saw declining revenues year-over-year in 2015. Overall, China-based foundries accounted for just 7.8 percent of total worldwide foundry capacity last year, and the overall growth rate by Chinese foundries “is way below the expectations of the Chinese government,” Wang said.

China-based companies are focusing partly on MEMS and other devices made on 200mm wafers, including analog, sensors, and power. SMIC’s Hui said “most of our customers don’t see much benefit to migrate to 12-inch. 200mm still has a lot of potential; just consider the hundreds of products still made on 180nm technology, which was developed 20 years ago. Many customers still see that as a sweet spot.”

Foster, who has three decades of tech-watching experience from his base in Tokyo, said the 200mm wafer fabs being built in China will make products that “do not need the gigantic scale” required of Intel, TSMC, Samsung and Toshiba. Figure 2, courtesy of SEMI, shows the seventeen 200mm wafer fabs/lines that are expected begin operation in 2015 to 2019. Six of the seventeen will be in China.

Figure 2. Source: SEMI

“After decades of trying, China has found a market-based strategy: building scale and experience from the bottom up. In the long run, this is likely to be far more effective than going out to buy foreign companies,” Foster said.

Display is another area China is counting on. In an Aug. 18 conference call following a strong quarter, Applied Materials chief financial officer Bob Halliday told analysts: “In display, we recorded record orders of $803 million with more than half coming from projects in China.”

The Applied CFO also said, “Just listening to the Chinese government, they’re in this for a long-term and their interest in investing in the semiconductor industry is probably only going to increase.”

Kateeva turns to China funds

China is often lumped together with other Asian nations as a country that has a government-led, me-too, follower mentality. But increasingly, China is either proving innovative itself, or able to quickly adopt innovations from the West.

At the Innovation Forum at Semicon West, Conor Madigan, co-founder of ink jet printer startup Kateeva (Newark, Calif.) spoke about the readiness of Chinese venture capital funds to step in where Silicon Valley-based VCs were overly hesitant. China proved a more receptive place to raise money than the United States, though the early establishment of the M.I.T. spinout did come from U.S. based sources.

After its initial development effort, Kateeva figured it needed more than $100 million to accomplish its goals. After making the rounds to raise funds in the United States without success, Kateeva turned to China, where five different funds eventually became investors.

Asked why Chinese investors were willing to back Kateeva when funds in the United States and other Asian countries were reluctant, Madigan pointed to a confluence of factors.

The Chinese government had identified OLED displays as a focus of its Five Year Plan. The follow-on economic plan further identified inkjet technology as a critical technology. Investors in China favor companies which can provide the equipment for products, such as OLEDs, which have the government’s blessing and financial support. That government support reduced the investment risks in ways that are not readily seen in Japan or the United States, he said.

Madigan had studied OLEDs as an undergraduate at Princeton University, and then studied under an M.I.T. professor who had developed ink jet technology for large formats.

Though an early goal was to use large-format inkjet to deposit the RGB materials in OLEDs, the Kateeva team learned that its YieldJet system could be adapted to solve a more urgent problem: thin film encapsulation (TFE). It “pivoted” on the advice of an early customer, which fortunately already had developed the “ink” which under UV light would form a uniform encapsulation layer for the large OLED substrates required for TVs and other large display applications.

Two display companies in China identified Kateeva as a strategic partner, which allowed Kateeva to raise money from private Chinese VC funds, rather than taking money from regional government funds which might have asked Kateeva to locate its manufacturing operations in their local area.

Madigan also pointed to the tendency of U.S.-based venture capital funds to favor software companies over manufacturing-focused opportunities. As VCs make money in software-related startups, the funds gradually have more partners and investors which favor software because that is what they are familiar with.

VC fund managers with backgrounds in software “want to invest in the space that they understand. In the United States, that often means software, because you pick companies in the space that you understand.”

3D-NAND Deposition and Etch Integration

Thursday, September 1st, 2016

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By Ed Korczynski, Sr. Technical Editor

3D-NAND chips are in production or pilot-line manufacturing at all major memory manufacturers, and they are expected to rapidly replace most 2D-NAND chips in most applications due to lower costs and greater reliability. Unlike 2D-NAND which was enabled by lithography, 3D-NAND is deposition and etch enabled. “With 3D-NAND you’re talking about 40nm devices, while the most advanced 2D-NAND is running out of steam due to the limited countable number of stored electrons-per-cell, and in terms of the repeatability due to parasitics between adjacent cells,” reminded Harmeet Singh, corporate vice president of Lam Research in an exclusive interview with SemiMD to discuss the company’s presentation at the Flash Memory Summit 2016.

“We’re in an era where deposition and etch uniquely define the customer roadmap,” said Singh,“and we are the leading supplier in 3D-NAND deposition and etch.” Though each NAND manufacturer has different terminology for their unique 3D variant, from a manufacturing process integration perspective they all share similar challenges in the following simplified process sequences:

1)    Deposition of 32-64 pairs of blanket “mold stack” thin-films,

2)    Word-line hole etch through all layers and selective fill of NAND cell materials, and

3)    Formation of “staircase” contacts to each cell layer.

Each of these unique process modules is needed to form the 3D arrays of NVM cells.

For the “mold stack” deposition of blanket alternating layers, it is vital for the blanket PECVD to be defect-free since any defects are mirrored and magnified in upper-layers. All layers must also be stress-free since the stress in each deposited layer accumulates as strain in the underlying silicon wafer, and with over 32 layers the additive strain can easily warp wafers so much that lithographic overlay mismatch induces significant yield loss. Controlled-stress backside thin-film depositions can also be used to balance the stress of front-side films.

Hole Etch

“The difficult etch of the hole, the materials are different so the challenges is different,” commented Singh about the different types of 3D-NAND now being manufactured by leading fabs. “During this conference, one of our customer presented that they do not see the hole diameters shrinking, so at this point it appears to us that shrinking hole diameters will not happen until after the stacking in z-dimension reaches some limit.”

Tri-Layer Resist (TLR) stacks for the hole patterning allow for the amorphous carbon hardmask material to be tuned for maximum etch resistance without having to compromise the resolution of the photo-active layer needed for patterning. Carbon mask is over 3 microns thick and carbon-etching is usually responsive to temperature, so Lam’s latest wafer-chuck for etching features >100 temperature control zones. “This is an example of where Lam is using it’s processes expertise to optimize both the hardmask etch as well as the actual hole etch,” explained Singh.

Staircase Etch

The Figure shows a simplified cross-sectional schematic of how the unique “staircase” wordline contacts are cost-effectively manufactured. The established process of record (POR) for forming the “stairs” uses a single mask exposure of thick KrF photoresist—at 248nm wavelength—to etch 8 sets of stairs controlled by a precise resist trim. The trimming step controls the location of the steps such that they align with the contact mask, and so must be tightly controlled to minimize any misalignment yield loss.

A) Simplified cross-sectional schematic of the staircase etch for 3D-NAND contacts using thick photoresist, B) which allows for controlled resist trimming to expose the next “stair” such that C) successive trimming creates 8-16 steps from a single initial photomask exposure. (Source: Ed Korczynski)

Lam is working on ways to tighten the trimming etch uniformity such that 16 sets of stairs can be repeatably etched from a single KrF mask exposure. Halving the relative rate of vertical etch to lateral etch of the KrF resist allows for the same resist thickness to be used for double the number of etches, saving lithography cost. “We see an amazing future ahead because we are just at the beginning of this technology,” commented Singh.

—E.K.

Fab Facilities Data and Defectivity

Monday, August 1st, 2016

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By Ed Korczynski, Sr. Technical Editor

In-the-know attendees at SEMICON West at a Thursday morning working breakfast heard from executives representing the world’s leading memory fabs discuss manufacturing challenges at the 4th annual Entegris Yield Forum. Among the excellent presenters was Norm Armour, managing director worldwide facilities and corporate EHSS of Micron. Armour has been responsible for some of the most famous fabs in the world, including the Malta, New York logic fab of GlobalFoundries, and AMD’s Fab25 in Austin, Texas. He discussed how facilities systems effect yield and parametric control in the fab.

Just recently, his organization within Micron broke records working with M&W on the new flagship Fab 10X in Singapore—now running 3D-NAND—by going from ground-breaking to first-tool-in in less than 12 months, followed by over 400 tools installed in 3 months. “The devil is in the details across the board, especially for 20nm and below,” declared Armour. “Fabs are delicate ecosystems. I’ll give a few examples from a high-volume fab of things that you would never expect to see, of component-level failures that caused major yield crashes.”

Ultra-Pure Water (UPW)

Ultra-Pure Water (UPW) is critical for IC fab processes including cleaning, etching, CMP, and immersion lithography, and contamination specs are now at the part-per-billion (ppb) or part-per-trillion (ppt) levels. Use of online monitoring is mandatory to mitigate risk of contamination. International Technology Roadmap for Semiconductors (ITRS) guidelines for UPW quality (minimum acceptable standard) include the following critical parameters:

  • Resistivity @ 25C >18.0 Mohm-cm,
  • TOC <1.0 ppb,
  • Particles/ml < 0.3 @ 0.05 um, and
  • Bacteria by culture 1000 ml <1.

In one case associated with a gate cleaning tool, elevated levels of zinc were detected with lots that had passed through one particular tool for a variation on a classic SC1 wet clean. High-purity chemistries were eliminated as sources based on analytical testing, so the root-cause analysis shifted to to the UPW system as a possible source. Then statistical analysis could show a positive correlation between UPW supply lines equipped with pressure regulators and the zinc exposure. The pressure regulator vendor confirmed use of zinc-oxide and zinc-stearate as part of the assembly process of the pressure regulator. “It was really a curing agent for an elastomer diaphragm that caused the contamination of multiple lots,” confided Armour.

UPW pressure regulators are just one of many components used in facilities builds that can significantly degrade fab yield. It is critical to implement a rigorous component testing and qualification process prior to component installation and widespread use. “Don’t take anything for granted,” advised Armour. “Things like UPW regulators have a first-order impact upon yield and they need to be characterized carefully, especially during new fab construction and fit up.”

Photoresist filtration

Photoresist filtration has always been important to ensure high yield in manufacturing, but it has become ultra-critical for lithography at the 20nm node and below. Dependable filtration is particularly important because industry lacks in-line monitoring technology capable of detecting particles in the range below ~40nm.

Micron tried using filters with 50nm pore diameters for a 20nm node process…and saw excessive yield losses along with extreme yield variability. “We characterized pressure-drop as a function of flow-rate, and looked at various filter performances for both 20nm and 40nm particles,” explained Armour. “We implemented a new filter, and lo and behold saw a step function increase in our yields. Defect densities dropped dramatically.” Tracking the yields over time showed that the variability was significantly reduced around the higher yield-entitlement level.

Airborne Molecular Contamination (AMC)

Airborne Molecular Contamination (AMC) is ‘public enemy number one’ in 20nm-node and below fabs around the world. “In one case there were forrest fires in Sumatra and the smoke was going into the atmosphere and actually went into our air intakes in a high volume fab in Taiwan thousands of miles away, and we saw a spike in hydrogen-sulfide,” confided Armour. “It increased our copper CMP defects, due to copper migration. After we installed higher-quality AMC filters for the make-up air units we saw dramatic improvement in copper defects. So what is most important is that you have real-time on-line monitoring of AMC levels.”

Building collaborative relationships with vendors is critical for troubleshooting component issues and improving component quality. “Partnering with suppliers like Entegris is absolutely essential,” continued Armour. “On AMCs for example, we have had a very close partnership that developed out of a team working together at our Inotera fab in Taiwan. There are thousands of important technologies that we need to leverage now to guarantee high yields in leading-node fabs.” The Figure shows just some of the AMCs that must be monitored in real-time.

Big Data

The only way to manage all of this complexity is with “Big Data” and in addition to primary process parameter that must be tracked there are many essential facilities inputs to analytics:

  • Environmental Parameters – temperature, humidity, pressure, particle count, AMCs, etc.
  • Equipment Parameters – run state, motor current, vibration, valve position, etc.
  • Effluent Parameters – cooling water, vacuum, UPW, chemicals, slurries, gases, etc.

“Conventional wisdom is that process tools create 90% of your defect density loss, but that’s changing toward facilities now,” said Armour. “So why not apply the same methodologies within facilities that we do in the fab?” SPC is after-the-fact reactive, while APC is real-time fault detection on input variables, including such parameters as vibration or flow-rate of a pump.

“Never enough data,” enthused Armour. “In terms of monitoring input variables, we do this through the PLCs and basically use SCADA to do the fault-detection interdiction on the critical input variables. This has been proven to be highly effective, providing a lot of protection, and letting me sleep better at night.”

Micron also uses these data to provide site-to-site comparisons. “We basically drive our laggard sites to meet our world-class sites in terms of reducing variation on facility input variables,” explained Armour. “We’re improving our forecasting as a result of this capability, and ultimately protecting our fab yields. Again, the last thing a fab manager wants to see is facilities causing yield loss and variation.”

—E.K.

Slowdown in Equipment Business Hits Applied’s Quarterly Results

Friday, February 19th, 2016

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By Jeff Dorsch, Contributing Editor

Applied Materials reported net income of $286 million on revenue of $2.257 billion for the fiscal first quarter ended January 31, compared with net income of $348 million on revenue of $2.359 billion in the same quarter of a year ago.  Orders in Q1 were $2.275 billion, flat with $2.273 billion a year earlier.

Applied said foundry customers accounted for 38 percent of orders in the first quarter of fiscal 2016, while DRAM manufacturers represented 29 percent, flash memory suppliers 22 percent, and logic/others 11 percent. One year ago, orders were evenly split between foundry and DRAM customers, at 34 percent for each segment.

The 4 percent reduction in Q1 revenue, year over year, reflects the current softness in the semiconductor equipment business. SEMI’s book-to-bill ratio for North American equipment suppliers has been below parity for the last three months, with a preliminary figure of 0.99 in January, subject to revision.

“As the market moves into the sweet spot for Applied’s materials engineering technology, we see strong demand for our semiconductor, display and service businesses,” Gary Dickerson, Applied’s president and chief executive officer, said in a statement. “We are maintaining a positive outlook for 2016 as our customers make strategic, inflection-driven investments that play to our strengths.”

Dickerson told analysts Wednesday, “We are growing beyond semiconductor.” Applied’s display business is being driven by the industry’s move to organic light-emitting diode displays, he said.

An OLED fabrication facility represents three times the potential spending on equipment for an amorphous silicon liquid crystal display plant, according to Dickerson. “I am confident about our growth,” he said. The company’s etch and chemical vapor deposition businesses are “making significant gains,” the CEO added.

While there are “global economic risks” in 2016, similar to those in 2015, 10-nanometer chips and 3D NAND flash memory devices are creating demand for production equipment, along with “increased spending in China” by domestic and foreign companies, Dickerson said. “There is a fierce battle for leadership in these new device categories,” he commented.

Capital spending at the silicon foundries in 2016 will be at “levels more or less the same as last year,” Dickerson added. Their capital expenditures for 10nm ICs is expected to pick up in the second half of calendar 2016, he predicted.

NAND flash investment will be up 25 percent from 2015, particularly for 3D NAND, Dickerson said. The “heavy DRAM investment” of 2015 will cool off this year, falling about 20 percent in 2016, he added.  Logic spending will be “relatively flat, year over year,” he said.

Bob Halliday, the company’s senior vice president and chief financial officer, forecast net income in the fiscal second quarter would be in the range of 30 to 34 cents per share, compared with 25 cents per share in Q1 and 28 cents per share in the first quarter of fiscal 2015. Thomson Reuters I/B/E/S said analysts were expecting an average of 26 cents per share for Q2.

Worldwide spending on wafer fabrication equipment will be flat in 2016, compared with 2015, Halliday said. “We expect our share to increase,” he added.

The Applied Global Services business is in its third year of growth and display is in its fourth year of growth, the CFO noted.

Blog review September 8, 2014

Monday, September 8th, 2014

Jeff Wilson of Mentor Graphics writes that, in IC design, we’re currently seeing the makings of a perfect storm when it comes to the growing complexity of fill. The driving factors contributing to the growth of this storm are the shrinking feature sizes and spacing requirements between fill shapes, new manufacturing processes that use fill to meet uniformity requirements, and larger design sizes that require more fill.

Is 3D NAND a Disruptive Technology for Flash Storage? Absolutely! That’s the view of Dr. Er-Xuan Ping of Applied Materials. He said a panel at the 2014 Flash Memory Summit agreed that 3D NAND will be the most viable storage technology in the years to come, although our opinions were mixed on when that disruption would be evident.

Phil Garrou takes a look at some of the “Fan Out” papers that were presented at the 2014 ECTC, focusing on STATSChipPAC (SCP) and the totally encapsulated WLP, Siliconware (SPIL) panel fan-out packaging (P-FO), Nanium’s eWLB Dielectric Selection, and an electronics contact lens for diabetics from Google/Novartis.

Ed Koczynski says he now knows how wafers feel when moving through a fab. Leti in Grenoble, France does so much technology integration that in 2010 it opened a custom-developed people-mover to integrate cleanrooms (“Salles Blanches” in French) it calls a Liaison Blanc-Blanc (LBB) so workers can remain in bunny-suits while moving batches of wafers between buildings.

Handel Jones of IBS provides a study titled “How FD-SOI will Enable Innovation and Growth in Mobile Platform Sales” that concludes that the benefits of FD-SOI are overwhelming for mobile platforms through Q4/2017 based on a number of key metrics.

Gabe Moretti of Chip Design blogs that a grown industry looks at the future, not just to short term income.  EDA is demonstrating to be such an industry with significant participation by its members to foster and support the education of its future developers and users through educational licenses and other projects that foster education.

Atomic Layer Etch now in Fab Evaluations

Monday, August 4th, 2014

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By Ed Korczynski, Sr. Technical Editor

Atomic-Layer Etch (ALE) technology from Lam Research Corp. is now in beta-site evaluations with IC fabrication (fab) customers pursuing next generation manufacturing capabilities. So said Dr. David Hemker, Lam’s senior vice president and chief technical officer, in an exclusive interview with Solid State Technology and SemiMD during this year’s SEMICON West trade-show in San Francisco. Hemker discussed the reasons why ALE is now under evaluation as a critically enabling technology for next generation IC manufacturing, and forecast widespread adoption in the industry by 2017.

As detailed in the feature article “Moving atomic layer etch from lab to fab” in last December’s issue of Solid State Technology, ALE can be plasma enhanced with minor modifications to a continuous plasma etch chamber. The lab aspects including the science behind the process were discussed in a TechXPOT during SEMICON West this year in a presentation titled “Plasma Etch in the Era of Atomic Scale Fidelity” by Lam’s Thorsten Lill based on work done in collaboration with KU Leuven and imec. In that presentation, Lill reminded the attendees that the process has been explored in labs under a wide variety of names:  ALET, atomistic etching, digital etch, layer-by-layer etch, PALE, PE-ALE, single layer etch, and thin layer etching.

ALE can be seen as a logic counter-part to atomic-layer deposition (ALD), with the commonality that both processes become cost-effective when the amount of material being either added or removed are readily measured in atomic layers. It’s comforting that when the industry needs control to the atomic-level we are dealing with such tiny structures that ALD and ALE can provide acceptable throughputs. “By 2017, we see able 15% of the opportunity for us could be addressed by atomic processing,” projected Hemker.

However, ALE as promoted by Lam differs from ALD, because etch processes generally need directionality. “That’s where it diverges from ALD,” explained Hemker. “Using ions we get all the benefits of directionality and selectivity. Likewise, if we design the process correctly, we could theoretically have infinite selectivity with under layers.” Figure 1 shows a trench formed in single-crystal silicon using ALE, with vertical side-walls and a bottom surface smooth at the atomic scale. Such process capability is based on the pulsing of both energy and chemistry into the reaction chamber.

Fig. 1: (Left) Schematic cross-section of Atomic-Layer Etch (ALE) of silicon using a silicon-oxide top mask, (Middle) SEM cross-section of nominal 40-nm silicon trench, and (Right) TEM close-up of the silicon surface showing atomic-scale smoothness.

“We need to be able to pulse multiple things at the same time,” explained Hemker. “So we can absorb a reactant, and then switch over to a plasma. The breakthrough in this is being able to pulse everything correctly.” Labs have been doing this but on a timescale of minutes per atomic layer removed. Lam productized the principle to run on a time-scale of seconds on the 2300 Kiyo tool, which is the current leading-edge hardware for conductor etch from the company.

Pulsing of energy into a reaction chamber has been used in the company’s high aspect-ratio etch process for 3D NAND which runs on the 2300 Flex tool for dielectrics. In this process flow, vias through alternating layers of oxide and nitride in a stack must be etched at 40:1 aspect-ratio today, with 60:1 and even 100:1 aspect-ratio specifications from Samsung for device evaluations. “You see it coming in with pulsing the plasma, allowing us to get ions in and reactants out,” explained Hemker. So the ALE process can be seen as an extension of this pulsing plasma approach, with the extra sophistication of pulsing the chemical precursors into the chamber. “The trick is how to do it repeatably and reliably so that it’s production worthy,” reminded Hemker.

When the ALE precursor adsorbs as a single-layer on surfaces, the connection to the surface could be merely van der Waals forces, or depending upon the application could include some reaction with underlying atoms. “The process conditions have to tailored for flows and gases, but it does open up the possibility of using less expensive process gases. There’s no new gases needed,” declared Hemker. “The real message is not that this is just a new process, but this shares a common background with ALD in pulsing things and having sophisticated enough control of the process.”

Such commonalities would seemingly extend to some chamber hardware and the vacuum and effluent abatement systems, such that it would be very straightforward to cluster single-wafer processing chambers for ALD with ALE with plasma pre-treat and possibly even with annealing. Such a cluster would allow for sophisticated “dep/etch” recipes to be developed for atomic-scale device fabrication.

Fig. 2: Commonality in the need for ALD and ALE process technologies when IC device dimensions scale to atomic levels.

Figure 2 shows the comparison between ALD and ALE processes for a trench structure, and why both are needed when device geometries reach atomic-scales. When trench aspect ratios (AR) are ~1:1 continuous deposition and etch processes can be fairly easily developed to provide uniform results. However, as the AR increases, reaction byproducts tend to non-uniformly deposit on sidewalls and especially at the corners of structures. Eventually, the top of high AR trenches “pinch-off” to create an open in IC circuitry, even when slowing down continuous processes to allow more time for byproducts to escape reaction areas.

Lam expects ALE to be used on the leading-edge of IC manufacturing within a few years, with increasing applications as more critical layers in a device must be patterned to smaller than 22nm half-pitch. “It’s not that you can’t do some of these processes with continuous etch, but ALE really opens up the process window,” explained Hemker. Now is the time for ALE, since the minimum variability of continuous etching consumes more and more of the critical dimension with ever smaller feature sizes.

“If you look at ALD as the for-runner of this, it was first adopted for capacitor deposition in a batch process, then it migrated to single-wafer for high-k metal-gate formation where greater control was needed,” reminded Hemker. “It was used but somewhat niche, and now we’re seeing traction on ALD for many more applications such as quadruple-patterning. The spacers themselves have to be perfectly conformal, because any thickness variation will be a CD variation and it compounds with quadruple patterning.”

Control of pattern fidelity at the atomic-scale will be needed as the commercial IC fab industry integrates new materials for improved device functionalities. ALE and other technologies that can control processing of individual atomic layers should be used to pattern ICs for the indefinite future.

Experts At The Table: Commercial potential and production challenges for 3D NAND memory technology

Thursday, February 6th, 2014

The last six months have seen several developments concerning 3D memory concepts moving into production, from companies such as Samsung, Micron, Toshiba and Sandisk. What follows are excerpts from a roundtable discussion with SemiMD, Samsung Electronics (SE) in South Korea, which has begun production of its proprietary 3D NAND technology, Bradley Howard, Vice President of Advanced Technology Group, Etch Business Unit, at Applied Materials and Jim Handy from Objective Analysis, which specialises in coverage of the memory industry.

SemiMD: Where does 3D NAND fit into the long-term roadmap for memory technology and is there one technology most likely to dominate?

SE: We successfully came out with the industry’s first 3D NAND (V-NAND) in August 2013, which offers 128 GB on a chip and vertically stacks cell layers that make use of charge trap flash (CTF) technology. The V-NAND has already been used in 960 GB solid state drives (SSDs) for server and enterprise applications.

The V-NAND technology is expected to replace planar NAND market gradually, starting from the high-end enterprise market. We will continue to come up with more advanced V-NAND products with higher density and reliability. The company has also been working on a diversity of next-generation memory technologies including RRAM (or ReRAM) while strengthening its future business competence.

Howard: All major memory customers have 3D NAND transition in their roadmap. We’ll soon see the first generation of 24-layer 3D cell array devices enter the market. RRAM and STT-MRAM technologies are further out from the market as there are still critical process and manufacturing challenges for both the materials and patterning.

Handy: NAND will dominate. 3D NAND is less disruptive than alternative technologies, like RRAM, since it involves the same materials that have been used to produce NAND for its entire lifetime, while RRAM, MRAM, FRAM and so on require new materials that are not as well understood. After 3D NAND has reached a limit and can no longer place increasing numbers of transistors onto a wafer then the door is opened for alternative technologies like RRAM, but that won’t happen until 2023.

How is the semi industry (such as foundries and designers) preparing for the transition to 3D memory?

Handy: The bulk of the semiconductor industry doesn’t need to transition since these technologies are only being used for the highest-density discrete memory chips. The most significant impact should be to the capital equipment market, where a move to 3D could increase materials equipment usage while decreasing spending on lithography tools.

SE: We are working closely with global IT companies in a wide range of fields to expand the market base and application of 3D V-NAND, and we expect that the market will grow rapidly throughout the year. The 3D V-NAND is expected to be adopted in many different applications including SSDs, high-density memory cards and other applications for consumer electronics. While Samsung will work on more V-NAND based applications, the company also will contribute to global IT companies’ development of next-generation IT systems using our 3D V-NAND products.

Are there specific tooling challenges that must be overcome?

SE: The key technologies for V-NAND would be applying 3D CTF structure for individual cells and constructing vertically interconnected cell arrays. We have mastered these technological challenges and will continue to come up with more advanced V-NAND products.

Howard: Fabricating vertically to build multilayer stacks of 3D NAND cells reduces the historical reliance on lithography as the dominant and limiting factor in scaling, and increases the role of materials-enabled deposition and etch to drive vertical scaling. This shift brings formidable device performance and yield challenges for deposition and etch technologies including distortion-free high aspect ratio etching, complex staircase patterning with precise step-width control, and uniform and repeatable deposition.

From a 3D NAND fab perspective, the changing balance of tool types toward significantly more deposition and etch equipment will have a substantial impact on tool footprint and fab layout to enable optimum manufacturing efficiency. Moreover, this new tool balance compromises the capability to adjust manufacturing capacity between NAND and DRAM since planar NAND and DRAM share a high level of commonality with regard to the balance of tool types and lithography.

Handy: For 3D NAND there are significant challenges in putting down layers that have uniform thickness across the entire wafer. There are also issues with pull-back etching for stairsteps that currently increase the lithography load more than was originally anticipated, but this issue should eventually be solved. For alternative technologies there will be issues in bringing new materials into the fab, some of which are antagonistic to the underlying silicon.

To what extent can 3D memory chips be scaled and what challenges does this pose?

Howard: Scaling for the first few generations, from 32 to 48 to 64 and higher cell layer stacks will largely be a matter of adding more vertical layers. The general consensus is that this is sustainable to around 100 device layers, and this will likely require some amount of reduction on the layer thicknesses to control the aspect ratios that must be etched. Even small reductions in thickness are critical, because any reduction gets multiplied by the number of layers. Scaling beyond this will likely require more effort towards thinning the layers through advancements on the device architecture.

Lithographic-based horizontal scaling will continue, but instead of the historical 15-20 percent CD reduction per generation, we expect planar scaling to slow dramatically, equivalent to a CD shrink more on the order of ~5 percent per generation. In addition, layout changes in the peripheral circuits to achieve more efficiency, along with more efficient designs for the complex staircase structure to allow for access to the different layers, are expected. These will all play a role in overall die size efficiency.

For deposition, major challenges to effectively scale vertically are advanced thickness and uniformity controls layer to layer. Any non-uniformity in a film layer will propagate throughout the stack as subsequent layers are deposited on top of it. With more layers in the device stack, this results is more devices potentially impacted by topography.

The challenge for etch is growing high aspect ratios despite a thinning down of individual layers in the stack. Aspect ratios today are already at 60:1. Achieving etch fidelity at such aspect ratios puts pressure on getting higher selectivity to the mask material which already is very thick. In some cases, the aspect ratio for the hard mask is already greater than 20:1, and this is the aspect ratio before even starting the etch into the device stack. While thinning the hard mask layer reduces the overall aspect ratio of the feature, new more resilient patterning films will be required. Higher selectivity will be through a combination of new materials with higher etch resistance and improvements to the etch process chemistry.

SE: We have core technologies to develop more advanced high-density V-NAND devices and are seeking to define manufacturing technologies for stacking more than 24-cell-layer structure which was applied to our first 3D V-NAND device.

The most advanced process technology for conventional NAND using floating gate would be 10 nm-class technology. However, process technology refers to the width of integrated circuitry that is used for NAND on a conventional planar structure. Applying the same considerations to our V-NAND would not be appropriate because the cell array structure has been totally changed.

For example, if we compare the wafer productivity of Samsung’s new 128 GB V-NAND to previous products, it has the approximate chip size of a conventional NAND that was built using approximately mid-10nm-class process technology.

The 3D V-NAND has its strength in scalability. There are plans to continue developing more advanced V-NAND products and applications including 1 TB and higher-density SSDs for servers and enterprise systems and other next-generation memory storage which should lead to the growth of the overall NAND flash market.

Handy: 3D NAND is expected to scale in height, from 16-bit-tall strings to string heights of more than 128 bits. Meanwhile NAND makers will probably find ways of placing these strings closer to each other through more aggressive lithography. There is a lot of room for scaling in 3D.

Everything in 3D is a significant challenge. With vertical scaling the challenges include etching high aspect ratio holes, with the aspect ratio doubling with each doubling of layers. These holes must have absolutely parallel walls or scaling and device operation may be compromised. If the layers are thinned then the atomic layer deposition (ALD) of the layers must be able to apply a constant thickness layer across the entire wafer. This is also true of the layers that are deposited on the walls of the hole. The entire issue of 3D is its phenomenal complexity.

3D NAND: To 10nm and beyond

Wednesday, January 29th, 2014

By Sara Ver-Bruggen, contributing editor

In launching the iPod music player, Apple bumped consumption of NAND flash – a type of non-volatile storage device – driving down cost and paving the way for the growth of the memory technology into what is now a multibillion dollar market, supplying cost-effective storage for smart phones, tablets and other consumer electronic gadgets that do not have high density requirements.

The current iteration of NAND flash technology, 2D – or planar – NAND, is reaching its limits. In August 2013, South Korean consumer electronics brand Samsung announced the launch of its 3D NAND storage technology, in the form of a 24-layer, 128 GB chip. In 2014, memory chipmakers Micron and also SK Hynix will follow suit, heralding the arrival of a much-anticipated and debated technology during various industry conferences in recent years. Other companies, including Sandisk, are all working on 3D NAND flash technology.

Like floors in a tower block, in 3D NAND devices memory cells are stacked on top of each other, as opposed to being spread out on a two-dimensional (2D), horizontal grid like bungalows. Over the last few decades as 2D NAND technology has scaled, the X and Y dimensions have shrunk in order to go to each chip generation. But scaling, as process nodes dip below 20nm and on the path towards 10nm, is proving challenging as physical constraints begin to impinge on the performance of the basic memory cell design. While 2D NAND has yet to hit a wall, it is a matter of time.

Transition to mass production

But despite the potential of 3D NAND and announcements by the leading players in the industry, transferring 3D NAND technology into mass production is very challenging to do. As Jim Handy, from Objective Analysis, points out: “The entire issue of 3D NAND is its phenomenal complexity, and that is why no one has yet shipped a 3D NAND chip yet.” Mass production of Samsung’s device will happen this year. With 3D NAND there is the potential for vertical scaling, going from 16-bit-tall strings to string heights of more than 128 bits.

But while 3D NAND does not require leading-edge lithography, eventually resulting in manufacturing costs that are lower than they would be for the extension of planar NAND, new deposition and etch technologies are required for high-aspect-ratio etch processes. This “staircase” etching requires very precise contact landing. In 3D NAND manufacturing depositing layers of uniform thickness across the entire wafer presents issues with pull-back etching for these “stair steps” that currently increase the lithography load more than was originally anticipated.

Staircase etching requires very precise contact landing.

“Everything in 3D is a significant challenge. With vertical scaling the challenges include etching high aspect ratio holes, with the aspect ratio doubling with each doubling of layers. These holes must have absolutely parallel walls or scaling and device operation may be compromised. If the layers are thinned then the atomic-layer deposition (ALD) of the layers must be able to apply a constant thickness layer across the entire wafer, which is also true of the layers that are deposited on the walls of the hole,” according to Handy.

Indeed, while the best combination of cost, power and performance will be found in 3D NAND architectures, there still remain issues concerning cost, especially. These issues, in the context of their respective memory technology roadmaps, were discussed by memory chipmakers, including Sandisk, SK Hynix and Micron, at a forum organized and sponsored by semiconductor industry equipment manufacturer Applied Materials in December 2013, while the equipment supplier provided some in-depth discussion on 3D NAND manufacturing considerations and challenges. The session was hosted by Gill Lee, Senior Director and Principal Member of Technical Staff Silicon Systems Group at Applied Materials.

Sandisk plays its 2D hand for as long as possible

Ritu Shrivastava, Vice President Technology Development, at Sandisk Corporation, set out the challenge. “Whenever you talk about technology, it has to be in relation to the objectives of your company. In our case we have a $38 billion total available market projected to 2016 and any technology choices that we make have to serve that market.” Examples of products he was referring to include smart phones and tablets. “Our goal is to choose technologies that are most cost-effective and deliver in terms of performance.”

Sandisk has a joint NAND fab investment with Toshiba and the two have had a 128 GB 2D NAND flash chip using 19 nm lithography in production for a while now. They have also previously announced plans to build a semiconductor fab for 16-17 nm flash memory.

”One of our goals is to extend the life of 2D NAND technologies as far as possible because it reflects the huge investment that we have made in fabs and the technology, over the number of years,” said Shrivastava. “Of course, 3D NAND is extremely important and when it becomes cost-effective then it will move into production.” Sandisk plans to start producing its 3D NAND chips in 2016.

“We are travelling in what we think is the lowest cost path in every technology generation, going from 19 nm to 1Y where we at the limit with lithography, and then we will scale to 1Z, which is our next-generation 2D NAND technology. We believe that this scaling path gives us the lowest cost structure in each of the nodes and in terms of cumulative investment.”

But it is not just achieving the smallest die size, it is the cost involved in scaling. Capital equipment investment is what determines success in the market, according to Shrivastava. “Even though we are saying that 3D NAND is a reality there are a couple of things that we need to keep in mind. It leverages existing infrastructure, which is good, but there are still a lot of challenges. 3D NAND devices use TFT as opposed to the floating gate devices commonly used in 2D NAND chips. New controller schemes and boards will be required also.”

So while, according to Shrivastava, 3D NAND is looking very promising, there is a big ‘but’ for a company such as Sandisk, which produces some of the most cost-competitive flash memory devices on the market. “2D NAND still continues to be more cost-effective than 3D NAND and 3D NAND is not yet proven in volume manufacturing. Every new technology takes some time. Getting to mass manufacturing will take time. Our goal is to extend 2D NAND as long as possible, continue to work on 3D NAND and introduce it when it becomes cost-effective.”

Shrivastava sees 2D and 3D NAND technologies co-existing for the rest of the decade. Beyond 3D NAND the company is developing a 3D resistive RAM (RRAM) as the future technology beyond 3D NAND.

From 3D DRAM to 3D NAND

Next Chuck Dennison, Senior Director Process Integration, from Micron, provided an overview of where the company is today in terms of its own NAND memory technology roadmap.

“Our current generation is 16nm NAND that is now in production and we’re showing that it is getting to be a very competitive and very cost-effective technology,” according to Dennison. Micron’s new 16nm NAND process provides the greatest number of bits per sq mm at the lowest cost of any multilayer cell (MLC) device. Eight of these die can hold 128 GB of data. The 16nm storage technology will be released on next-generation solid state drives (SSDs) during 2014. SSDs consist of interconnected flash memory chips as opposed to platters with a magnetic coating used in conventional hard disk drives (HDDs).

Micron 16nm NAND die

“Our next node is a 256 GB class of the NAND memory. Technically it could be extended before taking the full step to 3D NAND.”

Today NAND is the lowest cost-per-bit memory technology and this continued cost-per-bit reduction is really driving the whole of the NAND industry, according to Dennison. It is why NAND replaced DRAM in terms of total dollars and has continued to proliferate across various applications, and is responsible for continued innovation in portable consumer electronics, such as tablets, where so much functionality enabling photography, video recording, storage of an entire music library, and so on, can be packed into one device.

Outlining Micron’s technology scaling path, Dennison explained: “We went to high-K/metal gate to 20 nm and we used the same technology to extend us to 16nm. From there, the company is moving to a vertical channel 3D NAND for a 256 GB class.

“In terms of capital expenditure (CapEx) per wafer it all looks very cost-effective, with a little bit of transition going to 20 nm,” explained Dennison, because of the high-K metal gate, but with minimal increase going to 16nm. “But when you go to 3D NAND it is expensive, per wafer. So if you are increasing your wafer costs by X amount you need a much higher amount of GB per cm sq, so the density we are choosing to go with is a 256 GB class. And when you start actively looking at 3D NAND there are a lot similarities between 3D NAND and DRAM,” he explained, referring to the stacked capacitor of DRAM. “There is a lot planarization, you are etching very high aspect ratio contacts where you need to be very controlled, in terms of how you define your control and CD uniformity. Then there are a lot of additional modules requiring ALD deposition. So we think that there is a lot of opportunity to utilize our DRAM expertise.”

He outlined an inflection point going from 16nm, again. “We’re transitioning to go to the 256 GB density. We think that when we do this it will make financial sense and it will be a cost-effective solution despite the high Capex. And then from there we will continue. With the majority, or bulk, of the market we’ll see vertical NAND continuing to scale with a couple of us scaling fast for that market.”

Dennison also touched on longer term advances in classes of flash memory, in the form of 3D cross-point technology. These are memories stacked in cross-point arrays over CMOS logic to enable memory technology with speed features akin to DRAM but the density and cost effectiveness of NAND. The 3D stacked memory arrays in 3D cross-point technology would make these devices suitable, for future, in very high density computing and even biological systems.

“But, to conclude, NAND will not be replaced and will continue to be the lowest cost, it’s going to be the largest market in tablets, phones and so on. It’s not the best memory technology – it has poor cycling endurance and it has a terrible latency – but it is very low cost at very high density so it is the most cost-effective solution. We think that 3D cross-point absolutely has a market in terms of displacing DRAM and will selectively displace some NAND in very high performance applications but we will stay with NAND and go to 3D NAND.”

Soek-Kiu Lee, VP and Head of the Flash Device Technology Group, at SK Hynix brought the audience up to speed on his company’s NAND technology. Every year SK Hynix has increased bit density per area by around 50%. The company’s 16nm 64 GB MLC NAND flash, based on floating gate technology, has been in production since mid-2013 with SK Hynix now entering full scale mass production of 16nm chips. SK Hynix will start to ship samples of its 3D NAND chips this year with mass production happening later in 2014.

Like Shrivastava, Lee expects that 2D NAND and 3D NAND will co-exist and compete with each other in terms of reliability, performance and density, for some time and that the big challenges facing the transition to 3D NAND architectures include stabilization of multi-stack patterning to improve yields, better metrology and defect monitoring in the 3D structure itself.

Head for heights

Lastly, Applied Materials was able to provide some insight into manufacturing the more complex structures that moving to 3D NAND device architecture entails. Very simplistically, to make 3D NAND flash devices requires building extremely tall multilayer structures. Every layer in the device requires an insulating layer, so – for example – a 32-layer device is really a 64-layer device. As a result of this, aspect ratios of the structure being etched are getting to be very high and the challenge that this poses is nothing less than a game-changer for etch and deposition, according to Applied Materials’ Vice President, Advanced Technology Group Etch Business Unit, Bradley Howard.

“Historically, if you look at how scaling has gone, it has been limited by lithography on getting to the next node down, now we getting to the point where scaling is being driven by deposition and etching because as the scaling is now going in a vertical direction you’ve eased out the design rules.” The reality is that lithography is still important, Howard said, listing off control, good uniformity and other factors. ‘Everything that you had to have from lithography before still needs to be there but it just does not need to be the limiting factor for scaling.”

High aspect ratios present lots of challenges. Standard photolithography will not hold up for the long etches required for etching such deep features so hard mask layers are needed. “Depositioning is transitioning from single layer depositions in typically thinner films to multilayer stacks where you go and deposit alternating stacks of films and then also very thick films for both device and the hard mask,” said Howard.

Howard addressed the gates axis, an alternating stack of materials built up with alternating layers. “You need to have very precise control and very low defectivity. Historically, if you had a defect come in on a film it affected that bit, or that area. Now if you get a defect that gets deposited on your first layer down at the bottom it becomes a propagating defect that goes up the entire stack and it is going up in regions , which means that the defect density on deposition is becoming more important.”

Howard then moved on to hard masks. “We are going to have thicker hard masks because the aspect ratios of what you are trying to etch are getting very extreme as well as the amount of depth you have to etch. Having a micron or a micron-and-a-half of hard mask is not unusual. In effect, the hard mask that you are forming is its own high aspect ratio feature and then it is forming a high aspect ratio feature below it. In addition, there are various challenges on the isolation on getting the gap filled between the features and also into these very complex three dimensional structures.

“On the etch side high aspect ratio is really the key. There are multiple features, contacts in the array, there are contacts coming out of the staircase, and 60: 1 aspect ratios are becoming the common target here.

“At the edge of the array access still has to be made at each one of the layers, so a staircase structure is made to enable different landing pads for contacts to come down. But some of the contacts – towards the top – are very shallow and the ones at the bottom are extremely deep.

“You might think it might be achieved by doing a litho step and an etch step and a litho step and an etch step and doing that 32, 64, or whatever number of times, but what happens is that you are starting out with a feature and you etch down into the feature then you pull back the resist and then you etch again and then you pull back the resist and so you start to form your ‘steps’ that way and you do that as many times as you can get away with, depending on the amount of resist that you have. So, you can envision that you are trying to pull this resist back really fast. The problem is the resist is now determining the CD for the cell, so you need to have good control in place.” Howard summarized the challenges as being about sequential processes for both deposition and etching, thick films – whether it be the alternating stack of films or the thick films that are done to separate out the different arrays – and, finally, defect densities – especially with deposition – which are becoming more critical than ever before because of the additive effect on the deposition.

The panellists:

Dr Ritu Shrivastava, Vice President Technology Development, at SanDisk Corporation

Chuck Dennison, Senior Director, Process Integration, at Micron

Dr Soek-Kiu Lee, VP and Head of the Flash Device Technology Group, at SK Hynix

Hang-Ting Liu, Deputy Director Nanotechnology R&D Division, at Macronix International Co.

Dr Bradley Howard, Vice President, Advanced Technology Group Etch Business Unit, at Applied Materials

FinFET on SOI: Potential Becomes Reality

Thursday, December 5th, 2013

Authors: T. B. Hook, I. Ahsan, A. Kumar, K. McStay, E. Nowak, S. Saroop, C. Schiller, G. Starkey, IBM Semiconductor Research and Development Center

We report here empirical results demonstrating the electrical benefits of SOI-based FinFETs. There are benefits inherent in the elimination of dopant as the means to establish the effective device dimensions.  However, significant compromise is unavoidable when using doping as a means of isolation, as in bulk-based FinFETs.  Accordingly, we use SOI as the base on which to build the FinFET, which not only simplifies the process but enables full realization of the potential of the device.
Fully depleted transistor technologies – both planar and SOI-based FinFET – offer excellent circuit operation for SRAM and DRAM due to the unsurpassed threshold voltage matching associated with the near-absence of doping.   Additionally, good low voltage and stacked-fet circuit operation is realized due to the superior electrostatics associated with thin-body devices.  Hardware data specifically illustrating these features is described below.

Threshold voltage matching and distribution

A significant improvement in threshold voltage mismatch has been well documented, as well as the degradation associated with adding doping to a FinFET.  Less well publicized, however, is the even larger relative benefit to be found in thick-dielectric transistors, such as are used for analog and IO devices, and also in DRAM.

Random dopant fluctuation is not the only mechanism contributing to local threshold voltage mismatch, but it has historically been the largest contributor.  It has been an even larger contributor for thicker dielectrics, as its baleful influence scales directly with dielectric thickness, unlike work function variations for example.   Therefore an even more dramatic improvement in matching is found in thick-dielectric devices, as shown in Figure 1.

Figure 1. Mismatch data as a function of tinv for conventional doped (dotted line) and SOI FinFET (solid line). While the improvement in matching for ‘thin-oxide’ (1.2-1.5nm) is well known, less widely recognized is the even larger advantage obtained with ‘thick-oxide’ (>3nm) devices commonly used in IO and analog applications.

This improvement is important to IO and analog circuit operation and is vital to scaling the DRAM transfer device into the next generations.
In Figure 2 are shown probability plots of the threshold voltage for two DRAM transfer gate transistors and the profound improvement is obvious.   The FinFET version actually has a considerably thicker gate dielectric than the conventional doped device and a shorter gate yet much better matching.  The absence of thickness-driven matching opens up the device design space and enables optimization of the overall design, as well as allowing for the fundamental area scaling needed to move to the next generation.

Figure 2: Threshold voltage matching for DRAM transfer devices. Blue: 32nm generation thick oxide doping-controlled device. Red: 14nm generation thick oxide FinFET device. The FinFET device is shorter and has a thicker dielectric, yet the threshold voltage matching standard deviation is 0.7X that of the conventional planar doped version. This improvement is applicable also to other thick oxide devices, such as are used in IO and analog applications.

SRAM Vmin
One of the most important benefits of improved matching is the much-desired reduction in the minimum operating voltage of the classic 6T SRAM.  While the transistor matching data clearly show an advantage, putting it all together into a quantized FinFET SRAM cell with correct beta and gamma ratios and device centering to actually achieve low Vmin is a larger challenge.
Additionally, there may be other factors present in the scaled-up SRAM array that may not be so evident in the classic Pelgrom analysis from which most matching data are derived, such as some perturbation to line-edge-roughness, or nfet/pfet interactions, or any number of other possibilities.

Our data demonstrate that these concerns are surmountable and that real SOI FinFET SRAMs can operate at very low voltages. Figure 3 shows remarkable results on an SRAM array, with full read and write operation down to 400mV, without any assist circuitry.  This is among the best results ever reported, even among those that utilize boost techniques and in-situ tuning of the devices.

Figure 3: Shmoo plot of 14nm SOI FinFET SRAM array showing a minimum operating voltage of 400mV, with full read and write capability. This result, as good or better than any yet reported, was obtained without benefit of the chip-specific tuning techniques associated with planar fully depleted devices or specialized independent double-gate FinFETs.

Low Voltage Circuit Operation
A considerable improvement in electrostatics associated with the FinFET over conventional doped devices not only enables the necessary gate-length scaling, but simultaneously improves the relative performance at reduced voltage and therefore reduces the power density at a given performance.  While fully-depleted devices should in principle enjoy this advantage, the introduction of non-uniformity such as is involved with the tapered fin profile associated with bulk-based FinFET seriously compromises the output conductance and may obviate these expectations, as shown in Figure 4.

Figure 4: Representative bulk-based and SOI-based fin profiles, and corresponding empirical degradation in electrostatics. The tapered shape of the bulk fin shown results in nonuniform current flow and poorer low-voltage operation and self-gain than the more ideally shaped SOI FinFET.

The fin profile obtainable in SOI-based FinFETs is very nearly ideal and our data show that the low voltage benefits are fully realized in hardware.  The frequencies of a suite of ring oscillator circuits (inverter, NANDs, and NORs) were measured on 14nm SOI-based FinFET hardware as a function of voltage and compared to the modeled expectations.
Figure 5 shows excellent correspondence with expectation, and also shows how the data are far superior to the voltage dependence of conventional planar technology.

Figure 5: Normalized frequency reduction as a function of Vdd for a suite of circuits (NANDs, NORs, and inverters). Near-perfect correspondence of the SOI FinFET data with the compact model is shown. This flatter voltage dependence is highly superior to that typical of doping-controlled planar technology.

Conclusion
Several key elements of the putative advantages of FinFETs over conventional devices have been demonstrated in hardware.  By using SOI-based FinFET technology, the need for doping in the body has been effectively minimized, resulting in excellent matching characteristics in the undoped DRAM transfer device, and truly remarkable minimum operating voltage in the SRAM.  Additionally, the superior voltage dependence and stacked-fet circuit behavior relative to conventional devices has also been demonstrated through measurements of ring oscillators of various sorts.

Applied Materials – Tokyo Electron Merger Hastens EDA Changes

Monday, September 30th, 2013

Paradoxically, the merger of equipment manufacturers AMAT and TEL may shrink the Electronic Design Automation (EDA) tool market while improving IP security.

In the last several days, much has been written about the proposed merger of Applied Materials (AMAT) and Tokyo Electron (TEL). Desired by both, this merger would create a company worth $29B that would be the largest semiconductor equipment company in the world by sales. In comparison, the EDA tool market is roughly valued at $1.1B.

This merger of capital equipment giants represents an ongoing consolidation of the semiconductor supply chain, from chip/component developers through the IDM/foundries and manufacturing space. One reason for this consolidation is the increasingly high costs of making chips smaller and smaller – e.g., at the leading edge process nodes.

At first glance, it would appear that the merger will have little impact on the world of semiconductor intellectual property (IP). Still, one of the stated goals of the merged companies is to extract costs, “from all layers of the supply chain,” according to a recent report from Canaccord Genuity’s analyst Josh Baribeau (see, “Size Matters: Our First Take on AMAT’s Proposed Merger with Tel.”)

While admittedly far down on the supply chain relative to capital equipment, the Electronic Design Automation (EDA) tool market – heavy dependent on design and verification IP – might feel the effects of this merger in several ways.

First, equipment manufactures use EDA tools and related processes to qualify new manufacturing systems. For example, last year Applied Materials supplied critical film properties (new materials) and device characterization data from its advanced process systems to Synopsys. This allowed the EDA vendor to create more accurate chip design and verification models.

Such new materials and processes are necessary to keep Moore’s Law on track, in contrast to the ever increasing lithographic costs at lower and lower nodes. Several new technologies and process node shrinks are also driving up the cost of manufacturing leading edge chips – such things as 3D NAND devices, 450mm wafers, finFET structures, stacked dies and more.

Still, the cost of EDA tools are low in relationship to other costs. According to long-time EDA analyst Gary Smith, the cost of EDA tools is analogous to lunch money. The real costs in SoC development are related to the cost of engineers to do the design. Greater level of chip design-verification tool automation will reduce these costs, as will, “the reuse of software, the reuse of verifiable design IP, and by reducing SoC core blocks below the typical five blocks.” (see, “Gary Smith’s Sunday Night, Pre-DAC Forecast”)

It may well be that consolidation by the equipment manufactures will result in accelerated consolidation of the lower part of the semiconductor supply chain, e.g., EDA tool vendors. Judging from the furry of acquisitions in the EDA community over the last several years, this scenario is hardly surprising.

On the other hand, this merger of equipment giants might be a good thing for the development of soft IP standards. As Warren Savage pointed out a few months ago (see, “Long Standards, Twinkie IP, Macro Trends, and Patent Trolls“), the semiconductor equipment companies need to approve any IP design standards since it will be their systems that must read the soft IP.

Consolidation of the equipment market should mean fewer companies that need to approve any such standards, thus (in theory) hastening the approval process.

Will the end result of the AMAT and TEL merger mean further consolidation of EDA tools and hence the IP markets? Will the merger lead to greater IP protection at the lower process nodes? The answer will probably be revealed in the next installment of Moore’s Law, i.e., the next process node advancement.