The introduction of EUV lithography into the semiconductor fabrication process will enable a continuation of Moore’s law below the 22 nm technology node. EUV lithography will, however, introduce new and unwanted sources of patterning distortions which must be accurately modeled and corrected on the reticle. Flare caused by scattered light in the projection optics is expected to result in several nanometers of on-wafer dimensional variation, if left uncorrected. Previous work by the authors has focused on combinations of model-based and rules-based approaches to modeling and correction of flare in EUV lithography. This paper focuses on the development of an all model-based approach to compensation of both flare and proximity effects in EUV lithography. The advantages of such an approach in terms of both model and OPC accuracy will be discussed. In addition, the authors will discuss the benefits and tradeoffs associated with hybrid OPC approaches which mix both rules-based.

To view this white paper, click here.

By Jeff Chappell
There may have been a time when AMD founder Jerry Sanders famous quote: “real men (i.e., real companies) have their own fabs” rang true, but in today’s business climate it seems quaint at best.

Fabless or fab-lite business models are more popular than ever today, while some IDMs have turned back the clock, so to speak, looking to improve capacity utilization and revenues by offering foundry services—Intel and Samsung among them. Then there is the fact that the third-largest chipmaker in 2012, in terms of revenue, was a pure-play foundry.

As the 28nm node capacity ramp continues in the foundry market in 2013, following unexpected demand and capacity bottlenecks in 2012, today’s foundry market is the end result of market trends and forces with old roots. But those trends and forces have been compounded in modern times by extreme financial and market necessities, not to mention technology.

In one sense, however, at its core, the foundry market hasn’t changed since Taiwan Semiconductor Manufacturing Co. (TSMC) launched as the industry’s first pure-play foundry in 1987: Chip companies look to foundries, either as a customer or as a provider, to maximize productivity and thereby minimize costs. That part of the game hasn’t changed, whether it involves a component supplier designing power modules with 0.18-micron design rules for manufacturing on 200mm wafers, or one of the two GPU giants producing their next-generation graphics processors based on the latest technology.

The trend for years now has been fabless or fab-lite; even Sanders’ own AMD spun out its manufacturing arm several years ago to create one of the world’s largest pure-play foundries, GlobalFoundries. This has naturally in turn spawned the growth of the pure-play foundry market from its birth some 26 years ago.

Indeed, last year the overall foundry market enjoyed revenues of $29.6 billion, managing year-over-year growth of 12%, which is three times that of the chip industry over all in 2012. That growth caught everyone by surprise including the foundries themselves; 28nm capacity was tight for much of the year, even as yields improved dramatically—so much so that it reportedly impacted some capital equipment purchases, in spite of tight foundry capacity.

But that illustrates the biggest and most obvious change in the foundry industry in modern times: The foundries themselves are involved directly with developing leading-edge semiconductor technology. In fact, with the industry looking at the end of planar CMOS at the leading edge for some devices with the advent of 3D transistor architectures and the high-k materials they require, leading foundries no longer can rely on a mix of conventional scaling, publicly available data and equipment and process technology suppliers to get their jobs done. Research and development now must be within their purview, at least for those playing at the leading edge.

“Historically foundries don’t do R&D, their clients do it,” noted Dean Freeman, a research vice president at Gartner Research. That’s not so, today.

Nothing illustrates that fact better than TSMC’s R&D budget. In 2012 the company spent 33.8 billion NT, or about $1.13 billion, on R&D—a quarter of its revenue. This year the company plans to spend 40.4 billion NT, or about $1.35 billion, which includes adding some 500 people to its employee headcount, bolstering its R&D staff from 3,400 people to 3,900.

Indeed, leading foundries have joined the leading IDMs and technology consortia as purveyors of—not just manufacturers of—advanced technology.

While TSMC and its foundry brethren in the first tier of the pure-play market—Globalfoundries and United Microelectronics Corp. (UMC)—continue to build out 28nm capacity, they are also hard at work on the 20nm node and the subsequent hybrid 14/16nm finFET based on a 20nm back-end of line process. In fact, TSMC just announced first tapeouts of an ARM A-57 processor, based on the 64-bit ARMv8 processor series and built with 16nm transistor technology, including finFETs. This followed their rival’s announcement of a few months earlier. In February, GlobalFoundries announced a “first implementation” of a dual-core ARM A9 processor using the company’s 14nm-XM FinFET transistor architecture.

Follow the money
Being on the very leading edge of technology is driving growth among the first-tier foundries.

Like many others in the industry, TSMC and its chairman and CEO, Morris Chang, are quite bullish on the continued demand for 28nm technology as well as the development of 20nm technology. In general, 28nm designs, with their combination of lower power consumption and speedier transistors, have consequently proven cost-effective for a chip industry currently driven by mobile devices—smartphones, tablets and ultra lightweight notebooks. During TSMC’s review of its 2012 results earlier this year, Chang said the company will continue to aggressively grow its 28nm capacity and output; 2013 capacity and output will triple that of 2012, he said.

“It’s all about lower power with functionality and no sacrifice on the power requirements,” observed Kathryn Ta, managing director of strategic marketing for Applied Materials’ Silicon Systems Group. The equipment and process technology supplier’s foundry customers are seeing a need to move to 3D transistor architectures with minimal leakage, she said, because of those power requirements.

Development will continue at 20nm and 16nm as well at TSMC and its rivals. This year, 88% of the 9 billion NT that TSMC will spend on capital expenditures will go to 28nm, 20nm and 16nm capacity; an additional 5% will be spent on additional R&D equipment. Chang predicted that by Q3 of this year high-k metal gate production will surpass that of standard oxynitride gates, a gap that naturally will widen in Q4 and beyond.

“Enough discussions have taken place with enough customers … to lead us to believe that in both its first and second year of production (2014 and 2015, respectively) the volume of 20nm SoCs will be larger than that of 28nm in its first and second years of production (2012 and 2013),” Chang said.

He further noted that this represented the state of the art, and not just for the foundry industry, but for the industry as whole. This may indeed prove to be true in a few years as those 20nm and 16nm/14nm SoC devices move into production. It’s a far cry from the days when foundries were traditionally technological also-rans.

But then the first-tier foundries at the leading edge are still playing catch-up in the meantime with those IDMs at the leading edge, namely Intel. The world’s biggest chipmaker has kept Moore’s Law on track on the CPU side of the ITRS roadmap, last year having brought its Ivy Bridge processors to market. These feature 22nm transistors replete with finFETs; Intel’s own roadmap calls for 14nm designs to be in production in 2014; in terms of mobile SoCs like those the foundries are talking about, the company has promised its 22nm Atom SoCs will be in production in 2015.

“Intel seems to be able to continue to shrink because they spend a fortune on R&D,” said Gartner’s Freeman. “The foundries are pushing hard to catch up,” He noted that while both GlobalFoundries and TSMC have 16nm/14nm chips featuring finFETs in development, they are taking a shortcut, so to speak, by employing 20nm metal interconnects. “It’s close to what Intel is doing. Intel’s design may be more sophisticated, but the lithography is the same.”

Plenty of room, and business, at the trailing end
But not everybody in the foundry market is playing at the leading edge. The same market and industry forces that have induced the bigger pure-play foundries to move beyond their historical roles also have created a two-tiered pure-play foundry market. In the first tier are those that have the deep pockets to play in this space: TSMC, Globalfoundries, UMC, and to a lesser extent China’s Semiconductor Manufacturing International Corp. (SMIC).

Then there are the second-tier companies, those that are still fulfilling a traditional foundry role—at trailing edge processes, but nevertheless needed or even essential semiconductor manufacturing technology and capacity. Indeed, many second-tier foundries do quite well with their particular market niches and technologies. In the world of mobile consumer gadgets, including but not limited to smartphones and tablets, there are still many components fabricated on established, trailing-edge technology, such as sensors, microcontrollers and power components.

Even in 2013, where CPUs with 22nm transistors and mobile SoCs with 28nm transistors represent the current state of the art, some 40% of all silicon used to manufacture chips goes into mature devices fabricated on 200mm wafers. That’s typically 0.18-micron designs or larger. And much, if not most, of that is coming from pure-play foundries.

At the top of that second-tier foundry market, Israel’s TowerJazz, for example, has found a relatively comfortable niche making high-speed devices for a broad range consumer applications utilizing 0.13-micron designs and larger. It also makes CMOS image sensors with 0.16- and 0.11-micron design rules. In terms of financials, this has translated to record revenues: last year TowerJazz posted revenues of $638.8 million, an increase of 5% over the previous year.

Freeman suggested there are plenty of opportunities for these second-tier foundries. The so-called “Internet of Things,” for example, is a major driver behind sensor applications, as it is for the controllers needed to coordinate the data these sensors produce—data that can be managed via mobile Internet devices. These supplemental and complementary applications typically don’t need cutting-edge technology.

As has always been the case in the foundry industry, as leading-edge technology becomes trailing-edge, there will be new opportunities for second-tier foundries, as well. Some of the larger second-tier foundries eventually may have the opportunity to compete with first-tier companies head-to-head with 28nm capacity if they have deep-enough pockets to invest.

In the bifurcated smartphone market, for example, low-end smartphones that originally utilized chips manufactured with 40nm technology soon will migrate to chips with 28nm technology, as capacity ramps and it becomes even more cost effective, said Applied’s Ta. Even as the leading-edge players are driven beyond the 28nm node and the adoption of 3D gate architectures, the industry could very well see an extended 28nm node, driven by this market for lower-end smartphones and other mobile devices, she said.

But What About …
Things rarely ever prove to be so clearly defined in the chip industry. With players such as Samsung, Intel and IBM among others flirting with the foundry business, and some of the larger first-tier foundries suffering the same financial headaches that have plagued the IDMs in the past—problems that drove some of them to a fabless model in the fist place—there are some significant unknowns.

While 3D, high-k metal gate architectures, i.e, finFETs and the like, seem to be the wave of the near future, there are still those in the industry that tout the efficacy of fully depleted silicon-on-insulator (FD-SOI) as either an alternative to complement to 3D gate technology, for example.

IBM and its technology alliance partners have considered FD-SOI as a possible outcome of the semiconductor technology roadmap in the near future, Ta noted. “We see most of the effort on the finFET/Intel approach, but some of our customers are still talking about SOI,” perhaps used in some combination with finFETs, she added.

Gartner’s Freeman noted that Intel’s finFET devices are already fully depleted devices, although SOI could conceivably provide a bit less leakage; as such it may be an option at future nodes. Given the transistor speed and power usage achieved by its 22nm Atom processors, which are manufactured on top of bulk silicon technology, that seems unlikely though for Intel and those choosing to follow its lead. Freeman further observed that GlobalFoundries, once a proponent of FD-SOI, has backed off somewhat, although some of its largest customers remain committed to an FD-SOI strategy for the foreseeable future. IBM, for one, has publicly stated it will use FD-SOI, finFETs and stacked die together at future nodes.

But what does this mean for the leading-edge foundries? As always they will have to be able to manufacture what their customers want. It may be that some chipmakers will choose to go the FD-SOI route and that could prove a competitive opportunity for any foundry.

Another wild card that the top-tier foundries will need to take into account is the overlapping of technology nodes, which may become more pronounced with the extension of the 28nm node coupled with the rush to get 20nm devices into production. “It’s happening faster than previous node transitions have happened,” Applied’s Ta, noting that it’s driven by the low-power promise of finFETs. In the past node transitions typically took two to 2.5 years; “This time we may see a 1.5 year transition to finFETs,” she added.

Another question mark in the foundry market itself is SMIC. While most would still classify the Chinese foundry as a top-tier foundry, it is in a very real way straddling the gap between first and second tier. The company, once relatively close behind TSMC and UMC, has foundered in red ink and legal woes in recent years. While it has subsequently experienced an impressive turnaround financially under the helm of current CEO Tzu-Yin Chiu in 2012, it’s capital expenditures fell dramatically, even as capacity utilization hit 95% in Q2, and it is well behind its rivals in terms of technology.

Customer tapeouts of 28nm devices won’t take place until the end of this year; One of SMIC’s largest domestic customers, Spreadtrum, already has been forced to move to rival TSMC to meet its current plans for 28nm devices.

SMIC’s Chiu has said that the company’s 28nm technology will include both standard polysilicon oxynitride devices and high-k metal gates, and that it has plans to manufacture finFET devices at the 20nm node. In the meantime, it has found a saving grace in applications typically manufactured by second-tier players: smart cards, CMOS image sensors and power management chips.

Which way will SMIC go? Will it continue its impressive turn around by abandoning the leading edge or will it continue to play technological catch up? Or perhaps a little bit of both?

Time will tell. But it’s certainly an interesting time for the foundry business, and certain that for the foreseeable future the pure-play foundries will have to work hard at the cutting edge of semiconductor technology.

By Ed Sperling
Ever since the inception of Moore’s Law, process nodes have moved forward at a rate of once every 18 to 24 months. Companies have been talking about slowing down the rate of progression as things get harder, but at least for the next couple of process nodes something very strange will occur—Moore’s Law will accelerate.

The root cause is growing competition for a shrinking number of increasingly valuable and complex SoCs reaching tapeout. The race between Intel, TSMC and the Common Platform triumvirate of IBM, Samsung and Global Foundries shifted into high gear when Intel introduced finFETs at 22nm. That was followed by promises of finFETs by GlobalFoundries and TSMC at 14nm, and later revised to add 14nm finFETs using 20nm back-end of line processes.

FinFETs offer clear advantages for controlling leakage over planar transistors. At the same time, because there is less heat being generated and batteries last longer on mobile devices, the clock frequencies can be turned up for some critical components without overstepping the system power budget. In grossly over-simplified terms, if you save in one place, you can spend in another without altering the balance. Nothing is ever quite that easy, of course, but with some place and route modifications and double patterning issues taken into account, the power/performance improvements that are possible with finFETS—and the carbon-nanotube and tunnel FETs that will follow—are game-changing.

Let the games begin
Intel stunned its competition when it rolled out its “TriGate” version of finFETs at 22nm. And with Intel touting its own limited foundry model to a select few high-volume customers, rival foundries had little choice but to accelerate their own R&D. They appear to have done this quite effectively—in fact the next node will follow introduction of the hybrid node 20/14nm node with FinFETs within about a year.

“In 2013 you will see a model shift,” said Michael Cadigan, general manager of IBM’s microelectronics division. “The focus is on more and earlier involvement, and we will deliver technology faster into the fabs, which means we also will bring technology to market faster.”

This is largely an ecosystem play, and in the case of the Common Platform members it combines extensive research capabilities from all three companies. “What we are able to do now is quickly ramp up our wafer knowledge,” said Mike Noonen, executive vice president at GlobalFoundries. “ That’s all a function of how fast we can move a wafer through.”

Ecosystem reverberations
Still, the decision isn’t entirely up to the foundries. No one company is big enough to do everything anymore—not even IBM or Samsung. The delay in bringing EUV to the market is a case in point. While the market has been more than ready—there’s even a building ready at the Albany Nanocenter, which IBM’s Cadigan promised the state of New York would be in use by now—the power source is still not commercially viable. It was supposed to have been ready at 45nm, and its absence is being felt acutely at 20nm because the alternative is double patterning of critical layers. By the time the 14nm back-end of line process shows up next year, multi-patterning will become the norm with double patterning on most other layers.

All of this has put a heavy burden on EDA tools and third-party IP vendors, which have to place bets in order to properly funnel R&D dollars. While it’s important to be at the bleeding edge of the market with tools and IP, because that allows them to mature along with the processes, it’s also important to strengthen offerings at 40nm and 28nm. The result is that EDA vendors hear complaints about not doing enough on either side.

“The tools we have today can do the job, but there are more issues and companies need to keep working closely together to deal with them,” said Juan Rey, senior engineering director for Mentor Graphics’ Design to Silicon Division. “When there is a need on the semiconductor manufacturing side to move at a certain pace, they generally keep in mind what has to happen on the EDA side. But the whole infrastructure has to be ready, so there may be a longer future at 10nm and beyond.”

Put in perspective, the acceleration of Moore’s Law in the short term may be an aberration, with fluctuations in the exact timing more likely to occur as design and manufacturing become more complex. He’s not alone in that assessment.

“We believe that at some point the process nodes will slow down,” said Chi-Ping Hsu, senior vice president for R&D in the Silicon Realization Group at Cadence. “Whoever has the best technology to address that last node will win in the marketplace.”

Still, understanding what that node is, and how other approaches will fit in and affect the whole design to process flow, is not clear. Billions of dollars have been spent already to bring EUV to market, with billions more being poured into the effort. It still isn’t ready, and companies are beginning to look at alternatives such as directed self-assembly just in case it never reaches commercial viability.

Moreover, the move to stacked die, which is expected to begin this year with 2.5D packaging approaches and within a couple of years for full 3D stacks with through-silicon vias, could allow things like analog, I/O and memory IP to stay at older process nodes. That, in turn, would greatly simplify the design and manufacturing digital platforms at newer process nodes, but it would render Moore’s Law meaningless for big portions of an SoC.

“2.5D and 3D are becoming active considerations in regard to what to put in the package,” said GlobalFoundries’ Noonen.

Scheduling conflicts
Unlike in the past, where there typically was one big problem to solve at each new process node (130nm was the exception because there were three—the introduction of copper interconnects, low-k dielectrics and 300mm wafers), there are more big issues surfacing at each new process node. And while things have accelerated in the short term, that’s unlikely to happen beyond 10nm.

KH Kim, executive vice president of the foundry business at Samsung Electronics, pointed to three main challenges at future nodes: process variation and parasitics, channel width and drive current choices, and modeling and extraction. Any one of these three areas can become more problematic at future nodes, Kim said.

And on the design side, things like routing congestion, fill, complex 3D modeling and verification of all types—including detailing of physical effects such as heat, electrostatic discharge and electromigration—already are difficult. At some point they will become significantly more expensive to resolve, raising questions about the return on investment for EDA and IP companies. The result may be that the entire ecosystem cannot afford to move forward to the next node at the same time.

As Gary Patton, vice president of the Semiconductor Research and Development Center at IBM, observed: “People are used to getting 50% performance and a 10% to 15% cost improvement as they move from one node to the next. In the future it will be less than 50% performance improvement with the same 10% to 15% cost benefit. It won’t be as large as in the past.”

And for most players in the design to manufacturing ecosystem, that benefit will vary depending upon their individual slice of the flow, which could further increase the gaps between players as time goes on.

GlobalFoundries VP Subramani Kengeri talks about progress and problems with advanced processes with Semiconductor Manufacturing & Design.

By Ann Steffora Mutschler
Given complexity, yield, power and other challenges with leading edge manufacturing, semiconductor foundries increasingly have been forced to require more and more restrictive design rules with each new process node.

“They keep adding more design rules and more operations to a particular check to eliminate corner cases where in manufacturing they saw some variant of this shape or this line width or whatever that is creating a yield problem or weak patterns,” observed Michael White, director of product marketing for Calibre physical verification at Mentor Graphics. “Starting at 40nm, even more so at 28nm and that much again at 20nm, is much more orientation-specific layout because folks are using more off-axis illumination. You pay a huge penalty for having optimized the aperture in your scanner for things that are oriented north-south. If you’ve got structures that are east-west they’re not going to resolve as well.”

One approach to deal with these issues termed ‘bad pattern flow’ is based on the idea that the designer can almost do anything they want, but certain 2D patterns are walled off as being bad and forbidden.

Coming at the problem from another perspective is the concept of ‘good pattern flow,’ based on the premise that, “in the future, maybe not everything is going to be manufacturable anymore,” explained Ya-Chieh Lai, engineering director at Cadence. “So the designer is going to be much more constrained moving forward, and the space of the design is really that most things are actually not going to print very well anymore. There’s a sense that maybe we need to have a better understanding of which things do manufacture well and come up with a set of patterns to represent that.”

While not in use at 20nm, this good pattern flow is being readied for the 14nm and 10nm nodes when design rule restrictions become even more severe. But to be enabled in the design flow will require the whole ecosystem to come together, he said.

“We’re working hard on having the core capabilities and tools. We need to work closely with the foundries, because they’re ultimately the source of all of these patterns and a lot of this analysis, to provide the right tools and capabilities to do the kinds of analyses they need to do. We also have to work in conjunction with the design side tools to enable this. This is all a work in progress.”

Specifically, Manoj Chacko, product marketing director at Cadence, pointed out that just as with bad pattern usage, the value to the designer of a good pattern flow is at the routing stage. “Find the issues early on and remove them before going through the signoff. The good pattern flow also mostly fits with the routing side and enforces certain patterns and makes the router enforce certain topologies.”

In terms of where the tools are now, work is being done with the foundries to make sure there is understanding about what the patterns are and how they are used. “A key part of what we are working on here is pattern analysis,” said Lai. “There’s been a lot of talk about pattern matching, but pattern analysis is a bigger story about understanding your layout. The foundries need to understand what designers are doing, be able to understand what patterns are in the design, what are the common cases and the outlier cases to make sure their manufacturing processes are tuned to be able to print what the designers are actually doing. A big part of that is analyzing what is actually in the design.”

Pushback is possible
Mentor’s White expects significant pushback to the good pattern flow strategy. “Over the last couple of years as we’ve been moving pattern matching out into the mainstream use for physical verification, we have some folks who love the ease of use of pattern matching and so on, and their foundry was headed down the path of trying to use more pattern matching to describe actual design rules. The frustration was that, ‘If I’m using patterns to describe only a very finite, small set of things that are manufacturable, you’re taking the design freedom away from the designer.’ They’d far prefer to have the foundry characterizing a broader application space of layout and maintain the designer’s freedom rather than solely focusing their attention on a smaller set of patterns that are known manufacturable.”

Lai agreed there’s always tension about being as restrictive as possible. “If it were up to the foundry they’d just want you to print grading—it’s just going to be straight lines because they know they can print that. But the designers want more flexibility to draw what they need to draw. So what we’re trying to do with the good patterns is to say, ‘We’re going to be as restrictive as possible but then we’re going to allow certain things to be used that would otherwise have been restricted by these restrictive design rules.’ That way it really is meant to help the designer where instead of putting on the brakes and saying, ‘No, you can’t do anything except use these very straight repeated structures,’ we are saying there are going to be certain things that are going to be allowed. These are allowed constructs that you as a designer can put in because this is what you need to make your design work, but everything else is going to be very locked in.”

At the end of the day, “the goal is to minimize patterning,” said Subramani Kengari, vice president of design solutions at GlobalFoundries. “But you also have to optimize a solution. That’s the main reason we’re using wide power rails on standard cells.”

Another consideration: As it stands, not all of the metal layers in a design at 20nm, or even the hybrid 20nm back-end of line (BEOL) process are coupled with 14nm finFETs. But as Moore’s Law continues, more layers will have to be at least double patterned, and with 14nm BEOL some parts of the chip will have to be triple or quadruple patterned.

With this just one example of the complexity that will be faced, a good pattern flow seems more reasonable. And given that designs are becoming much more regular at these advanced nodes is one reason a good pattern flow even becomes a possibility.

By Mark LaPedus
A survey revealed that 41% of U.S. adults who are married or in a relationship and have a computer say that time spent on the PC is a source of stress in their relationship. In fact, 59% cited work-related issues as causing relationship strain and 75% indicated that finances were a cause of stress in their relationship. The survey was conducted online by Harris Interactive on behalf of Crucial.com.

Taiwan’s United Microelectronics Corp. (UMC) continues to fall behind its competitors. UMC recently said it will move directly from 28nm to 14nm finFETs, thereby skipping the 20nm node. The new problem: UMC is having yield issues with 28nm and is behind in ramping up the technology, according to the company.

GlobalFoundries has not committed to build another new fab in upstate New York. However, the company this week filed plans for the possible construction of a new plant with 475,000 square feet of manufacturing space, according to various reports.

At the Common Platform Technology Forum, GlobalFoundries announced results from the industry’s first implementation of a dual-core ARM Cortex-A9 processor using finFET transistors.

GlobalFoundries also disclosed several of its customers at the event, including Adapteva, Cyclos and Rambus.

Also at the Common Platform Technology Forum, IBM confirmed that extreme ultraviolet (EUV) lithography will likely miss the 10nm node. Now, the industry is looking at inserting EUV at 7nm. The delays are not surprising. What’s surprising, and scary, is that many of the problems with EUV are not engineering issues. They’re due to pure physics, namely how to generate enough consistent power for the EUV source. “We’re talking about physics challenges,” said Gary Patton, vice president of IBM’s Semiconductor Research and Development Center. “This is real physics.”

Cadence announced an agreement to acquire Cosmic Circuits, a provider of analog and mixed signal intellectual property (IP) cores.  In addition, GlobalFoundries has certified Cadence’s EDA tools for custom/analog design for its 20nm LPM technology.

Soitec’s SOI wafer shipments for radio-frequency (RF) applications have increased by 400% in the last two years.  In fact, SOI is having a profound impact on RF designs and processes.

Mentor Graphics announced the next-generation of the FloEFD concurrent computational fluid dynamics (CFD) simulation product.

Fujitsu and Panasonic will merge their semiconductor units and form a new company. For some time, the system LSI businesses of Fujitsu Semiconductor and Panasonic have struggled.

Packaging and assembly are key segments of the semiconductor supply chain in China. There are more than 200 companies competing in the packaging and assembly market in China, according to SEMI.

LED bulb prices are expected to drop from $23 per 1,000 lumens in 2012 to $10 per 1,000 lumens in 2015, and then down to $5 per 1,000 lumens by 2020, according to SEMI.

The BioMEMS market is expected to grow from $1.9 billion in 2012 to $6.6 billion in 2018, according to Yole Développement. The BioMEMS market includes pressure sensors, silicon microphones, accelerometers, gyroscopes, optical MEMS and image sensors, microfluidic chips, and microdispensers.

NAND flash revenue was $19.7 billion last year, down from $21.2 billion in 2011. Revenue will pick up this year and will rise to $22.4 billion after last year’s stumble, according to IHS iSuppli.

Facing a relentless onslaught from tablets, smartphones and solid state drives (SSDs), hard disk drive (HDD) market revenue in 2013 will decline by about 12% this year, according to IHS.

Polysilicon suppliers to the solar photovoltaic (PV) industry have reduced their plant utilization rates during the past six months, with average quarterly utilization rates falling below 70%, according to Solarbuzz.

Limited commitments by touch-screen suppliers and ultra-slim panel makers are putting a squeeze on the ultra-slim PC market, according to NPD DisplaySearch.

Semiconductor Manufacturing & Design sits down with Mentor Graphics’ Jean-Marie Brunet to talk about double patterning, finFETs, design rules at advanced nodes and why design for manufacturing (DFM) has suddenly become so popular.

By Mark LaPedus
For years, silicon foundries have rolled out their respective leading-edge processes roughly on a two-year cadence.

The long-standing goal has been to keep foundry customers on a competitive price, power and performance curve. But as leading-edge chipmakers move from the 28nm node and beyond, the predictable process progression is changing. And the phenomenon of “node skipping” in the fabless-foundry world could reach new heights.

Two foundry vendors, GlobalFoundries and Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), recently accelerated their respective 14nm-class finFET shipment schedules by a year or so. In effect, the companies have shrunk the process cadence between their planar 20nm and 3D-like finFET technologies to roughly a year.

Samsung is expected to follow a similar path. In many respects, the foundries appear to be luring customers into making the giant leap from 28nm (or above) processes to finFETs, thereby skipping 20nm. The reason is largely due to lackluster demand for 20nm planar, and they are aggressively marketing their finFET technologies right now.

Rival United Microelectronics Corp. (UMC) has a different strategy. UMC will move directly from 28nm planar to 14nm-class finFETs, bypassing the 20nm planar node. UMC recently licensed finFET technology from IBM, but it will stick with bulk CMOS. For its part, IBM will ramp up finFETs using silicon-on-insulator (SOI) technology.

The foundries are speeding up their finFET efforts for several reasons. First, there is a perception that the foundries are falling further behind Intel. The chip giant rolled out finFETs at 22nm and is offering the technology to select foundry customers. Intel plans to begin ramping up its 14nm finFET process by the fourth quarter of 2013.

Some chipmakers have been openly critical about the 20nm foundry planar process, saying the technology puts the industry behind the traditional performance curve. “I know some customers want more,” acknowledged Morris Chang, chairman and chief executive of TSMC, in a recent conference call.

So, at 20nm and beyond, chipmakers are weighing their options and exploring the trade-offs. “There will be customers that will skip 20nm to get to (finFETs),” Chang said. “I think there will be customers that will be light on one (process technology) and heavy on another.”

The benefits of finFETs are clear, but the industry is finally coming to grips with the challenges associated with the transistor technology. Cost, patterning and variation are just a few of the issues. The complexity will require more and deeper collaboration between foundries and their customers. “The challenge for us is to work across the ecosystem with our partners and have earlier tapeouts that are fully debugged and tested,” said Gregg Bartlett, senior vice president and chief technology officer at GlobalFoundries.

All told, the fabless-foundry model is still alive and well, but the business continues to change. Going forward, leading-edge foundries will offer fewer process derivatives. Customers will have fewer choices. And in the future, expect possibly one foundry to exit from the leading-edge process race, with more consolidation seen on the horizon.

Skipping around the IC world
At one time, most leading-edge chipmakers followed the natural progression of process technology nodes. The dynamics began to change starting around the 90nm node, when chipmakers migrated towards sub-wavelength lithography, low-k, design-for-manufacturing (DFM) and other technologies.

IC design and manufacturing costs began to soar. As the complexity and cost escalated at each process node, it was no longer a clear-cut decision to follow the natural cadence of process nodes. Chipmakers weighed the various technical and economic trade-offs.

Starting at 90nm, node skipping among chipmakers became the rule instead of the exception. For example, Netronome is currently shipping communications processors based on a 65nm process from TSMC. Instead of moving to 40nm or 28nm, Netronome recently decided to make a giant leap from 65nm to Intel’s 22nm finFET foundry technology. The decision, according to Netronome, was based on density, power consumption and cost.

Node skipping is expected to reach new heights at the 20nm planar process. The so-called “time-to-market” IC makers, such as AMD, Altera, Nvidia, Qualcomm, Samsung, and Xilinx, likely will make the traditional progression from 28nm to the 20nm planar node before moving to finFETs.

Many of the so-called fast-followers, such as Broadcom, Freescale, Marvell and LSI, are still on the fence. At a recent event, for example, a Marvell representative questioned the feasibility of the 20nm planar node, saying the technology has a “negative ROI.”

Previously, foundries offered several different process derivatives at a given leading-edge node. But at 20nm, GlobalFoundries, Samsung and TSMC will offer only one leading-edge process, thereby providing customers with fewer choices.

The 20nm planar node also brings some new and challenging technologies to the mix, such as double patterning and the introduction of a third layer of local interconnects called the middle-of-the-line. At 20nm planar, there is a performance boost over 28nm, but the transistor speeds slow down as operating voltage is reduced.

IC makers that moved from 40nm to 28nm have experienced a 35% average increase in speed and a 40% power reduction, said Jack Sun, vice president of R&D and chief technology officer at TSMC. In comparison, IC vendors that will move from 28nm to 20nm planar are expected to see a 15% increase in speed and 20% less power, Sun said.

With that in mind, there is a temptation to skip 20nm and migrate to finFETs. FinFETs take the traditional 2D planar design and turn the conductive channel on its side, resulting in a 3D “fin” structure surrounded by a gate that controls the flow of current.

Compared to 32nm planar, finFET transistors enable a 37% performance increase at low voltages and a power reduction of 50% or more, according to Intel. Intel’s own Tri-Gate transistor enables a steeper sub-threshold slope at around 80 mV/decade or below, compared to 100 mV/decade for leading-edge planar transistors, said Mark Bohr, senior fellow at Intel, at a recent event.

“Vdd scaling has slowed down. Leakage is an issue as geometries shrink,” said Srinivas Nori, director of SoC marketing at GlobalFoundries. “The value (that finFETs) bring is that it enables one to lower the Vdd. Leakage is better controlled. The variation of the Vt is also much better controlled.”

The benefits are easy to grasp, but the hard part is obvious. “If I was a designer, I would be worried,” said Horacio Mendez, executive director of the SOI Industry Consortium, a group that is promoting SOI. “If you go back to the standard way of doing things in bulk, and you want a transistor with a different Vt and that drives a different current, you printed different line widths. You just made a fatter transistor. And you paid a little a bit of a penalty in the capacitance,” Mendez said. “How the heck can do you that in finFETs? It’s impossible. So, to make finFETs, you go in quantum steps. The way you actually do this is that you put down one fin, two fins or three fins on a structure.”

Besides the quantum issues, there are other problems. “The fin height is now a huge variable. In a junction-isolated fin, I don’t know how that is accurately controlled. So, from my perspective, this is a tricky thing for an SoC guy to get around. I would imagine you would need pretty stiff design rules to account for this,” he said.

Because of fin height variability, there are fears that the foundries could struggle making bulk finFETs with any consistency. The SOI proponents are pushing fully-depleted SOI (FD-SOI), claiming the technology can reduce the process steps and variability with little or no cost penalty.

New roadmaps
The foundries are still pushing bulk, but they have changed their roadmaps. In September, GlobalFoundries rolled out its finFET technology, dubbed 14nm-XM, based on a “modular fin” approach. GlobalFoundries opted to marry a 14nm front-end fin with a 20nm planar BEOL flow. In doing so, the company has accelerated its finFET process by a year. Product tape-outs are expected in 2013, with production slated for 2014.

“Today, customers, IP vendors and the whole ecosystem can actually start working on finFETs,” said Subramani Kengeri, head of advanced technology architecture at GlobalFoundries. “There are about 7,000 design rules that will carry over from 20nm planar to finFET. From a design point of view, the very early PDKs are almost the same as 20nm.”

Earlier this year, TSMC thought 20nm planar would become a popular node and announced a 20nm pilot line to prepare for the big ramp. But initial 20nm demand is lukewarm. TSMC claims to have 50 tape-outs for the technology, roughly one-fifth compared to that of 28nm.

TSMC’s 20nm pilot line is still on track for 2013. But last month TSMC accelerated its finFET risk production schedule from February 2014 to November 2013. Mass production is slated a year after its 20nm planar process. “This is a somewhat faster cadence than the previous generation,” TSMC’s Chang said.

Meanwhile, UMC said it has developed 20nm planar capability, but the company is not pursuing it as a mainstream process offering. Instead, it is more or less skipping 20nm and pursing finFETs. “After 28nm, finFET will be our focus,” said Shih-Wei Sun, chief executive of UMC, during a recent conference call.

By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss future lithography challenges with Juan Rey, senior director of engineering at Mentor Graphics; Aki Fujimura, chairman and chief executive at D2S; and Tatsuo Enami, general manager for the sales division at Gigaphoton. What follows are excerpts of that conversation.

SMD: What is the general state of the next-generation lithography (NGL) arena?
Fujimura: I have been in the industry for a long, long time. There have not been this many alternatives that have a chance for success. It’s definitely an interesting time.

SMD: But EUV is clearly late. Does the industry need to allocate more R&D dollars to the various NGL technologies beyond EUV?
Fujimura: Yes. There should be more investment in all areas. Unfortunately, semiconductors in general are not really a fit for a pure venture capital model. It’s too expensive and the returns on any individual bet are not high enough. So it has to be the larger companies that step up and create a fund, or maybe even some kind of joint fund. That’s probably not going to happen. The larger companies may need to collaborate somehow, probably quietly, and voting with their dollars. Don’t just vote on the top one. Vote on several alternatives.
Rey: I agree. I am absolutely convinced that more money is required, because the challenges are bigger. In fact, the need for increased functionality is everywhere. The standard way of actually getting that increased functionality is really becoming a lot more difficult by following the standard path. It is a lot more difficult to do patterning today. There is also a transition toward finFETs, SOI, fully depleted SOI or some other technique. There are other things that are required at the transistor level. It is getting more difficult everywhere.

SMD: What other challenges do you see?
Rey: For example, in the data communications path, there is a need for transmitting more data with lower power and cost. I mentioned silicon photonics because it is a technique that seems to offer the potential for much larger bandwidth for the same amount of power as copper at shorter distances. But no one knows how do to it at a cost that is feasible at this moment. The industry is starting to respond in a very interesting direction. Interestingly enough, the silicon photonics conferences were once attended exclusively by physicists. Now you have keynote presenters from companies like Facebook and Google. So you can see that the large companies that have needs in that direction are paying attention to what’s happening with the technology. The industry as a whole requires more investment from the companies that are getting the benefits of having a path towards more functionality per unit area. Hopefully, they will follow with the funding that is required to bring some of these technologies forward. The industry at a higher level needs to get involved with the technology to enable what customers want.
Fujimura: And let’s take cell phones. For the most part, they still don’t work. You can’t rely on the cell phone to give you a reliable connection. There is a lot more that can be done. We need a lot more and better technology.

SMD: Let’s get back to lithography and EUV. When will EUV finally move into production?
Enami: At the 14nm node in 2016.

SMD: What does Gigaphoton’s EUV source roadmap look like?
Enami: The industry target is to have a 50-watt source in 2015 or so. This is because 2016 is the target for the mass production of DRAMs with EUV. Our milestone, of course, is to reach 50 watts. Our current source is operating at around a few watts. Within this year, we want to achieve 20 watts. In Q1 of next year, we need to reach 50 watts. And if possible, at the end of next year, we want to reach 100 watts. A 100-watt source can produce around 60 to 70 wafers per hour. If we can reach 100 watts by the end of next year, we can provide a source to the customer by 2014 or 2015.

SMD: What’s going on with laser light sources for traditional 193nm lithography?
Enami: We are doing both EUV and deep UV sources. Of course, the laser for DUV is working at the 60-watt level today. That translates to 175 wafers per hour. The recent ASML scanner hopes to reach 200 wafers an hour. That requires 90 watts of power. The actual multi-patterning scanner requires 120 watts in one or two years. We are also developing 120-watt lasers. We’ve almost achieved that target. In production, a 120-watt source power can be applied for 450mm scanners. For deep UV laser sources, multi-patterning requires more R&D dollars. Customer requirements are very tough. Even for DUV lasers, they want cheaper, more durable and higher-availability technologies.

SMD: Do you see other challenges with EUV beyond the source?
Fujimura: EUV needs very accurate masks. If the mask is not accurate, it will show up on the wafer.
Rey: Defects on EUV mask blanks can’t be completely eliminated. That is extremely disruptive. Given that this is the case, what can be done at any part of the design flow to compensate for that? It is possible to find solutions for it. But it is not easy to determine today if there are going to be practical approaches to that. Essentially, you need to know something about the design to be able to use a mask. In this case, you don’t know where the defects are, but you still need to use the mask for that design. That is not something any manager in the food chain wants to deal with. People are starting to scratch their heads about this issue, but nobody seems to be too willing to embrace it. It will be interesting to see how Intel, IBM and TSMC are going to deal with it.

SMD: Will DSA make it into chip production?
Fujimura: I say positively yes.
Rey: I have a positive feeling about DSA. So far, the whole infrastructure that exists today for doing the creation of the shapes for the actual mask seems to be similar. But with DSA, it seems like new models need to be adapted. They need to be proven that they can work in terms of memory consumption, speed and scalability at full-chip level. If you look at it, all of the techniques applied today are essentially based on the resolution limits of photolithography. In the beginning, it was possible to print something very close that was drawn. With the exception of source-mask optimization, pretty much everything follows that key concept. For example, you want to print a rectangle. You start with a rectangle and you see how much you need to modify it. When you apply the model, it predicts how the rectangle is going to be printed. The modifications we’ve seen in DSA are much larger than that.

SMD: Can EUV play a role to help DSA?
Enami: DSA does require guide patterns. To make the guide patterns, you need traditional lithography or EUV.

SMD: If all else fails, the industry can move to multiple patterning. Are EDA tools ready for multiple patterning?
Rey: The tools can be extended. If we go from double patterning to triple patterning, the complexity is a lot larger. But the expectation is that hopefully you won’t need triple patterning everywhere. The algorithms are too complex. There are flow approaches to make the tools feasible. From a conceptual point of view, they are well understood. But not all the tools at full-chip level are completely ready. They are in the process of being developed.

By Mark LaPedus
In the late 1990s, a group led by Intel launched a consortium to propel extreme ultraviolet (EUV) lithography into the mainstream.

Originally, the consortium, dubbed the EUV LLC, envisioned the advent of EUV scanners that would move into production at the 65nm node. Clearly, the now-defunct consortium underestimated the difficulties and challenges associated with EUV.

ASML Holding, the sole EUV tool supplier, has experienced ongoing delays and problems with the technology. EUV is tardy for the 14nm node and could possibly miss the 10nm window. And there are also signs that ASML’s EUV customers, and its new investors, are becoming increasingly impatient regarding the delayed delivery schedules for EUV.

Many blame the delays on the EUV power source. For years, Cymer, the key developer of EUV sources, has struggled to meet its specified targets. The other EUV source suppliers, Gigaphoton and Xtreme, are also behind.

In a drastic step to solve the lingering problem, ASML has entered into a definitive agreement to acquire Cymer for $2.6 billion. Despite the acquisition, ASML still faces some challenges to get Cymer’s EUV source efforts back on track.

And that’s only the tip of the iceberg. Lost in the shuffle are the ongoing issues with the EUV mask blanks, pellicles, resists and other parts of the supply chain.

The source of the problem
It is unlikely that ASML, and its customers, will pull the plug on EUV in the near term. The industry has poured billions of dollars into EUV. Recently, for example, Intel invested some $4.1 billion in ASML, as part of an effort to raise the overall confidence level in EUV and the 450mm wafer transition. TSMC and Samsung also recently invested in the Dutch-based lithography giant for similar reasons.

Intel and others have backed EUV for years. In the 1990s, there were fears that optical lithography would run out of gas, prompting the need for a next-generation lithography (NGL) technology. More recently, EUV became the leading NGL candidate. The other NGLs, maskless lithography and nanoimprint, are lagging behind.

Compared to optical lithography, EUV is a radically different technology. Using a 13.5nm wavelength, EUV is a soft X-ray technology in which the processing steps take place in a vacuum chamber. EUV also uses defect-free mirrors that reflect light via interlayer interference.

There are three types of EUV source technologies: laser-produced plasma (LPP), discharge-produced plasma (DPP) and a hybrid approach. In LPP, plasma is generated by a focused laser pulse hitting an appropriate target material. In DPP, the plasma is generated within an electrode system by an electrical discharge in the gas phase. Laser-assisted discharge plasma (LDP) is the hybrid technology. For the commercial market, Cymer and Gigaphoton are working on LPP technology, while Xtreme is developing an LDP source.

Meanwhile, ASML is expected to ship its NXE:3300B, its first EUV production tool, later this year. In January, ASML promised an acceptable throughput of 69 wafers an hour (wph) for the tool. In the future, ASML has said it needs to reach 250 watts of average source power to achieve the 125 wph throughputs sought by its customers.

In a recent interview, Yan Borodovsky, an Intel senior fellow and director of advanced lithography at the Technology and Manufacturing Group in Portland, said that EUV source power needs to be in the range of 1,000 watts for patterning the contact holes. This is partly due to the much slower resists required for good contact hole patterning. Contact resists must be in the range of 60 to 70 milliJoules/cm(2).

But amid ongoing delays for the EUV light source from Cymer, ASML recently lowered its targets and promised a throughput in the “30ish” range in terms of wph in 2012. Right now, however, Cymer’s EUV light source has been exposing wafers at up to 11 Watts in power, resulting in 7 wph for the NXE:3100. The NXE:3100 is a pre-production EUV machine.

In the lab, ASML and Cymer have demonstrated a sustained 30-watt source exposure power potential, which would enable the NXE:3300B to expose 18 wafers per hour. ASML’s specified target remains at 105 Watts, or 69 wph, to be achieved for 2014 production.

Clearly, ASML’s acquisition of Cymer is aimed to accelerate the development of EUV and the sources. ASML’s expertise in lithography systems design and integration supposedly will reduce the risk and accelerate the introduction of this technology.

Going forward, ASML faces an uphill battle. “Regarding field performance, Cymer highlighted an average power of 9 to 13 Watts, droplet stability of better than 0.5%, and 60% source availability, enabling 100 wafer throughput per day,” said C.J. Muse, an analyst at Barclays Capital, in a research note prior to the acquisition. “We note that the 60% source availability is down from 70% in the prior two quarters, suggesting progress is still slow here.”

Cymer has been able to improve the tin droplet stability with a new steering mechanism. “As for downside, Cymer is still not able to show equal to or better than 0.2% dose stability as per ASML’s specs,” Muse said. On its roadmap, Cymer hopes to deliver a 20 watt source, with a <0.5% dose stability and a 90% duty cycle by year’s end. By mid-2013, Cymer plans to have a 40 to 60 watt source at less than 0.5% dose stability.

Like Cymer, the other EUV source providers are struggling. “Xtreme has apparently resolved the reliability issues, but power scaling remains a focus,” Muse said. “And Gigaphoton continues to make incremental progress, though an integrated real pilot tool is not scheduled to be released until 2013.”

Forgotten pieces in the puzzle
The source has garnered most of the attention, but there are also other challenges. One forgotten piece of the EUV puzzle is the pellicle. EUV masks do not make use of a protective pellicle, which could introduce undesirable and killer defects in the flow. “That also means the mask life may be shorter,” said Banqiu Wu, principal member of the technical staff and chief technology officer for the Mask and TSV Etch Division at Applied Materials.

Stefan Wurm, the director of Sematech’s lithography program, raised another concern: There are problems with EUV mask blanks. “I am much more worried about the mask issue,” Wurm said at a recent event. A Sematech assignee, Wurm is also a principal member of the technical staff at GlobalFoundries.

EUV mask blanks have MoSi multilayers. They must be free of defects and particles to a much higher degree than today’s mask substrates. There are only two mask blank suppliers, Asahi Glass and Hoya. And only one fab tool vendor, Lasertec, is developing an EUV blank inspection tool.

“If you look at blank inspection, that’s a big issue,” said Franklin Kalk, executive vice president and chief technology officer at Toppan Photomasks. “How many mask blank companies are there? There might be two. How many inspection tools do they need? They only need a couple. How do you make a business of blank inspection tools for EUV if you are never going to sell more than five? That’s a tough business model.”

For some time, the industry has also come to the troubling realization: EUV mask blanks will have defects in some form or another. “We will always have defects on our blanks,” Kalk said. “Therefore, we will need to manage those defects.”

In one strategy, mask makers will first map the defects for an EUV blank. Then, they will pattern around the defects to avoid them. “I think it would be prudent to use fiducial marks on the blanks and do two separate blank inspections. You would inspect the multilayer and then put down the absorber stack and then re-inspect it. Then, you map all those defects,” he said.

Then, there are several ways of writing around the defects. “One is that you shift the pattern. You basically bury the multilayer defects under the dark areas, where the absorber won’t be removed. Or, if you can’t do that, and you know that a defect is going to fall in an area that’s written, then you write in such a way that the defect still doesn’t print on the scanner,” he said. “The alternative, of course, is after you’ve written the pattern, you go in and inspect. And then you repair.”

Like the EUV power source, the EUV blank inspection, pattern inspection, repair and related tools must be ready in time. “That whole strategy of managing defects is going to be the key issue for masks,” Kalk said. “The tools and the defect-management strategy are not trivial.”