Posts Tagged ‘14nm’
By Ed Korczynski, Sr. Technical Editor
In another example of the old one-liner that “all that is old is new again,” the old technique of solid-source doping is being used by Intel for a critical process step in so-called “14nm node” finFET manufacturing. In the 7th presentation in the 3rd session of this year’s IEDM, a late news paper written by 52 co-authors from Intel titled “A 14nm Logic Technology Featuring 2nd-Generation FinFET Transistors, Air-Gapped Interconnects, Self-Aligned Double Patterning and a 0.0588m2 SRAM Cell Size” disclosed that solid source doping was used under the fins.
As reported by Dick James of Chipworks in his blog coverage of IEDM this year, the fins have a more vertical profile compared to the prior “22nm node” and are merely 8nm wide (Fig. 1). Since Intel is still using bulk silicon wafers instead of silicon-on-insulator (SOI), to prevent leakage through the substrate these 8nm fins required a new process to make punch-through stopper junctions, and the new sub-fin doping technique uses solid glass sources. Idsat is claimed to improve by 15% for NMOS and 41% for PMOS over the prior node, and Idlin by 30% for NMOS and 38% for PMOS.
Solid glass sources of boron (B) and phosphorous (P) dopants have been used for decades in the industry. In a typical application, a lithographically defined silicon-nitride hard-mask protects areas from a blanket deposition in a tube furnace of an amorphous layer containing the desired dopant. Additional annealing before stripping off the dopant layer allows for an additional degree of freedom in activating dopants and forming junctions.
In recent years, On Semiconductor published how solid-source doping on the sidewalls of Vertical DMOS transistors enable a highly phosphorous doped path for the drain current to be brought back to the silicon surface. The company shows that phosphorous-oxy-chloride (POCl) and phospho-silicate glass (PSG) sources can both be used to form heavily doped junctions 1-2 microns deep.
The challenge for solid-source doping of 8nm wide silicon fins is how to scale processes that were developed for 1-2 microns to be able to form repeatable junctions 1-2 nm in scale. Self-aligned lithographic techniques could be used to mask the tops of fins, and various glass sources could be used. It is likely that ultra-fast annealing is needed to form stable ultra-shallow junctions.
Intel is notoriously protective of process Intellectual Property (IP) and so has almost certainly ensured that any equipment and materials suppliers who work on the solid-source doping process sign Non-Disclosure Agreements (NDA) with amendments that forbid acknowledging signing the NDA itself, so it is pointless to directly ask for any further details at this point. However, slides from John Borland’s recent presentation at the NCCAVS Junction Technology Users Group meeting provide a great overview of the publicly available information on finFET junction formation, and include the following:
…higher dopant activation can be realized at low temperatures if the junction is amorphous and recrystalized by using SPE (solid phase epitaxy) recrystalization of the junction as also shown in the data by Intel.
Also seen at IEDM this year in the 7th presentation of the Advanced Process Modules section, Taiwanese researchers—National Nano Device Laboratories, National Chiao Tung University, and National Cheng Kung University—joined with Californian consultants—Current Scientific, Evans Analytical Group—to show “A Novel Junctionless FinFET Structure with Sub-5nm Shell Doping Profile by Molecular Monolayer Doping and Microwave Annealing.” They claim an ideal subthreshold swing (~60 mV/dec) at a high doping level. Poly-Si n & p JLFinFETs (W/L=10/20 nm) with SDP experimentally exhibit superior gate control (Ion/Ioff >10E6) and improved device variation.
Contour Semiconductor, Inc. announced it has been awarded three new patents to back its Diode Transistor Memory (DTM) technology, the world’s lowest production-cost, non-volatile memory technology.
Fujitsu Semiconductor America announced that Shinichi “James” Machida, who led the company from late 2008 until spring of 2011, has been named as the new president and CEO of FSA.
ProPlus Design Solutions announced Samsung Electronics has extended its partnership with ProPlus through the deployment of ProPlus’ BSIMProPlus modeling platform for its 14nm FinFET SPICE modeling.
Analog Devices, Inc. introduced the first and only MEMS gyroscope specified to withstand temperatures of up to 175 degrees Celsius commonly encountered by oil and gas drilling equipment.
GLOBALFOUNDRIES, a provider of advanced semiconductor manufacturing technology, announced that Louis “Lou” Lupin has joined the company as senior vice president and chief legal officer.
Credo Semiconductor announced the appointment of Jeff Twombly as vice president of sales and business development.
Taiwanese chipmakers, LED manufacturers, and Outsourced Semiconductor Assembly and Test (OSAT) firms will spend firm nearly $24 billion in the next two years on equipment and materials, powering excitement for SEMICON Taiwan 2014, which opened this week in Taipei.
United Microelectronics Corporation and Fujitsu Semiconductor Limited announced an agreement for UMC to become a minority shareholder of a newly formed subsidiary of Fujitsu Semiconductor that will include its 300mm wafer manufacturing facility located in Kuwana, Mie, Japan.
Rudolph Technologies, Inc. announced that the SUNY College of Nanoscale Science and Engineering (CNSE), Albany, NY, has selected its Discover Enterprise Yield Management Software (YMS) to provide an integrated data warehouse and analytics system for the Global 450 Consortium (G450C) equipment development program.
By Ed Korczynski and Pete Singer, SemiMD and Solid State Technology
Fabless companies could skip the 20nm node and move straight to 14nm FinFETs. That is the hope of GLOBALFOUNDRIES and Samsung who are announcing a joint program that offers a single process design kit (PDK) and manufacturing at four different fabs with identical processes. The PDKs are available now, and 14nm manufacturing could move into high volume production by the end of the year.
“This is unprecedented,” said Kelvin Low, senior director of marketing at Samsung. “It never has happened in the industry, especially at the very leading edge nodes. We are confident that this will transform the supply chain model,” he added.
Fabless companies such as Qualcomm have been lobbying for such multi-sourcing for some time, and are eager to move to FinFETs which offer higher performance and reduced power consumption. 14nm FinFETs offer a 20% improvement in performance and a 35% reduction in power compared to 20nm technology.
“For both Samsung and GLOBALFOUNDRIES, we will be providing our customers with a choice and assurances of supply, enabled by the unprecedented global capacity across our respective manufacturing facilities throughout different locations worldwide,” Low said. “For Samsung, we have facilities in the U.S. in Austin. We also have a couple of plants in Korea. For GLOBALFOUNDRIES, the 14 nm capacity will be in Malta, NY.”
The single process design kit will allow customers to do a single design that is capable of being multi-sourced from different locations.
“This really is a change from the existing supply chain model where customers are trying to design multiple designs to multi-source their products,” Low said. “True design compatibility in this collaboration will allow customers to better manage their design NRE and they can focus on bringing the product to market on time. Both companies see this as a necessary advancement of the supply chain model and we start off with the 14nm LPE as well as the 14nm LPP technology node.” 14nm LPP is a follow-on offering which has additional performance enhancements as well as power reduction attributes.
Samsung had already developed much of the process technology for LPP and LPE flows to run using 14nm node finFETs, while GLOBALFOUNDRIES was working independently on another 14nm node process variant. The two companies decided to pool resources to save both time and money in bringing 14nm node finFET capability to the commercial IC foundry market.
“Because of customer interest in having that assurance of supply and being able to do one GDS and being able to work off of one common PDK and source at both of our companies, we decided to work together and go with the 14 LPE and 14 LPP as common offerings between Samsung and GLOBALFOUNDRIES,” said Ana Hunter, VP of product management at GLOBALFOUNDRIES.
Low said that Samsung is already running 14nm products in its fab in Korea. The 14nm LPE, for example, was qualified earlier this year.
“We are already in silicon validation of our lead customer products. We expect to ramp production by the end of this year,” he said. Design activities started almost three years ago. “Right now, we are seeing a lot more pickup overall by the lead adopters and even other customers following suit, mainly because the marketplace does see that the 14nm FinFET is at the right maturity level for volume production,” Low said.
Although there is still lot of activity at 28nm, the technology is considered to be in a mature phase. “We still continue to see healthy, new design-ins,” Low said. “Of course, there are a lot of requests to see what additional enhancements we can do at our 28nm node to prolong the lifespan of that node.”
What about 20nm? “From Samsung’s viewpoint, we see that a relatively short-lived node, mainly because of the overall resonance of FinFETs and the eagerness of customers to migrate from 28nm directly to 14nm FinFETs.”
Hunter agrees, noting that 28nm has been in high volume production for several years now. She said GLOBALFOUNDRIES does have 20nm product tapeouts running in the line, but said that she does not see 20nm being a very extensive node in that most customers are eager to get onto FinFETs.
“We do have products running at 20nm, but I think the design efforts will quickly go over to FinFET and we’ll see that be a much longer lived node with a lot more product tapeouts,” she said.
The companies say the 14nm FinFET offering could be up to 15% smaller than that available from other foundries due to aggressive gate pitch, smaller memory solution and innovative layout schemes for compact logic.
Hunter, having been a VP at Samsung before holding her current position at GLOBALFOUNDRIES, noted that the two companies, along with IBM, have been in collaboration for quite some time on “The Common Platform” at 65, 45, and 28nm nodes, but this announcement is strictly between GF and Samsung.
“We do continue to work with IBM in other areas at the Albany Nanotech center, where there is continuing collaboration on more advanced nodes, on materials research, pathfinding, and advanced module development kind of work,” she said.
Fabless customers use a single PDK to do a single design, allowing a single GDS file to be sent to either company. The design-for-manufacturing (DFM) and reticle-enhancement technologies (RET) needed at the 14nm node are challenging.
“We go deep into the collaboration, even to the OPC level and a lot of sharing on DFM as well. It is a very extensive collaboration,” confirmed Hunter. “At 14nm the designs are extremely complex, and to be able to truly supply multi-sourcing from one GDS, you have to have that level of collaboration to ensure that the output from all of our factories is the same. That’s a huge advantage to customers because the idea that you could source from two different companies without the kind of collaboration that GLOBALFOUNDRIES and Samsung are doing is just simply impossible when you get into 14nm FinFETs. When you get into the complexity of the designs, the databases, the amount of reticle enhancement techniques that are required to be able to print these geometries, you need to have that kind of in-depth collaboration.”
Low said that the two companies have a “fabsync” structure running in the background to ensure the fabs are fully synchronized.
“There are a couple of things we are doing proactively,” he said. “The technology teams are deeply engaged with each other. We have technology workshops across both companies. We have test chips that are run regularly to ensure that the process continues to stay synchronized. These test chips are not just simple transistors. We have product level elements that we’ve included to make sure we measure the critical parameters. This is only enabled through open sharing of technology information.”
Hunter adds: “We run the same test chips, we share wafers back and forth to measure each other’s products to make sure all of our equipment is calibrated, test equipment calibrated, results are the same on exactly the same test chip.We have test-chips with product-level structures that run in all fabs and both companies share all data to ensure that all fabs stay in alignment. Not just SPICE models and SRAMs, but full chip-like design features.”
However, customers will have to re-do lithography masks if they want to move manufacturing from one company to the other, in part because of issues with shipping masks. Kevin Low, Samsung’s senior director of marketing, commented, “We’ll be providing our customers choice and secure supply. At Samsung we have capacity in Texas and Korea.”
Cost/transistor for 14nm may not be lower compared to 20nm and 28nm. Hunter said, “To continue with optical lithography, it is challenging to do double-patterning and keep costs low.” However, since much of the motivation in moving from 20nm to 14nm is for power-sipping mobile SoCs, by reducing the power consumption by the claimed 35% there could be cost-savings at the packaging level such that the overall product cost is reduced.
To be able to offer essentially the same manufacturing process to customers, GLOBALFOUNDRIES and Samsung had to harmonize not just process recipes but many of the OEM tools used in these fabs.
Hunter says, “To get the same results at this node, it does require engineering down to the tool level and the individual recipe level. That doesn’t mean all tools are exactly the same, however, since cost and availability of tools may have been different when the fabs were equipped.”
Customers can choose which foundry that choose to work with, and then they can choose to discuss commercial terms such as which specific foundry site may be booked to do the work.
New blogs delve into the packaging technology of Apple’s A7, the road ahead for bulk FinFETs as defined by imec, with EUV is a gating factor for 450mm, split-manufacturing for U.S. trusted IC (TIC) program and Japan’s growing market for equipment and materials.
For the 10nm node and beyond, transistor research efforts are focused on high mobility designs with Ge and III-V channel, reducing VDD supply voltage as well as the subthreshold slope in transistors and optimizing multi-Vt designs. Pete Singer reports on work underway at imec in Belgium.
At the IEEE 3DIC in San Francisco Dan Radack of the Institute of Defense Analysis gave an update on the IARPA trusted Integrated Chip Program. Phil Garrou reports how it is now focused on split-manufacturing with FEOL done off-shore and BEOL done by trusted facilities in the U.S.
The A7 is manufactured by Samsung on a high-κ metal gate (HKMG) 28 nm process and the chip includes over 1 billion transistors on a die 102 mm2 in size. Phil Garrou reports on observations on the Package-on-Package (PoP) design as noted by fellow blogger Dick James. In an earlier blog, Dick described how the Apple A7 is using Samsung’s 28nm process.
Simon Favre of Mentor Graphics notes how EUV could possibly be a gating factor for 450mm. “Would you put in 450mm immersion steppers, and then yank them out to put in EUV before they’re fully depreciated?” he asks.
In advance of Semicon Japan, to be hold December 4-6 at the Makuhari Messe, SEMI’s Dan Tracy and Yoichiro Ando report that restructuring and consolidation has led to a new focus for the semiconductor manufacturers in Japan. As a result, the semiconductor equipment market in Japan will experience double-digit growth in both 2013 and 2014, driven by higher spending for memory production and in spending increases planned for the manufacturing of power semiconductors and “More than Moore” semiconductor technologies. Total equipment spending in Japan is estimated to reach $4.6 billion by 2014. Combining this with the $8 billion-plus spending on semiconductor materials, Japan represents a $12 billion market in 2014 for the suppliers of equipment and materials.
The readiness of EUV lithography is later than hoped, but appears to be on time for insertion into the 10nm node, which is slated to go into production in late 2015/early 2016. “I’m very convinced that very soon EUV will be ready to enter manufacturing,” said Luc Van den hove, president and CEO of imec, as reported by Pete Singer.
In an earlier blog, Veeco’s Tim Pratt, Senior Director, Marketing, said that indeed the next major roadblock to progress in the ongoing push to develop EUV lithography for volume production is the availability of defect-free mask blanks. He said that the tools in place today are not capable of producing mask blanks with the kind of yield necessary to support a ramp in EUV.
Meanwhile, results from early work into directed self-assembly (DSA) is quite promising. DSA could be used in conjunction with EUV for the 7nm node, scheduled to go into production in the 2017/2018 timeframe. Work at imec has shown that the polymers, with a hard mask on top, are robust enough to enable the etching of the patterns into silicon. “That’s fairly new data and very promising,” said An Steegen, senior vice president of process technology at imec.
EUV readiness also been the focus of several blogs by Vivek Bakshi. Earlier this year, he predicted that 50 W sources will be ready and working in NXE3300B sometime in 2014, corresponding to 43 WPH throughput. 100 W sources will be ready in 2015 or 2016 corresponding to 73 WPH. “The readiness of 250 W EUV sources cannot be safely predicted, unless we see 100 W sources ready and have identified the issues to ensure that they are no showstoppers. I am not convinced that present approaches can get to 500 W sources. It is easy to put them on roadmaps, but delivering them is another question,” he said.
Intel is far ahead of anyone else when it comes to putting 14nm devices into production. However, even Intel finds it challenging. Speaking on a quarterly call with analysts, newly elected CEO Brian Krzanich said 14nm rollout was “about a quarter behind our projections.” He said defects were the problem. “As a result, we are now planning to begin production in the first quarter of next year,” as Pete Singer reported.
Intel already has 3D finFETs in production, and FinFETs will likely become the logic technology of choice for the upcoming generations, with high mobility channels coming into play for the 7 and 5nm generation (2017 and 2019).
Brian Krzanich also said that Intel remained committed to the transition to 450mm wafers, saying: “We have not changed our timing. We are still targeting the second, latter half of this decade.” At Semicon Europa week, Paul Farrar, general manager of G450C, provided an update on the consortium’s progress in demonstrating 450mm process capability. He said 25 tools will be installed in the Albany cleanroom by the end of 2013, progress has been made on notchless wafers with a 1.5mm edge exclusion zone, they have seen significant progress in wafer quality, and automation and wafer carriers are working.
Phil Garrou reports on developments from Semicon Taiwan 2013 of interest to the IC packaging community. The Market Trends Forum chaired by Dr. Burn Lin of TSMC, included a report on DRAM Status (continued consolidation) by Charlie Chan of Morgan Stanley; Nicolas Gaudois Managing Director of UBS Investment Research looked at the “The End of the High End Smartphones Run,” and Dan Tracy of SEMI provided the Packaging Materials Outlook.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing. To find out more about what’s changing in this area and why it’s so important, click here.
The introduction of EUV lithography into the semiconductor fabrication process will enable a continuation of Moore’s law below the 22 nm technology node. EUV lithography will, however, introduce new and unwanted sources of patterning distortions which must be accurately modeled and corrected on the reticle. Flare caused by scattered light in the projection optics is expected to result in several nanometers of on-wafer dimensional variation, if left uncorrected. Previous work by the authors has focused on combinations of model-based and rules-based approaches to modeling and correction of flare in EUV lithography. This paper focuses on the development of an all model-based approach to compensation of both flare and proximity effects in EUV lithography. The advantages of such an approach in terms of both model and OPC accuracy will be discussed. In addition, the authors will discuss the benefits and tradeoffs associated with hybrid OPC approaches which mix both rules-based.
To view this white paper, click here.
Graphene meets heat waves; UT Dallas technology could make night vision, thermal imaging affordable; Breakthrough in OLED technology
A new spin on spintronics; Novel solid-state nanomaterial platform enables terahertz photonics; Novel crumpling method takes flat graphene from 2-D to 3-D
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.