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Posts Tagged ‘10nm’

5nm Node Needs EUV for Economics

Thursday, January 29th, 2015

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By Ed Korczynski, Sr. Technical Editor

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At IEDM 2014 last month in San Francisco, Applied Materials sponsored an evening panel discussion on the theme of “How do we continue past 7nm?” Given that leading fabs are now ramping 14nm node processes, and exploring manufacturing options for the 10nm node, “past 7nm” means 5nm node processing. There are many device options possible, but cost-effective manufacturing at this scale will require Extreme Ultra-Violet (EUV) lithography to avoid the costs of quadruple-patterning.

Fig. 1: Panelists discuss future IC manufacturing and design possibilities in San Francisco on December 16, 2014. (Source: Pete Singer)

Figure 1 shows the panel being moderated by Professor Mark Rodwell of the University of California Santa Barbara, composed of the following industry experts:

  • Karim Arabi, Ph.D. – vice president, engineering, Qualcomm,
  • Michael Guillorn, Ph.D. – research staff member, IBM,
  • Witek Maszara, Ph.D. – distinguished member of technical staff, GLOBALFOUNDRIES,
  • Aaron Thean, Ph.D. – vice president, logic process technologies, imec, and
  • Satheesh Kuppurao, Ph.D. – vice president, front end products group, Applied Materials.

Arabi said that from the design perspective the overarching concern is to keep “innovating at the edge” of instantaneous and mobile processing. At the transistor level, the 10nm node process will be similar to that at the 14nm node, though perhaps with alternate channels. The 7nm node will be an inflection point with more innovation needed such as gate-all-around (GAA) nanowires in a horizontal array. By the 5nm node there’s no way to avoid tunnel FETs and III-V channels and possibly vertical nanowires, though self-heating issues could become very challenging. There’s no shortage of good ideas in the front end and lots of optimism that we’ll be able to make the transistors somehow, but the situation in the backend of on-chip metal interconnect is looking like it could become a bottleneck.

Guillorn extolled the virtues of embedded-memory to accelerate logic functions, as a great example of co-optimization at the chip level providing a real boost in performance at the system level. The infection at 7nm and beyond could lead to GAA Carbon Nano-Tube (CNT) as the minimum functional device. It’s limited to think about future devices only in terms of dimensional shrinks, since much of the performance improvement will come from new materials and new device and technology integration. In addition to concerns with interconnects, maintaining acceptable resistance in transistor contacts will be very difficult with reduced contact areas.

Maszara provided target numbers for a 5nm node technology to provide a 50% area shrink over 7nm:  gate pitch of 30nm, and interconnect level Metal 1 (M1) pitch of 20nm. To reach those targets, GLOBALFOUNDRIES’ cost models show that EUV with ~0.5 N.A. would be needed. Even if much of the lithography could use some manner of Directed Self-Assembly (DSA), EUV would still be needed for cut-masks and contacts. In terms of device performance, either finFET or nanowires could provide desired off current but the challenge then becomes how to get the on current for intended mobile applications? Alternative channels with high mobility materials could work but it remains to be seen how they will be integrated. A rough calculation of cost is the number of mask layers, and for 5nm node processing the cost/transistor could still go down if the industry has ideal EUV. Otherwise, the only affordable way to go may be stay at 7nm node specs but do transistor stacking.

Thein detailed why electrostatic scaling is a key factor. Parasitics will be extraordinary for any 5nm node devices due to the intrinsically higher number of surfaces and junctions within the same volume. Just the parasitic capacitances at 7nm are modeled as being 75% of the total capacitance of the chip. The device trend from planar to finFET to nanowires means proportionally increasing relative surface areas, which results in inherently greater sensitivity to surface-defects and interface-traps. Scaling to smaller structures may not help you if you loose most of the current and voltage in non-useful traps and defects, and that has already been seen in comparisons of III-V finFETs and nanowires. Also, 2D scaling of CMOS gates is not sustainable, and so one motivation for considering vertical transistors for logic at 5nm would be to allow for 20nm gates at 30nm pitch.

Kappurao reminded attendees that while there is still uncertainty regarding the device structures beyond 7nm, there is certainty in 4 trends for equipment processes the industry will need:

  1. everything is an interface requiring precision materials engineering,
  2. film depositions are either atomic-layer or selective films or even lattice-matched,
  3. pattern definition using dry selective-removal and directed self-assembly, and
  4. architecture in 3D means high aspect-ratio processing and non-equilibrium processing.

An example of non-equilibrium processing is single-wafer rapid-thermal-annealers (RTA) that today run for nanoseconds—providing the same or even better performance than equilibrium. Figure 2 shows that a cobalt-liner for copper lines along with a selective-cobalt cap provides a 10x improvement in electromigration compared to the previous process-of-record, which is an example of precision materials engineering solving scaling performance issues.

Fig. 2: ElectroMigration (EM) lifetimes for on-chip interconnects made with either conventional Cu or Cu lined and capped with Co, showing 10 times improvement with the latter. (Source: Applied Materials)

“We have to figure out how to control these materials,” reminded Kappurao. “At 5nm we’re talking about atomic precision, and we have to invent technologies that can control these things reliably in a manufacturable manner.” Whether it’s channel or contact or gate or interconnect, all the materials are going to change as we keep adding more functionality at smaller device sizes.

There is tremendous momentum in the industry behind density scaling, but when economic limits of 2D scaling are reached then designers will have to start working on 3D monolithic. It is likely that the industry will need even more integration of design and manufacturing, because it will be very challenging to keep the cost-per-function decreasing. After CMOS there are still many options for new devices to arrive in the form of spintronics or tunnel-FETs or quantum-dots.

However, Arabi reminded attendees as to why the industry has stayed with CMOS digital synchronous technology leading to design tools and a manufacturing roadmap in an ecosystem. “The industry hit a jackpot with CMOS digital. Let’s face it, we have not even been able to do asynchronous logic…even though people tried it for many years. My prediction is we’ll go as far as we can until we hit atomic limits.”

SPIE Photomask Technology Wrap-up

Tuesday, September 23rd, 2014

Extreme-ultraviolet lithography was a leading topic at the SPIE Photomask Technology conference and exhibition, held September 16-17-18 in Monterey, Calif., yet it wasn’t the only topic discussed and examined. Mask patterning, materials and process, metrology, and simulation, optical proximity correction (OPC), and mask data preparation were extensively covered in conference sessions and poster presentations.

Even with the wide variety of topics on offer at the Monterey Conference Center, many discussions circled back to EUV lithography. After years of its being hailed as the “magic bullet” in semiconductor manufacturing, industry executives and engineers are concerned that the technology will have a limited window of usefulness. Its continued delays have led some to write it off for the 10-nanometer and 7-nanometer process nodes.

EUV photomasks were the subject of three conference sessions and the focus of seven posters. There were four posters devoted to photomask inspection, an area of increasing concern as detecting and locating defects in a mask gets more difficult with existing technology.

The conference opened Tuesday, Sept. 16, with the keynote presentation by Martin van den Brink, the president and chief technology officer of ASML Holding. His talk, titled “Many Ways to Shrink: The Right Moves to 10 Nanometer and Beyond,” was clearly meant to provide some reassurance to the attendees that progress is being made with EUV.

He reported his company’s “30 percent improvement in overlay and focus” with its EUV systems in development. ASML has shipped six EUV systems to companies participating in the technology’s development (presumably including Intel, Samsung Electronics, and Taiwan Semiconductor Manufacturing, which have made equity investments in ASML), and it has five more being integrated at present, van den Brink said.

The light source being developed by ASML’s Cymer subsidiary has achieved an output of 77 watts, he said, and the company expects to raise that to 81 watts by the end of 2014. The key figure, however, remains 100 watts, which would enable the volume production of 1,000 wafers per day. No timeline on that goal was offered.

The ASML executive predicted that chips with 10nm features would mostly be fabricated with immersion lithography systems, with EUV handling the most critical layers. For 7nm chips, immersion lithography systems will need 34 steps to complete the patterning of the chip design, van den Brink said. At that process node, EUV will need only nine lithography steps to get the job done, he added.

Among other advances, EUV will require actinic mask inspection tools, according to van den Brink. Other speakers at the conference stressed this future requirement, while emphasizing that it is several years away in implementation.

Mask making is moving from detecting microscopic defects to an era of mesoscopic defects, according to Yalin Xiong of KLA-Tencor. Speaking during the “Mask Complexity: How to Solve the Issues?” panel discussion on Thursday, Sept. 18, Xiong said actinic mask inspection will be “available only later, and it’s going to be costly.” He predicted actinic tools will emerge by 2017 or 2018. “We think the right solution is the actinic solution,” Xiong concluded.

Peter Buck of Mentor Graphics, another panelist at the Sept. 18 session, said it was necessary to embrace mask complexity in the years to come. “Directed self-assembly has the same constraints as EUV and DUV (deep-ultraviolet),” he observed.

People in the semiconductor industry place high values on “good,” “fast,” and “cheap,” Buck noted. With the advent of EUV lithography and its accompanying challenges, one of those attributes will have to give way, he said, indicating cheapness was the likely victim.

Mask proximity correction (MPC) and Manhattanization will take on increasing importance, Buck predicted. “MPC methods can satisfy these complexities,” he said.

For all the concern about EUV and the ongoing work with that technology, the panelists looked ahead to the time when electron-beam lithography systems with multiple beams will become the litho workhorses of the future.

Mask-writing times were an issue touched upon by several panelists. Shusuke Yoshitake of NuFlare Technology reported hearing about a photomask design that took 60 hours to write. An extreme example, to be sure, but next-generation multi-beam mask writers will help on that front, he said.

Daniel Chalom of IMS Nanofabrication said that with 20nm chips, the current challenge is reduce mask-writing times to less than 15 hours.

In short, presenters at the SPIE conference were optimistic and positive about facing the many challenges in photomask design, manufacturing, inspection, metrology, and use. They are confident that the technical hurdles can be overcome in time, as they have in the past.

Solid State Watch: September 12-18, 2014

Monday, September 22nd, 2014
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ASML on EUV: Available at 10nm

Wednesday, September 17th, 2014

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By Jeff Dorsch, contributing editor

Extreme-ultraviolet lithography systems will be available to pattern critical layers of semiconductors at the 10-nanometer process node, and EUV will completely take over from 193nm immersion lithography equipment at 7nm, according to Martin van den Brink, president and chief technology officer of ASML Holding.

Giving the keynote presentation Tuesday at the SPIE Photomask Technology conference in Monterey, Calif., Martin offered a lengthy update on his company’s progress with EUV technology.

Sources for the next-generation lithography systems are now able to produce 77 watts of power, and ASML is shooting for 81W by the end of 2014, Martin said.

The power figure is significant since it indicates how many wafers the litho system can process, a key milestone in EUV’s progress toward becoming a volume manufacturing technology. With an 80W power source, ASML’s EUV systems could turn out 800 wafers a day, he noted.

The goal is to get to 1,000 wafers per day. ASML has lately taken to specifying throughput rates in daily production, not wafers per hour, since many wafer fabs are running nearly all the time at present.

ASML’s overarching goal is providing “affordable scaling,” Martin asserted, through what he called “holistic lithography.” This involves both immersion litho scanners and EUV machines, he said.

Martin offered a product roadmap over the next four years, concluding with manufacturing of semiconductors with 7nm features in 2018.

The ASML president acknowledged that the development of EUV has been halting over the years, while asserting that his company has made “major progress” with EUV. He said the EUV program represented “a grinding project, going on for 10 years.”

For all of EUV’s complications and travails, “nothing is impossible,” Martin told a packed auditorium at the Monterey Conference Center.

With many producers of photomasks in attendance at the conference, Martin promised, “We are not planning to make a significant change in mask infrastructure” for EUV. He added, “What you are investing today will be useful next year, and the year after that.”

Blog review December 16, 2013

Monday, December 16th, 2013

Randhir Thakur of Applied Materials wishes the transistor a happy 66th birthday, noting that the transistor is truly one of the most amazing technological innovations of all time! He says it’s estimated that more than 1200 quintillion transistors will be manufactured in 2015, making the transistor the most ubiquitous man-made device on the planet.

Phil Garrou writes that 3DIC memory, and therefore all of 2.5/3D technology, took one step closer to full commercialization last week with the High Bandwidth Memory HBM joint development announcement from AMD and Hynix at the RTI 3D ASIP meeting in Burlingame CA.

Zhihong Liu, Executive Chairman of ProPlus Design Solutions is celebrating 20 years of BSIM3v3 SPICE models. He notes that with continuous geometry down-scaling in CMOS devices, compact models became more complicated as they needed to cover more physical effects, such as gate tunneling current, shallow trench isolation (STI) stress and well proximity effect (WPE).

Applied Materials and Tokyo Electron held a media roundtable in Japan to discuss the merger of equals announced on September 24, 2013. Tetsuro Higashi, Chairman, President and CEO of Tokyo Electron, who will become Chairman of the new company, and Mike Splinter, Executive Chairman of Applied Materials, who will serve as Vice-Chairman, addressed the audience of more than 20 members of the Japanese media. Kevin Winston blogs about the event.

Pete Singer is freshly back from the International Electron Devices Meeting (IEDM). “A dream for the device engineer could be a nightmare for a process integration engineer,” said Frederic Boeuf of ST Microelectronics in the opening talk. That seemed to be echoed throughout the conference, where the potential of new devices such as tunnel FETs or materials such as graphene were always tempered with a dose of reality that materials had to be deposited, patterned, annealed to create devices, and those devices had to be connected.

Blog Review November 5 2013

Tuesday, November 5th, 2013

New blogs delve into the packaging technology of Apple’s A7, the road ahead for bulk FinFETs as defined by imec, with EUV is a gating factor for 450mm, split-manufacturing for U.S. trusted IC (TIC) program and Japan’s growing market for equipment and materials.

For the 10nm node and beyond, transistor research efforts are focused on high mobility designs with Ge and III-V channel, reducing VDD supply voltage as well as the subthreshold slope in transistors and optimizing multi-Vt designs. Pete Singer reports on work underway at imec in Belgium.

At the IEEE 3DIC in San Francisco Dan Radack of the Institute of Defense Analysis gave an update on the IARPA trusted Integrated Chip Program. Phil Garrou reports how it is now focused on split-manufacturing with FEOL done off-shore and BEOL done by trusted facilities in the U.S.

The A7 is manufactured by Samsung on a high-κ metal gate (HKMG) 28 nm process and the chip includes over 1 billion transistors on a die 102 mm2 in size. Phil Garrou reports on observations on the Package-on-Package (PoP) design as noted by fellow blogger Dick James. In an earlier blog, Dick described how the Apple A7 is using Samsung’s 28nm process.

Simon Favre of Mentor Graphics notes how EUV could possibly be a gating factor for 450mm. “Would you put in 450mm immersion steppers, and then yank them out to put in EUV before they’re fully depreciated?” he asks.

In advance of Semicon Japan, to be hold December 4-6 at the Makuhari Messe, SEMI’s Dan Tracy and Yoichiro Ando report that restructuring and consolidation has led to a new focus for the semiconductor manufacturers in Japan. As a result, the semiconductor equipment market in Japan will experience double-digit growth in both 2013 and 2014, driven by higher spending for memory production and in spending increases planned for the manufacturing of power semiconductors and “More than Moore” semiconductor technologies. Total equipment spending in Japan is estimated to reach $4.6 billion by 2014. Combining this with the $8 billion-plus spending on semiconductor materials, Japan represents a $12 billion market in 2014 for the suppliers of equipment and materials.

Research Bits: Oct. 22, 2013

Tuesday, October 22nd, 2013

Size matters in the giant magnetoresistance effect in semiconductors

Professors at Georgia State University reported that a giant magnetoresistance effect depends on the physical size of the device in the GaAs/AlGaAs semiconductor system.

In research that is supported by grants from the U.S. Department of Energy and the U.S. Army Research Office, Dr. Ramesh Mani, professor of physics and astronomy, studied the magnetoresistance in flat, very thin sheets of electrons in the ultra high quality GaAs/AlGaAs semiconductor with his colleagues Annika Kriisa from Emory University and Werner Wegscheider from the ETH-Zurich in Switzerland.

The researchers found that the change in the resistance or resistivity with the magnetic field depends on the size of the device. They demonstrated that, under the application of a magnetic field, wide devices develop a smaller and quicker change, while small devices develop a bigger but slower change in the resistivity. The resistance or resistivity of a material to the flow of electricity is a technologically important property, especially in semiconductors.

This research team developed a model to understand the observations and deduced that when the semiconductor system becomes of even better quality, the change in the resistance under the application of a magnetic field will become even bigger. Indeed, the change might become so big that the resistance vanishes entirely in the small magnetic field.

Thin film semiconductors that will drive production of next-generation displays

Researchers at the National Institute for Materials Science have developed a pixel switching semiconductor, which will be the key to driving next-generation displays, by using an oxide film with a new elemental composition.

When an oxide film contains metal with low bond dissociation energy, the thin film absorbs or desorbs oxygen easily and the conductivity of the film changes. For example, zinc has very low bond dissociation energy, so a thin film using zinc absorbs or desorbs oxygen easily when heated or cooled. This finding suggests that the manufacturing conditions for oxide semiconductors can be controlled by focusing on the bond dissociation energy. In fact, the research team confirmed that film deposition conditions can be broadened by adding silicon oxide with high bond dissociation energy to indium oxide. We also confirmed stabilization of thin-film conductivity in post-deposition heat treatment.

The research results are expected to be effective not only for reducing the power consumption of displays which consume about half of the power in rapidly diffusing smartphones, but also for achieving higher frequencies to realize higher-definition TVs. Additionally, the thin film developed in this research contributes to conserving precious resources by not using zinc, which is a trace element of concern, or high-cost gallium which is used in large quantities for galvanized steel sheets or as a rubber vulcanizing agent, while it also enables the manufacture of flat panel displays not affected by wild fluctuations in raw material prices.

Ultraviolet light to the extreme

When you heat a tiny droplet of liquid tin with a laser, plasma forms on the surface of the droplet and produces extreme ultraviolet (EUV) light, which has a higher frequency and greater energy than normal ultraviolet.Now, for the first time, researchers have mapped this EUV emission and developed a theoretical model that explains how the emission depends on the three-dimensional shape of the plasma. In doing so, they found a previously untapped source of EUV light, which could be useful for various applications including semiconductor lithography, the process used to make integrated circuits.

In the experiments, Andrea Giovannini and Reza Abhari from ETH-Zurich in Switzerland blasted a 30-micron-diameter droplet of tin with a high-powered laser 6,000 times a second. They measured the spatial distribution of the resulting EUV emission and found that 30 percent of it came from behind the region of the droplet that was struck by the laser. According to their model, this unexpected distribution was due to the fact that the plasma partially surrounding the droplet was elongated in the direction of the laser pulse.

Devices that produce narrow beams of EUV for purposes like in semiconductor lithography use mirrors to focus the emission. But, until now, no one knew to collect the EUV light radiating from behind the droplet.

Blog Review October 21 2013

Monday, October 21st, 2013

The readiness of EUV lithography is later than hoped, but appears to be on time for insertion into the 10nm node, which is slated to go into production in late 2015/early 2016. “I’m very convinced that very soon EUV will be ready to enter manufacturing,” said Luc Van den hove, president and CEO of imec, as reported by Pete Singer.

In an earlier blog, Veeco’s Tim Pratt, Senior Director, Marketing, said that indeed the next major roadblock to progress in the ongoing push to develop EUV lithography for volume production is the availability of defect-free mask blanks. He said that the tools in place today are not capable of producing mask blanks with the kind of yield necessary to support a ramp in EUV.

Meanwhile, results from early work into directed self-assembly (DSA) is quite promising. DSA could be used in conjunction with EUV for the 7nm node, scheduled to go into production in the 2017/2018 timeframe. Work at imec has shown that the polymers, with a hard mask on top, are robust enough to enable the etching of the patterns into silicon. “That’s fairly new data and very promising,” said An Steegen, senior vice president of process technology at imec.

EUV readiness also been the focus of several blogs by Vivek Bakshi. Earlier this year, he predicted that 50 W sources will be ready and working in NXE3300B sometime in 2014, corresponding to 43 WPH throughput. 100 W sources will be ready in 2015 or 2016 corresponding to 73 WPH. “The readiness of 250 W EUV sources cannot be safely predicted, unless we see 100 W sources ready and have identified the issues to ensure that they are no showstoppers. I am not convinced that present approaches can get to 500 W sources. It is easy to put them on roadmaps, but delivering them is another question,” he said.

Intel is far ahead of anyone else when it comes to putting 14nm devices into production. However, even Intel finds it challenging. Speaking on a quarterly call with analysts, newly elected CEO Brian Krzanich said 14nm rollout was “about a quarter behind our projections.” He said defects were the problem. “As a result, we are now planning to begin production in the first quarter of next year,” as Pete Singer reported.

Intel already has 3D finFETs in production, and  FinFETs will likely become the logic technology of choice for the upcoming generations, with high mobility channels coming into play for the 7 and 5nm generation (2017 and 2019).

Brian Krzanich also said that Intel remained committed to the transition to 450mm wafers, saying: “We have not changed our timing. We are still targeting the second, latter half of this decade.” At Semicon Europa week, Paul Farrar, general manager of G450C, provided an update on the consortium’s progress in demonstrating 450mm process capability. He said 25 tools will be installed in the Albany cleanroom by the end of 2013, progress has been made on notchless wafers with a 1.5mm edge exclusion zone, they have seen significant progress in wafer quality, and automation and wafer carriers are working.

Phil Garrou reports on developments from Semicon Taiwan 2013 of interest to the IC packaging community. The Market Trends Forum chaired by Dr. Burn Lin of TSMC, included a report on DRAM Status (continued consolidation) by Charlie Chan of Morgan Stanley; Nicolas Gaudois Managing Director of UBS Investment Research looked at the “The End of the High End Smartphones Run,” and Dan Tracy of SEMI provided the Packaging Materials Outlook.