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Rhines Reviews Four Decades of Design and Verification


By Jeff Dorsch, Contributing Editor

The electronic design automation industry is progressing from the “Applications Age” to a new era of field-programmable gate array prototyping where security and safety considerations are coming to the fore, according to Wally Rhines, chairman and chief executive officer of Mentor Graphics, giving the keynote address at DVCon U.S. in San Jose, Calif.

The Mentor CEO, who spent 21 years at Texas Instruments before getting into the EDA business, recalled that back in 1972, “there was no verification,” as chip designers were working on small-scale integration and medium-scale integration circuits that weren’t very complex.

Soon after, the CANCER simulator and the SPICE simulation program were developed, ushering in what Rhines called “verification era 0.0.”

This was followed by the register-transfer language design era of VHDL and the Verilog hardware description language, which he dubbed the “verification 1.0 era.”

As computers grew “faster, bigger,” Rhines said, “simulation became very fast, very productive,” leading to testbenches and “verification 2.0,” he added.

The emulation/simulation/verification segment in EDA increased to more than $1 billion in revenue during 2014, Rhines noted. This led to the “systems era” and “verification 3.0,” with multiple domains, he said.

The industry continues to evolve, from the “Pre-ICE Age” and ICE (in-circuit emulation) Age to the current times, with test creation automation and “the goal of portable stimulus,” the Mentor CEO said.

Going “beyond functional verification,” Rhines cited security as an increasing concern in IC design and verification. He pointed to Beckstrom’s Law of Cybersecurity:

  1. Anything attached to a network can be hacked.
  2. Everything is being attached to networks.
  3. Everything is vulnerable.

Semiconductors are now subject to side-channel attacks, Rhines noted. There are also the issues of counterfeit chips and malicious logic inside the chip. For the latter, the industry will resort to static tests and dynamic detection, he said.

In light of these developments, design and verification is moving to “verifying a chip does nothing it is not supposed to do,” Rhines commented.

Safety is the other big issue in chip design and verification. For automotive vehicles, there is the ISO 26262 standard. In medical equipment, it’s the IEC 60601 standard. And in military/aerospace applications, it’s the D0-254 standard, according to Rhines.

Working with such standards, subject to auditing, calls for fault injection and formal-based fault injection/verification, he said.

DVCon, short for Design and Verification Conference and Exhibition, evolved early in the 21st century from the establishment of verification standards and formation of the Accellera Systems Initiative. Annual conferences are held in Europe, India, and the U.S., with plans for a DVCon China in 2017.

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