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EMC2015 – New Devices, Old Tricks

By Ed Korczynski, Sr. Technical Editor

The 57th annual Electronic Materials Conference (, held June 24-26 in Columbus, Ohio, showcased research and development (R&D) of new device structures, as well as new insights into the process-structure-properties relationships of electronic devices now running in high-volume manufacturing (HVM) lines globally. A plethora of papers on compound-semiconductor quantum-dots and nanorods, LEDs and quantum-dot detectors, power electronics, and flexible and bio-compatible devices all show that innovation will not slow down despite the limitations of Dennard Scaling and Moore’s Law. With 3D stacking of existing devices on novel substrates an ongoing integration challenge for HVM, the conference also explored substrate engineering and 3D stacking technologies.

CEA-Leti’s “Smart-cut” technology has been used for over 20 years to cleave crystalline layers for transfer and bonding to stack substrate functionalities, such as Silicon-On-Insulator (SOI) wafers. Researchers from Leti looked at the discrete steps involved in the hydrogen implantation, annealing to create the buried plane of micro-bubbles within the crystal, and then the acoustic wave that travels through the plane to complete the cleave. A periodic wave pattern is dynamically generation during cleaving, with the evolving wavefront dependent upon the contribution of all the past fracture fronts to any particular point. The cleaved roughness is related to the speed of the fracture wave moving through the wafer plane, and that depends on the micro-cracks the are originally present due to the micro-bubbles.

Leti researchers also reported on “Copper grain-size effects on direct metallic bonding mechanisms” such as will be used in 3D chip-stacking. The main limitation on the density of 3D copper (Cu) connections between chips is the micro-bump pitch, with Cu-Cu bonds providing both electrical and mechanical connections. Since the grain-size of annealed Cu thin-films depends on film thickness, they used electro-chemical deposition (ECD) to grow two different thicknesses, annealed each at 400°C for 10 hours to allow for maximum grain growth, and then used CMP to get all samples to the same final thickness. The result was fine-grain Cu bumps with 0.6 micron diameter grains, and large-grain bumps with ~2.1 micron diameter grains. With no post-bond-anneal there was significant improvement in bonding strength with fine-grain-structure Cu compared to large-grains, but with post-bond-anneals up to 300°C the grain-size effect was reduced such that all samples approaching the same high levels of bond strength. However, 400°C annealing resulted in a newly observed voiding phenomenon between the Cu and TiN barrier layers, with more voids associated with finer-grains.

Artificial Neural Networks

Researchers from Sandia Labs showed data on multi-level data storage using memristors. Lacking repeatable processes to manufacture memristors, people have used SRAM arrays to build the first Artificial Neural Networks (ANN) such as those commercialized by NeuroMem Inc. However, models indicate that changing from SRAM- to memristor-arrays would reduce power by 16x and chip area by 6x (assuming 25,600 elements). Sandia has been working with TaOx (where 3 < x < 5) as the memristor switching layer, and has been able to show up to 5 discrete High Resistance States (HRS) to be able to do multi-bit storage in a single cell. For multilevel switching, the standard deviation of a target resistance increases with increasing resistance (not with the magnitude of the resistance change). However, each cell was only cycled 25-50 times, so reliability/wear-out has not yet been explored.

IBM Almaden Labs began work on Phase-Change Memory (PCM) with Macronix and Qimonda in 2004, and recently have explored PCM to build ANN. They sacrifice density and double up the artificial synapses to separately encode excitory and inhibitory functions. In PCM it is easy to slowly step up the High-Resistance State (HRS) levels since a crystalline plug is the Low Resistance State (LRS) and gradual crystallization of the edges of the plug gradually increases resistance, while reset back to LRS either happens on doesn’t across the entire plug so there is an inherently asymmetrical response. For Resistance RAM (ReRAM) structures there is opposite asymmetry in that the conductive filament either forms or doesn’t, while reset to LRS can happen gradually. These asymmetries  in the inherent dynamic responses of artificial synapses result in problems for learning/programming of ANN since ideal learning calls for slight increases and decreases in resistances.


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