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Tackling Parameter Extraction for 16nm and Below


There are four reasons why parasitic parameter extraction is getting a lot harder for 16nm and below technology nodes: 1) 3D device geometries, such as the finFET, which result in more complex electrical fields around the device 2) multi-patterning, which causes increased variability; 3) a demand for 10X tighter levels of accuracy, and 4) increased levels of secrecy from foundries and designers.

With Calibre xACT, Mentor Graphics has a solution that is part equation-based and part field solver, giving high accuracy and high throughput. Customers using the Calibre xACT platform for parasitic extraction have experienced improvements in turnaround time as high as 10X, while meeting the most stringent accuracy requirements.

At DAC this week, Carey Robertson, product marketing director of Calibre xACT, will be presenting an optimized extraction flow for RF-SOI processes, based on work with STMicroelectronics, today (Monday June 8th) between 4-5 pm at the Mentor Graphics booth #1432. Register at the Mentor Graphics website:

Robertson explained the new challenges facing the industry. “We have new types of devices that are three-dimensional in nature. There is a very profound electrical field that is three dimensional in nature, and very difficult to capture with traditional techniques, such as equations or tables,” he said. In addition to the device itself, there’s going to be local interconnect, there’s going to be contacts that need to be modeled.

Parasitic electrical fields around a 3D finFET device.

Double- and multi-patterning adds to the complexity.  “In the area of parasitic extraction, double patterning essentially means that we have geometries on the same layer on different masks. As those masks shift, that will incur additional sources of parasitic variation that we have to consider,” Robertson explained.

In addition, foundries such as Samsung, TSMC and GLOBALFOUNDRIES are pushing tighter and tighter criteria. “Foundries are pushing EDA vendors to bring the accuracy of their parasitic tools to a much tighter level vs their golden reference,” Robertson said. “At 20nm, if we felt like our accuracy was within 5-10% of the golden reference, that was typically fine. What we’re seeing at 16, 14 and 10nm is that foundries are requiring that the accuracy be within 2%, many times 1% with a sigma of 2%,” Robertson said. “It’s very, very tight criteria, tighter than we’ve ever seen before.

The other challenge is that in years past, EDA vendors would get a lot of data to use to develop their tools. “We’d get a lot of structures and a lot of things to go check against. We’d get those inside Mentor Graphics and R&D could play with that and figure out the best models to accommodate them,” Robertson said. He described today’s situation as an arms race between foundries and designers, where secrecy was paramount. “It’s an arms race to see who comes up with the best process, and it’s a race amongst designers to come up with who has the best designs. They don’t let their design data go outside of their respective companies. We have to figure out how to model these with more complex interactions, tighter criteria and much less access to data,” he said.

Enter the new Calibre® xACT™ parasitic extraction platform that addresses a wide spectrum of analog and digital extraction needs, including 14nm FinFET, while minimizing guesswork and setup efforts for IC designers. The Calibre xACT platform delivers a combination of accuracy and turnaround time (TAT) by automatically optimizing its extraction techniques for the customer’s specific process node, application, design size, and extraction objectives.

Samsung has worked extensively with Mentor Graphics on the development and qualification of the Calibre xACT platform for 14nm, and used it during technology development because of the high accuracy it provides. The Calibre xACT product’s ability to employ a single rule deck for a range of extraction applications allows customers to get the accuracy and fast TAT they need without having to manually modify their rule decks or tool configuration.

“After careful benchmarking of the leading extraction products, we selected Calibre xACT to be our reference signoff extraction tool for all of our next generation designs,” said Dragomir Nikolic, CAD Director, Cypress Semiconductor. “This includes products at the 90nm and 65nm process nodes. We found Calibre xACT to have the best combination of high accuracy and fast turnaround available among extraction products targeting leading-edge nodes. We also see great value in the ability to use a single extraction tool to produce optimum results across a wide variety of applications, from transistor level to full chip digital extraction.””

Circuit designers have to wrestle with performance versus accuracy throughout the design cycle. Parasitic extraction is no different. With the leading process nodes using more complex FinFET devices, design engineers are pushing for tighter accuracy, while also needing higher performance and capacity for billion transistor designs. In fact, all process nodes are seeing growing complexity with the mix of memory, analog, standard cell, and custom digital content in modern IC’s. This complexity poses a range of different challenges for extraction tools. To meet these requirements the Calibre xACT platform uses a combination of compact model, field solver and efficient multi-CPU scaling technologies to ensure robust accuracy as well as turnaround performance needed to meet schedule deadlines.

The Calibre xACT extraction platform is integrated with the entire Calibre product line for a seamless verification flow, including the Calibre nmLVS™ product for complete transistor-level modeling, and the Calibre xACT 3D product for targeted, extreme-accuracy extraction applications. It also interoperates with third-party design environments and formats to ensure compatibility with existing design and simulation flows.

“It’s an environment that has all of the necessary integration and accuracy techniques that the custom IP designer needs, as well as the throughput, turnaround time and scalability the signoff/extraction needs,” Robertson said.

At DAC this week, Robertson will be presenting an optimized extraction flow for RF-SOI processes, based on work with STMicroelectronics, today (Monday June 8th) between 4-5 pm. Register at the Mentor Graphics website:

Robertson says to enable RF design optimization with high correlation to actual silicon, simulation of RF-SOI designs must include extraction and modeling of the silicon substrate. Conventional silicon substrate extractions are cumbersome to use or lack the accuracy and performance required to produce a full-chip post-layout netlist.

STMicroelectronics, Mentor Graphics and Coupling Wave Solutions are working on a new flow that generates silicon substrate parasitics in just a few minutes. These can be added to a conventional post-layout netlist to produce a complete and accurate parasitic model for RF SOI designs. Carey’s presentation will give an overview of RF-SOI technology, and describe how the new extraction flow delivers parasitics accuracy, performance and ease-of-use.

Mentor Graphics Technical Sessions are held at booth #1432.

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