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Changes and Challenges Abound in Multi-patterning Lithography


By Jeff Dorsch

Multi-patterning lithography is a fact of life for many chipmakers. Experts in the fields of electronic design automation and lithography address the issues associated with the technology. Providing responses are David Abercrombie, Design for Manufacturing Program Manager, Mentor Graphics; Gary Zhang, Vice President Marketing, ASML Brion; and Dr. Donis Flagello of Nikon Research Corporation of America.

1. What are the significant considerations in semiconductor manufacturing and design with multi-patterning lithography?

David Abercrombie: Like most process/design trade-offs moving from one node to another it comes down to cost vs area and performance. Without multi-patterning or EUV you will struggle do design at 20nm or below limiting the opportunity to take advantage of design area and performance scaling. Essentially, Moore’s Law slows to a crawl without it. Multi-patterning affects almost all aspects of design and manufacturing. For physical design it adds additional design rule constraints and constrains cell placement and routing depending on cell architecture. For electrical design it adds additional parasitic variability to consider in timing analysis. For DFM it adds additional requirements for fill and lithographic checking. In manufacturing it adds additional masks, process steps and increases stepper utilization. All of these increase complexity and have an associated cost. It ultimately has to make business sense. Because of this you are seeing fewer companies moving to these advanced nodes as quickly as before, as they must have the volume and profit margins to justify the increased cost. Fortunately, there are products that do need the newest and most advanced process nodes, and because of those needs we continue to move forward into these new technology nodes on a regular schedule.

Gary Zhang: Multiple patterning (MPT) using immersion lithography is required for the semiconductor industry to continue device scaling until extreme ultraviolet (EUV) comes into full production (EUV is expected for a mid-node insertion in the 10nm logic node, and for 7nm node development and production in the 2015-2017 time frame). Multiple-patterning lithography brings the following new challenges from design to manufacturing. ASML has been collaborating with the chipmakers in a holistic lithography framework to tackle these challenges with innovative hardware and software solutions, including scanner systems, computational lithography, metrology and process control.

Integrated circuit designs have to be multiple patterning compatible. Industry has been developing methods to enable MPT-compatible designs via layout decomposition (coloring) and conflict resolution using multiple patterning rules as constraints. This applies to standard-cell libraries, cell boundaries, and placement and route to ensure full chip layouts meet all manufacturing requirements and can be decomposed into separate masks without any post-coloring MPT conflicts. Structured layouts with highly restricted design rules seem to be a key enabler for MPT-compliant designs.

The rule-based approach to MPT compatible designs tends to run the risk of pattern defects from design hot spots, especially when design rules are pushed aggressively for competitive die size. The lithography process window of these design hot spots can be enlarged using source-mask optimization (SMO). Brion’s Tachyon SMO has been routinely used to co-optimize scanner optics such as illumination source and projection lens wavefront and mask enhancements including sub-resolution assist features (SRAF) and optical proximity correction (OPC) for any given designs. Take triple patterning of a 10nm node metal layer as an example. Tachyon SMO enables a 23% larger process window for the selected SRAM and logic designs (Figure 1). By evaluating a range of design variations, SMO can help optimize design rules and MPT coloring rules to eliminate design hot spots in the technology development stage. For production mask data preparation, Brion’s multiple patterning OPC and LMC (Lithography Manufacturability Check) are widely used by the leading chipmakers to deliver the best full chip process window in wafer manufacturing. A combination of SMO, OPC and LMC makes up ASML’s process window enhancement solutions to the design hot spot problem.

Figure 1. Source-mask optimization (SMO) of a 10 nm node metal layer in triple patterning lithography. Overlapping process window of all three splits (masks) is improved by 23% for selected SRAM and logic patterns imaged with the same illumination setup.

Multiple patterning drives tighter CD, focus and overlay requirements to account for more process variations from the additional processing steps. Overlay is used here as an example to show the increasing complexity in multiple patterning process control from single exposure at 28nm node, to double patterning at 14nm node, to triple patterning at 10nm node (Figure 2). Tighter overlay specification has to be met for the exponentially increasing number of critical masks and metrology steps at 14nm and 10nm nodes. To deliver the required overlay control on product wafers, scanner matching and process control have to include high order corrections (Figure 3). ASML’s latest generation of immersion scanners have a large number of flexible actuators and are capable of sub-3 nm matched-machine overlay, dynamic lens heating and reticle heating corrections, and high-order interfield and intrafield corrections for imaging, focus and overlay.

Figure 2. A comparison of overlay metrology and control for single exposure at 28 nm node, double patterning at 14 nm node and triple patterning at 10 nm node, using the Metal 1 (M1) to Metal 2 (<2) process loop as an example.

Figure 3. On-product overlay roadmap showing the ever tighter specification from 28 nm node to 14 and 10 nm nodes and the requirement of advanced scanner correction capabilities (such as dynamic and high-order).Two different production scenarios are considered, namely scanner/chuck dedication and mix and match of different scanners.

With the introduction of multiple patterning below 28 nm node, the increasing number of masks and metrology steps translates to lower wafer throughput per scanner and longer wafer cycle time from start to finish. This then leads to cost per wafer significantly higher than the historical cost scaling trend from the previous technology nodes. ASML has been continuously driving the scanner innovation to increase the throughput and improve productivity in terms of wafer output per day. ASML’s YieldStar integrated metrology is another innovative solution to reduce wafer cycle time and improve on-product performance for effective productivity gain and overall cost benefit.

In summary, a full suite of design and manufacturing solutions are required to address the new challenges in multiple-patterning lithography. ASML has taken a holistic approach and worked in close collaboration with the chipmakers to optimize design, scanner, mask and process control altogether for the best manufacturability and yield. Figure 4 gives an example on how holistic lithography enables focus roadmap down to 1x nm node. In the design phase, process window enhancement solutions such as SMO, OPC and LMC are used to eliminate the design hot spots and maximize the full chip process window. In the wafer manufacturing phase, process window control solutions such as scanner matching and high order corrections are implemented to optimize CD, overlay and focus control dynamically from tool to tool, field to field, wafer to wafer and lot to lot. A combination of the largest process window and the tightest process control delivers the most robust manufacturability and yield in volume production.

Figure 4. An example of how holistic lithography enables focus roadmap down to 1x nm node (DPT: double patterning; MPT: multiple patterning). A combination of process window enhancement and process window control solutions delivers robust manufacturability and yield in volume production.

Donis Flagello: Multiple patterning brings a host of issues due to the added complexity associated with imaging and processing multiple patterns within the same design layer. From the exposure tool point of view, we need to ensure that the overall cost of ownership is maintained and the tool can enable further scaling. We are concentrating on many aspects of the technology. One of the most critical is overlay. This must be as low as possible such that the ensemble overlay of all the exposures within a layer is equal or better than a single exposure. Simultaneously, we need to increase the throughput of the tools to ensure that cost per wafer per hour is also continuously improved.  Both of these aspects drive a huge amount of innovation and technology development.

2. How do you deal with color assignment?

Abercrombie: The answer to that depends on the foundry and layer being discussed. Colorless, partial coloring and full coloring flows exist. In colorless flows the designer does not assign colors. There are specialized checks (like odd cycle checks in double patterning) that make sure the layout can be decomposed into multiple masks later once the design is taped-out to the foundry. In a partial coloring flow most of the layout follows the colorless flow, but the designer can manually assigns some parts of the layout to a particular color to manage subtle variation concerns. For instance, making sure matched circuitry also has matched coloring. In a fully colored flow the designer is responsible for producing the final mask assignments for all polygons in the layer. A GDS layer is dedicated to each mask. To assign a polygon to a given mask a copy of it is placed on the appropriate mask color layer. EDA companies provide various automation capabilities to assist with color assignment in custom, P&R and batch full chip applications.

It is best to use an EDA solution like Calibre that not only can address all different coloring flows but also provides the same checks/algorithms for all phases a design goes through from initial IP blocks to final full chip signoff.

Zhang: Layout decomposition or coloring has to deliver split patterns on separate masks which are free of any process rule violations and can then be patterned in single exposure with sufficient process window. A double patterning (DPT) using a litho-etch-litho-etch process is shown as an example (Figure 5). In the DPT coloring step, any non-native color conflicts are resolved in a layer aware implementation with stitches that are properly located away from the overlap region between layers (such as a metal line contacting a via) and have the least impact on the device performance and manufacturing yield. Process robust stitching must have sufficient overlap margin to tolerate misalignment between the exposures of the split masks. This is the concept of overlay aware stitching.

Figure 5. An example of design to manufacturing work flow for a litho-etch-litho-etch double patterning (DPT) process, from layer aware coloring to overlay aware stitching, to model based OPC, to the final contour after litho and etch processes.

Color balancing is another critical care-about in layout decomposition. MPT coloring not only needs to deliver split layouts free of MPT conflicts but also has to ensure the pattern density is balanced between the split masks. Color balancing is beneficial for litho and etch process control so that robust and uniform patterning qualities can be achieved.

Coloring can also be optimized for best process window using a model based approach, as described above in the “Design hot spots” section. Model-based coloring is not suitable for full chip application. It can be either used in source-mask optimization for MPT rule development or applied in local hot spot fix during the mask data preparation.

3. How does design rule check change? How is it the same?

Abercrombie: In a fully colored flow the design rules change slightly. First for every traditional spacing check there are essentially two checks for double patterning (DP): a minimum spacing for different colored polygons, and a larger minimum spacing for same colored polygons. In addition, there are usually additional density checks making sure the ratio between the colors is reasonably equal. In colorless flows specialized new checks have been developed to verify if a valid coloring exists for a given layout construct. In double patterning these specialized checks include odd cycle checks. For triple patterning (TP) and quadruple patterning (QP) new types of checks are required.

Zhang: Triple patterning (TPT) coloring is a lot more difficult and complex than DPT coloring. It is extremely hard to determine if a layout is TPT compatible, known as NP-complete problem in graph theory. There is no efficient way to find a solution on the full chip level. There are no existing methods for determining the number of conflicts and their locations.

Stitches are color-dependent in TPT and candidate stitch locations can be determined only after or during coloring.

Therefore it is important to ensure TPT compliance by design construct.

4. What are the complexities and issues in transitioning from double-patterning to triple-patterning?

Abercrombie: Although checking and decomposing a layout for two colors is complex, the algorithmic processing scales reasonably by design size. However, the generalized solution for triple and quadruple patterning has exponentially increasing run time as the number of polygons processed increases. This is, of course, is not a practical solution. So the problem must be constrained such that reasonable heuristic algorithmic approaches can be applied that provide reasonably scalable run times. So the complete set of design rules and design methodology need to be properly tuned to constrain the graph-complexity of the layouts produced so these checking and decomposition heuristic tools can be utilized. In addition, specialized checks may be needed so that layout constructs that do not meet the complexity constraints can be diverted from processing (to keep run time from exploding) and flagged to the user for modification until they can be properly processed.

The other challenge in moving from DP to TP and QP is colorless error visualization. If you are doing a colorless flow and need to check if the design can legally be colored, you need a way to highlight constructs for which no valid coloring solution exists in a way that the designer can understand so he/she can make changes in the layout to fix it. For DP this was odd cycle error visualization. An even-numbered cycle of interacting polygons can be colored and an odd numbered cycle of interacting polygons cannot. For TP and QP this is not the case. Any simple even or odd cycle can be colored. The constructs which cannot be colored are much more complex than in DP. In addition, narrowing down the implicated constructs to the “root” of the problem is more difficult. To address these issues Mentor Calibre is developing a new array of error visualization layers to help inform and guide the user to appropriate and productive fixes.

Flagello: Years ago many industry observers did not believe that double patterning was viable. Today double and triple patterning is being done. However, there are some key differences between the two. Depending on the technology used, double exposure from a tool perspective is more or less straightforward. Mask alignment is usually based on the previous layer mark. However, moving to triple exposure often results in much more of an optimization problem to determine the best alignment strategy. Sometimes, the previous layer alignment mark may have a poor signal depending on the number of films involved in the multiple-patterning schemes. While increasing the number of patterning steps increases some of the complexity, the solutions become more of an optimization and controls challenge.

5. What issues in IC design and verification emerge with multi-patterning?

Abercrombie: The designer should expect to see new design rules, more parasitic variation, more complexity in design and methodology constraints, increased wafer cost, and the need for new EDA tools and additional CPU hardware to process their designs. This is really not new as this increased complexity and cost has existed between every node transition. The difference is that the delta may be more than between previous nodes. It is important that design teams educate themselves early on the impacts of moving to multi-patterned process nodes. That includes getting information from the foundry and EDA partners as well as reading available material on the subject. I have a whole series of articles covering much of the questions in this round table in significant detail:

Zhang: In addition to the power, performance and area metrics, designers now have to ensure their IC designs are MPT compliant and free of design hot spots so that they can be manufactured cost effectively with the best yield using multiple-patterning lithography. From lithography point of view, design hot spots are the major yield detractor. Device performance such as RC timing delay, cross talk, leakage (such as IDDQ), breakdown voltage and final yield is heavily influenced by MPT process variations. Brion’s LMC has been used to evaluate the impact of realistic dose, focus, mask and overlay variations on MPT hot spots both intra-layer and interlayer. Identification of such MPT hot spots helps drive design and OPC improvements so that they can be eliminated in wafer manufacturing.

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