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Solid Doping for Bulk FinFETs


By Ed Korczynski, Sr. Technical Editor

In another example of the old one-liner that “all that is old is new again,” the old technique of solid-source doping is being used by Intel for a critical process step in so-called “14nm node” finFET manufacturing. In the 7th presentation in the 3rd session of this year’s IEDM, a late news paper written by 52 co-authors from Intel titled “A 14nm Logic Technology Featuring 2nd-Generation FinFET Transistors, Air-Gapped Interconnects, Self-Aligned Double Patterning and a 0.0588m2 SRAM Cell Size” disclosed that solid source doping was used under the fins.

As reported by Dick James of Chipworks in his blog coverage of IEDM this year, the fins have a more vertical profile compared to the prior “22nm node” and are merely 8nm wide (Fig. 1). Since Intel is still using bulk silicon wafers instead of silicon-on-insulator (SOI), to prevent leakage through the substrate these 8nm fins required a new process to make punch-through stopper junctions, and the new sub-fin doping technique uses solid glass sources. Idsat is claimed to improve by 15% for NMOS and 41% for PMOS over the prior node, and Idlin by 30% for NMOS and 38% for PMOS.

FIGURE: Intel Corp’s “14nm node” finFETs show (in the left SEM) 8nm wide and 42nm high fins in cross-section, below which are located the punch-through stopper junctions. (Source: IEDM 2014, Late News 3.7)

Solid glass sources of boron (B) and phosphorous (P) dopants have been used for decades in the industry. In a typical application, a lithographically defined silicon-nitride hard-mask protects areas from a blanket deposition in a tube furnace of an amorphous layer containing the desired dopant. Additional annealing before stripping off the dopant layer allows for an additional degree of freedom in activating dopants and forming junctions.

In recent years, On Semiconductor published how solid-source doping on the sidewalls of Vertical DMOS transistors enable a highly phosphorous doped path for the drain current to be brought back to the silicon surface. The company shows that phosphorous-oxy-chloride (POCl) and phospho-silicate glass (PSG) sources can both be used to form heavily doped junctions 1-2 microns deep.

The challenge for solid-source doping of 8nm wide silicon fins is how to scale processes that were developed for 1-2 microns to be able to form repeatable junctions 1-2 nm in scale. Self-aligned lithographic techniques could be used to mask the tops of fins, and various glass sources could be used. It is likely that ultra-fast annealing is needed to form stable ultra-shallow junctions.

Intel is notoriously protective of process Intellectual Property (IP) and so has almost certainly ensured that any equipment and materials suppliers who work on the solid-source doping process sign Non-Disclosure Agreements (NDA) with amendments that forbid acknowledging signing the NDA itself, so it is pointless to directly ask for any further details at this point. However, slides from John Borland’s recent presentation at the NCCAVS Junction Technology Users Group meeting provide a great overview of the publicly available information on finFET junction formation, and include the following:

…higher dopant activation can be realized at low temperatures if the junction is amorphous and recrystalized by using SPE (solid phase epitaxy) recrystalization of the junction as also shown in the data by Intel.

Also seen at IEDM this year in the 7th presentation of the Advanced Process Modules section, Taiwanese researchers—National Nano Device Laboratories, National Chiao Tung University, and National Cheng Kung University—joined with Californian consultants—Current Scientific, Evans Analytical Group—to show “A Novel Junctionless FinFET Structure with Sub-5nm Shell Doping Profile by Molecular Monolayer Doping and Microwave Annealing.” They claim an ideal subthreshold swing (~60 mV/dec) at a high doping level. Poly-Si n & p JLFinFETs (W/L=10/20 nm) with SDP experimentally exhibit superior gate control (Ion/Ioff >10E6) and improved device variation.


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3 Responses to “Solid Doping for Bulk FinFETs”

  1. Ali Says:

    Solid-source diffusion has been also been used to form the buried plate in the trench DRAMs. The biggest difference, IMO, is the doping density requirement. Sub-gate fin requires a doping of about 1e18 cm-3, while for DRAM you would go with the highest possible.

  2. Sang Kim Says:

    Sang Kim

    The 4nm finW(fin width) is considered to be the end of FinFET technology road map. Intel’s first 22nm bulk FinFETs are called FD(fully depleted)FinFETs meaning the FinFET channel is un-doped, and the FinFET device currents come predominantly from the fin peripheries or perimeters similar to the planer bulk Si transistors. In this year’s IEDM a fin paper written by 52 Intel Co-authors disclosed that solid source doping was used under the fins in its 2nd generation 14nm FinFET Logic Technology. But it is not clear why the new sub-fin doping is needed. The SEM cross-section report on Intel’s 14nm FinFETs by Dick James of Chipworks shows 8nm finW at the bottom and 42nm high fins. Thus, we have fins with finW=8nm at bottom and finW=4nm at the top with a 42nm hight, and the fin has the solid source doping. The key issue here is why the solid doping is needed under such narrow fins? The overall finW is so narrow between finW=8nm at the bottom and finW=4nm at the top that the volume inversions can take place in this case similar to the double gate transistors, resulting in high device on-currents. The device on-currents in this case, however, no longer comes from the fin peripheries, instead coming from the volume inversions of the very narrow fins.

  3. Sang Kim Says:

    I(Sang Kim) would like to add a couple of sentences at the end of my comment above: At the 4nm node the fin doesn’t exist any more because the fin equal to 4nm at the bottom and 4nm at the top is a rectangle, thus not a fin any more. Therefore, the Intel finFET will end at the 7nm node.

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