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Eliminating the Challenges of Giga-Scale Circuit Design With Nano-Scale Technologies

By Dr. Lianfeng Yang, Vice President of Marketing, ProPlus Design Solutions, Inc., San Jose, Calif.

These days, circuit designers are talking about the increasing giga-scale circuit size. Semiconductor CMOS technology downscaled to nano-scale, forcing the move to make designing for yield (DFY) mandatory and compelling them to re-evaluate how they design and verify their chips.

That’s what brought more than 150 engineers from foundries and fabless semiconductor companies in and around Shanghai, China, in early November to hear a visionary talk from Dr. Chenming Hu, TSMC distinguished professor of the Graduate School at the University of California, Berkeley. Professor Hu, giving the keynote during a ProPlus seminar, offered a perspective on the emerging technology known as 3D FinFET transistor that he and his team invented. It was a great day for all attendees as many of them were able to ask in-depth questions about the challenges at advanced nodes such as 28nm and 16nm.

Dr. Chenming Hu, TSMC distinguished professor of the Graduate School at the University of California, Berkeley talks at the ProPlus seminar.

Professor Hu, this year’s recipient of the Phil Kaufman Award from the IEEE Council for EDA and the EDA Consortium, is a long-time friend and advisor of ProPlus’. Several members of our team, including Zhihong Liu, ProPlus’ executive chairman, were part of a research group he led with Professor Ping K. Ko that invented the first industry-standard MOSFET SPICE model known as BSIM3. (I’ll save the details on this for ProPlus’ next blog.)

One day after the seminar in Shanghai, we were in Taiwan for a similar seminar, though Professor Hu did not join us. This group of engineers gave us a similar assessment of their challenges and ongoing concerns.

The general consensus from both groups is that they would benefit from having more closely integrated modeling, SPICE simulation and DFY technologies. Their perspective is one that is generally shared throughout the semiconductor industry and the EDA industry is starting to respond.

Many of the attendees we talked with over the two days commented on the challenges of good design. That is, modeling small transistors, then putting multi-billion nano-scale transistors together and making it functional, a challenge for the foundries as well because they have to manufacture these small transistors. That’s a function of having good yield.

Process variations create difficulties when accurately modeling nano-scale transistors because they create multi-dimensional uncertainties on device characteristics. Moving to 16- and 14nm nodes, 3D FinFET structure adds in more modeling challenges due to its new structure and complicated parasitics. As such, circuit designers are requested to understand the coverage, usage and limitations of foundry SPICE models.

They’re also challenged with finding the means to put a huge number of elements together. EDA vendors have taken notice here as well because they face the challenge of simulating a large-sized circuit with high enough accuracy and affordable simulation time.

Traditional FastSPICE is showing its age and limitations. The technology trend and advanced circuit designs require highly accurate SPICE simulator that can handle giga-scale size circuit simulations. Parallelization technology is the key, but no commercial SPICE simulator with patched parallel solutions can meet the needs. The trend we see is having a giga-scale SPICE simulator, with parallelization built-in from the ground up delivering giga-scale capacity with no accuracy compromises and significant speedup over traditional SPICE. At 16- and 14nm, FinFET circuit design sizes increase dramatically due to its 3D structure and complex parasitics. Giga-scale SPICE meets such challenges. No small feat, as the circuit designers pointed out.

Using nano-scale elements to design giga-scale circuits presents its own challenges, mainly due to variability, a DFY issue. Having a large amount of extremely small elements –– nanometer-sized transistors –– tightly packed together is a variability nightmare because every tiny variation could cause the function, performance or yield to change on the whole product. Such challenge increases with the technology advancement.

Caption: The design and manufacturing challenges for foundries, fabless design houses and EDA vendors. (Figure sources: Intel Tri-Gate transistors and Intel i7 CPU).

Such variation can be accounted for in the design phase. It’s a matter of how to accurately model small variations, efficiently simulate the large-sized circuit with small variation on each small element, and with variation modeling and simulation capabilities, how to improve designs to achieve optimum performance and yield.

Yes, a huge challenge, but critical for advanced IC designs. Depending on the number of instances to be varied, simulating the impact of variations, essentially Monte Carlo simulation, would require a different number of samplings, ranging from thousands (3σ) to billions (>6σ).

Consequently, the keys here are accurate modeling, giga-scale simulation and advanced high sigma sampling technologies that can reduce the number of sampling by orders of magnitude with the same level of accuracy. FinFET creates additional challenges as it requires very high sigma simulations (e.g., 7σ) for SRAM designs.

The answer as we heard from the circuit designers in China and Taiwan and others is that the only way out of these challenges is to more tightly integrate tools for nano-scale modeling, giga-scale SPICE simulation and DFY.

Dr. Lianfeng Yang currently serves as the Vice President of Marketing at ProPlus Design Solutions, Inc. Prior to co-founding ProPlus, he was a senior product engineer at Cadence Design Systems leading the product engineering and technical support effort for the modeling product line in Asia. Dr. Yang has over 40 publications and holds a Ph.D. degree in Electrical Engineering from the University of Glasgow in the U.K.

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