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Today’s Top Reliability Challenges

By Pete Singer

BTS, BTI, soft errors, dielectric breakdown and other reliability challenges will be addressed at the upcoming International Reliability Physics Symposium.

A double challenge faces today’s reliability engineers. They not only must understand the physics behind a complex set of mechanisms, such as bias temperature instability (BTI), but they must accurately simulate those mechanisms through modeling to predict device performance over time and estimated end-of-life.

These challenges will be front and center at the upcoming International Reliability Physics Symposium (IRPS), to be held April 14-18, 2013 at the Hyatt Regency Monterey Resort & Spa in Monterey, CA. The conference begins with tutorials on Sunday that run through Monday afternoon (40% of attendees are first time attendees). A plenary session on Monday afternoon after the tutorials is a “Year in Review” where experts highlight work published over the last year. Tuesday morning starts with a keynote by Berkeley’s Chenming Hu who will talk about compact modeling as well as tri-gate scaled reliability challenges. Krishnan said that compact modeling is one of the main themes of this year’s conference. “There has been a lot of work on how do we take reliability into the circuits and how do we model, not only at the SPICE level, but from a compact modeling perspective,” he said. The Compact Modeling Council will have a meeting immediately following IRPS at the same location. Tuesday’s keynote is followed by 19 sessions in three tracks, with a panel session, workshop and a combined poster session and buffet at Chateau Julien wine estate on Wednesday evening.

In terms of the overall reliability concerns now facing the industry, Krishnan said the number one thing people are worried about is the tri-gate finFET. “Our devices have been planar but now all of the sudden you have three sides to it. How do you reject the heat from a finFET?” he asks. “The second concern is basically electromigration. How do we scale EM?” The third main challenge lies in gallium nitride and HEMT structures. “What is the reliability of these GaN FETs in the field when you have some of these trapping effects that go on?” Krishnan asks. “The switch is good on day one but it slowly degrades over time. That’s why you’re seeing a lot on GaN FETs.”

A few examples that will be presented at this year’s IRPS will serve to highlight the reliability issues facing the industry.

Reliability in memories

Researchers from Mila Polytechnic, Micron and Intel will present a paper titled “Resolving Discrete Emission Events: a New Perspective for Detrapping Investigation in NAND Flash Memories.” Charlie Slayman, IRPS Vice Technical Program Chair, said that researchers looked at the effects of individual discrete traps in the tunnel oxide for 30nm NAND flash. “Looking at the threshold voltage over time, you can actually see the threshold voltage change in discrete quantized steps. They’ve analyzed this and determined these are individual traps in the device that are trapping and detrapping. This will have an impact on future flash technologies where single electron and defects become increasingly important,” Slayman said.
In a second paper on resistive RAM, authors are from Minatec and coauthors from the Center for Semiconductor Components at the University of Campinas Brazil and the department of electrical engineering at Stanford studied the retention time — the ability of a resistive RAM device to maintain its resistance state. The RAM consists of two metal electrodes and a hafnium oxide between those, where the hafnium oxide acts as a variable resistor. The authors look at the use of different metal materials. In one case they use platinum for the electrode, and in a second example they use a TiN-Ti to sandwich the hafnium oxide. They showed that the Pt/Pt electrode device loses its on-state resistance sooner than the TiN/Ti device. “They attribute the phenomenon to oxygen interstitials in the HfO2, and TiN-Ti’s ability to basically getter those interstitials and pin them at the surface,” Slayman said. This is illustrated in FIGURE 1.

Figure 1. Atomistic structure of HfO2 with an Oi intersitials leading the the recombination of Oi+Vo in Pt/Pt during reset (left). Atomistic structure of Ti awith an Oi interstitial creating more Vo in HfO2 (right).

A third paper on memory focuses on flash, specifically erratic bit classification in flash devices used in automotive applications. The authors studied error correction code and redundant addresses, both of which are widely used in flash as well as SRAM and DRAM memory. “What’s new with this paper is the authors have classified these erratic or bad bits,” Slayman said. FIGURE 2 shows three different types of erratic bits and their behavior over time. “In the first case, they are looking at the read current of one type of erratic bit where it will periodically spike to a higher read current. Then there’s another type of erratic bit they observed where about half the time, it’s in a low read current state and the other half of the time it’s in a high read current state. Then they have a third class of erratic bits where it’s just going back and forth constantly between the high read state and the low read state,” Slaymain explained.

Figure 2. Examples of different erratic bit signatures (left). Normal and erract states are highlighted for clarity. Erratic bits percentage per signature classification in delay time cycling experiments are shown on the right.

Typically, redundant address repair would be used when these bad bits are created, after so many read-write cycles, but that can be an expensive fix. “For a certain class of bad bits — such as the erratic bits on the top of Fig. 3, that are most of the time good and only infrequently bad — don’t bother using redundant address, just use your error correction code and that’s sufficient,” Slayman said. “Save your redundant addresses for the really bad erratic bits.” The authors demonstrated that they can save 35% of their redundancy space by using this classification scheme.

FinFET concerns

At the device level, Giuseppe Larosa, IRPS Technical Program Chair, said the focus in squarely on FinFETs. “For future nodes, 14nm and down to 10nm, FinFETs will be the device design of choice,” he said.

Larosa said one of the key questions people ask is how BTI is actually scaling when we go to finFETs. “Key information is coming from Intel, suggesting that NBTI seems to be an issue because it’s increasing with finFET scaling.” At IRPS, Intel will present a comparison of 32nm planar technology to a 22nm finFET technology, as shown in FIGURE 3 (32 in red and 22nm in blue). “You can see they can manage to really reduce the PBTI but the NBTI is actually getting worse with scaling,” he said.

Figure 3. 22nm BTI is comparable to 32nm. NMOS is significantly improved due to gate optimization and WF scaling. The second item on the list for finFETs is self-heating. "Self-heating is always there," said Larosa. "Anytime you drive current through a channel you produce some self-heating. But if you have a bulk technology, the self-heating will just move away down into the bulk. But in finFETs, because it's a three-dimensional structure, this self-heating is a bottleneck in scaling down."

Another Intel paper talks about the effect of self-heating in accelerating aging, not only at the level of the device in terms of finFETS, but also in terms of metal wires that are sitting on top of the finFET. “You may have some impact on electromigration in the metal wires. You can have enhanced electromigration simply because the self-heating of the finFET can locally increase the temperature in the metal wires above,” Larosa explained. “A key issue here is how to calibrate the self-heating to make sure that you have a good understanding of the local temperature of the structure, and then how to take that into account in your models that predict end-of-life aging, specifically finFETs and metal lines,” he said.

Figure 4. Self-heat manifests as a sensitivity to the fin or gate count in switching aging degradation. Here, switching conditions are accelerated to enhance the sensitivity.

FIGURE 4 shows how self-heating at the device level is affecting aging of a given FET: It’s a function of the number of fins and the number of active lines per transistor. “It looks like through optimization of the gate stack with appropriate oxide scaling and metal gate work function tuning and so on, you can achieve reliability similar to previous nodes,” Larosa said.
Another reliability concern to be discussed at IRPS: High-k dielectrics. “There are two aspects of high k dielectrics that people have to face,” Larosa said. “BTI is again a concern with continued scaling. Contrary to nitride oxides, high-k bring a higher sensitivity to the NFET devices to PBTI. This is mostly due to the fact that the high-k material can be sensitive to electron trap activation or generation, producing PBTI effects that you will not see in standard nitride oxide technologies.”
At IRPS, GLOBALFOUNDRIES will present the first large-scale stochastic BTI (particularly PBTI) study in metal gate/high-k technology confirming fundamental BTI area scaling trends derived from conventional SiO2 technologies, and IBM will report on TDDB in high-k, and how it will lead to more accurate models. “Without this model you cannot be confident in predicting end of life, and having this type of simulation can help in making a projection that will be relevant for product level of circuit level reliability,” Larosa said.

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