Making 3D TSVs more accessible, STATS ChipPAC Ltd. reported Tuesday that it has qualified it’s through silicon via (TSV) capabilities for 300mm mid-end manufacturing operation and transition to low volume manufacturing.  The company said it is working with multiple customers on TSV development programs with current 3D TSV development and customer qualification activities that include devices at the 28nm silicon node, application processors and graphic processors utilizing TSV for the high performance Wide I/O memory interface required by higher bandwidth applications for the mobile market.

Dr. Han Byung Joon, executive vice president and chief technology officer at STATS ChipPAC said in a statement, “The need for higher levels of integration, improved electrical performance, reduced power consumption, faster speed, smaller device sizes and shorter interconnects is forcing a shift to more complex 2.5D and 3D package designs utilizing TSV technology. TSV technology will be a key requirement in the convergence of mobile communication and computing functionality in devices such as smartphones and tablets. This is a trend which is expected to drive rapid growth and adoption of TSV technology.”

The company noted that the mid-end TSV process flow occurs between the wafer fabrication and back-end assembly process supporting the advanced manufacturing requirements of 2.5D and 3D packaging including wafer level, flip chip and embedded technologies and now has mid-end manufacturing capacity in place in Singapore and is working with customers on the production qualification of 2.5D and 3D packaging designs.

Tags: 2.5D, 3D, StatsChipPac, TSVs

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